@inproceedings{63758,
  abstract     = {{Resilient systems require monitoring and prediction of environmental and intrinsic conditions and the ability to adapt to changing circumstances to optimize the trade-off between performance, power consumption, and fault tolerance. TETRISC was introduced as a resilient multicore RISC-V processor system based on the PULPissimo platform. This paper presents the migration of TETRISC to the Rocket Chip SoC, which is freely scalable to the number of processors through parametrizable Chisel models. As such, we discuss and evaluate the main advantages and obstacles that come with the Chipyard framework for RTL simulation and FPGA synthesis for the rapid prototyping of resilient, scalable architectures that are online configurable through software for different multicore and lock-step modes.}},
  author       = {{Hannemann, Kai Arne and Luchterhandt, Lars and Müller, Wolfgang and Ulbricht, Markus and Lu, Li}},
  booktitle    = {{38. ITG / GMM / GI - Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen}},
  keywords     = {{RISC-V, Multicore, Fault Tolerant, TETRISC, Chisel, Chipyard}},
  location     = {{Potsdam}},
  title        = {{{Redesigning the TETRISC Architecture for Scalable Rocket Chip Implementations}}},
  year         = {{2026}},
}

@inproceedings{65595,
  abstract     = {{Resilient systems require monitoring and prediction of environmental and intrinsic conditions, as well as the ability to adapt to environmental hazards while optimizing the trade-off among performance, power consumption, and fault tolerance. TETRISC was introduced as a resilient multicore RISC-V processor system based on the PULPissimo platform. We introduce the migration of TETRISC to the open-source Rocket Chip SoC, targeting scalable TETRISC Chisel implementations. As such, we discuss and evaluate the main advantages and obstacles that come with the Chipyard framework for RTL simulation and FPGA synthesis, enabling rapid prototyping of resilient, scalable architectures configurable for multicore and lockstep modes.}},
  author       = {{Hannemann, Kai Arne and Luchterhandt, Lars and Müller, Wolfgang and Ulbricht, Markus and Lu, Li and Scheytt, J. Christoph}},
  booktitle    = {{29. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2026)}},
  location     = {{Würzburg}},
  title        = {{{TETRISC on Rocket Chip: A Scalable and Adaptive RISC-V Multicore Architecture}}},
  year         = {{2026}},
}

@inproceedings{58861,
  author       = {{Luchterhandt, Lars and Govindasamy, Vivek and Wang, Yutong and Dömer, Rainer and Müller, Wolfgang and Scheytt, J. Christoph}},
  booktitle    = {{OSSMPIC - Open Source Solutions for Massively Parallel Integrated Circuits}},
  title        = {{{Case Study on Combining Open-Source Tool Flows for Grids of Processing Cells}}},
  year         = {{2025}},
}

@inproceedings{66520,
  author       = {{Luchterhandt, Lars and Govindasamy, Vivek and Wang, Yutong and Scheytt, Christoph and Müller, Wolfgang and Dömer, Rainer}},
  booktitle    = {{2025 Forum on Specification & Design Languages (FDL)}},
  publisher    = {{IEEE}},
  title        = {{{A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids}}},
  doi          = {{10.1109/fdl68117.2025.11165408}},
  year         = {{2025}},
}

@inproceedings{45778,
  abstract     = {{RISC-V has received worldwide acceptance in the industry and by the academic community. As of today, multiple
RISC-V applications and variants are under investigation for embedded IoT systems, from resource-limited single-core
processors up to multi-core systems for High-Performance Computing (HPC). Recently, the Grid of Processing Cells
(GPC) platform has been proposed as a scalable parallel grid-oriented network of processor cores with local memories.
This paper describes a prototype design of the GPC platform for hardware implementation at Register-Transfer Level
(RTL) based on modified RISC-V Rocket processors with scratchpad memories. It introduces a scalable Chisel-based
implementation of the modified Rocket cores with RTL generation and a functional test using Verilator simulation. This
work also includes the adaptation of the Chipyard software toolchain to extend the compiler to multi-core grids with
different local address spaces.}},
  author       = {{Luchterhandt, Lars and Nellius, Tom and Beck, Robert and Dömer, Rainer and Kneuper, Pascal and Müller, Wolfgang and Sadiye, Babak}},
  booktitle    = {{MBMV 2024 - 27. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen“}},
  location     = {{Germany,  Freiburg}},
  publisher    = {{VDE Verlag}},
  title        = {{{Implementation of Different Communication Structures for a Rocket Chip Based RISC-V Grid of Processing Cells}}},
  year         = {{2024}},
}

@inproceedings{45775,
  abstract     = {{RISC-V has received worldwide acceptance in the industry and by the academic community. As of today, multiple
RISC-V applications and variants are under investigation for embedded IoT systems, from resource-limited single-core
processors up to multi-core systems for High-Performance Computing (HPC). Recently, the Grid of Processing Cells
(GPC) platform has been proposed as a scalable parallel grid-oriented network of processor cores with local memories.
This paper describes a prototype design of the GPC platform for hardware implementation at Register-Transfer Level
(RTL) based on modified RISC-V Rocket processors with scratchpad memories. It introduces a scalable Chisel-based
implementation of the modified Rocket cores with RTL generation and a functional test using Verilator simulation. This
work also includes the adaptation of the Chipyard software toolchain to extend the compiler to multi-core grids with
different local address spaces.}},
  author       = {{Luchterhandt, Lars and Nellius, Tom and Beck, Robert and Dömer, Rainer and Kneuper, Pascal and Müller, Wolfgang and Sadiye, Babak}},
  booktitle    = {{MBMV 2023 - 26. Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen“, MBMV 2023, Freiburg}},
  location     = {{Freiburg}},
  publisher    = {{VDE Verlag}},
  title        = {{{Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture}}},
  year         = {{2023}},
}