---
_id: '63758'
abstract:
- lang: eng
  text: Resilient systems require monitoring and prediction of environmental and intrinsic
    conditions and the ability to adapt to changing circumstances to optimize the
    trade-off between performance, power consumption, and fault tolerance. TETRISC
    was introduced as a resilient multicore RISC-V processor system based on the PULPissimo
    platform. This paper presents the migration of TETRISC to the Rocket Chip SoC,
    which is freely scalable to the number of processors through parametrizable Chisel
    models. As such, we discuss and evaluate the main advantages and obstacles that
    come with the Chipyard framework for RTL simulation and FPGA synthesis for the
    rapid prototyping of resilient, scalable architectures that are online configurable
    through software for different multicore and lock-step modes.
author:
- first_name: Kai Arne
  full_name: Hannemann, Kai Arne
  id: '63972'
  last_name: Hannemann
- first_name: Lars
  full_name: Luchterhandt, Lars
  id: '74648'
  last_name: Luchterhandt
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Markus
  full_name: Ulbricht, Markus
  last_name: Ulbricht
- first_name: Li
  full_name: Lu, Li
  last_name: Lu
citation:
  ama: 'Hannemann KA, Luchterhandt L, Müller W, Ulbricht M, Lu L. Redesigning the
    TETRISC Architecture for Scalable Rocket Chip Implementations. In: <i>38. ITG
    / GMM / GI - Workshop Testmethoden Und Zuverlässigkeit von Schaltungen Und Systemen</i>.
    ; 2026.'
  apa: Hannemann, K. A., Luchterhandt, L., Müller, W., Ulbricht, M., &#38; Lu, L.
    (2026). Redesigning the TETRISC Architecture for Scalable Rocket Chip Implementations.
    <i>38. ITG / GMM / GI - Workshop Testmethoden Und Zuverlässigkeit von Schaltungen
    Und Systemen</i>. 38. ITG / GMM / GI - Workshop Testmethoden und Zuverlässigkeit
    von Schaltungen und Systemen, Potsdam.
  bibtex: '@inproceedings{Hannemann_Luchterhandt_Müller_Ulbricht_Lu_2026, place={Potsdam},
    title={Redesigning the TETRISC Architecture for Scalable Rocket Chip Implementations},
    booktitle={38. ITG / GMM / GI - Workshop Testmethoden und Zuverlässigkeit von
    Schaltungen und Systemen}, author={Hannemann, Kai Arne and Luchterhandt, Lars
    and Müller, Wolfgang and Ulbricht, Markus and Lu, Li}, year={2026} }'
  chicago: Hannemann, Kai Arne, Lars Luchterhandt, Wolfgang Müller, Markus Ulbricht,
    and Li Lu. “Redesigning the TETRISC Architecture for Scalable Rocket Chip Implementations.”
    In <i>38. ITG / GMM / GI - Workshop Testmethoden Und Zuverlässigkeit von Schaltungen
    Und Systemen</i>. Potsdam, 2026.
  ieee: K. A. Hannemann, L. Luchterhandt, W. Müller, M. Ulbricht, and L. Lu, “Redesigning
    the TETRISC Architecture for Scalable Rocket Chip Implementations,” presented
    at the 38. ITG / GMM / GI - Workshop Testmethoden und Zuverlässigkeit von Schaltungen
    und Systemen, Potsdam, 2026.
  mla: Hannemann, Kai Arne, et al. “Redesigning the TETRISC Architecture for Scalable
    Rocket Chip Implementations.” <i>38. ITG / GMM / GI - Workshop Testmethoden Und
    Zuverlässigkeit von Schaltungen Und Systemen</i>, 2026.
  short: 'K.A. Hannemann, L. Luchterhandt, W. Müller, M. Ulbricht, L. Lu, in: 38.
    ITG / GMM / GI - Workshop Testmethoden Und Zuverlässigkeit von Schaltungen Und
    Systemen, Potsdam, 2026.'
conference:
  end_date: 2026-02-24
  location: Potsdam
  name: 38. ITG / GMM / GI - Workshop Testmethoden und Zuverlässigkeit von Schaltungen
    und Systemen
  start_date: 2026-02-22
date_created: 2026-01-27T13:14:51Z
date_updated: 2026-07-16T11:08:27Z
department:
- _id: '58'
has_accepted_license: '1'
keyword:
- RISC-V
- Multicore
- Fault Tolerant
- TETRISC
- Chisel
- Chipyard
language:
- iso: eng
place: Potsdam
publication: 38. ITG / GMM / GI - Workshop Testmethoden und Zuverlässigkeit von Schaltungen
  und Systemen
status: public
title: Redesigning the TETRISC Architecture for Scalable Rocket Chip Implementations
type: conference
user_id: '63972'
year: '2026'
...
---
_id: '65595'
abstract:
- lang: eng
  text: Resilient systems require monitoring and prediction of environmental and intrinsic
    conditions, as well as the ability to adapt to environmental hazards while optimizing
    the trade-off among performance, power consumption, and fault tolerance. TETRISC
    was introduced as a resilient multicore RISC-V processor system based on the PULPissimo
    platform. We introduce the migration of TETRISC to the open-source Rocket Chip
    SoC, targeting scalable TETRISC Chisel implementations. As such, we discuss and
    evaluate the main advantages and obstacles that come with the Chipyard framework
    for RTL simulation and FPGA synthesis, enabling rapid prototyping of resilient,
    scalable architectures configurable for multicore and lockstep modes.
author:
- first_name: Kai Arne
  full_name: Hannemann, Kai Arne
  id: '63972'
  last_name: Hannemann
- first_name: Lars
  full_name: Luchterhandt, Lars
  id: '74648'
  last_name: Luchterhandt
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Markus
  full_name: Ulbricht, Markus
  last_name: Ulbricht
- first_name: Li
  full_name: Lu, Li
  last_name: Lu
- first_name: J. Christoph
  full_name: Scheytt, J. Christoph
  id: '37144'
  last_name: Scheytt
  orcid: '0000-0002-5950-6618 '
citation:
  ama: 'Hannemann KA, Luchterhandt L, Müller W, Ulbricht M, Lu L, Scheytt JC. TETRISC
    on Rocket Chip: A Scalable and Adaptive RISC-V Multicore Architecture. In: <i>29.
    Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation
    von Schaltungen Und Systemen (MBMV 2026)</i>. ; 2026.'
  apa: 'Hannemann, K. A., Luchterhandt, L., Müller, W., Ulbricht, M., Lu, L., &#38;
    Scheytt, J. C. (2026). TETRISC on Rocket Chip: A Scalable and Adaptive RISC-V
    Multicore Architecture. <i>29. Workshop Methoden Und Beschreibungssprachen Zur
    Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2026)</i>. 29.
    Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation
    von Schaltungen und Systemen (MBMV 2026), Würzburg.'
  bibtex: '@inproceedings{Hannemann_Luchterhandt_Müller_Ulbricht_Lu_Scheytt_2026,
    title={TETRISC on Rocket Chip: A Scalable and Adaptive RISC-V Multicore Architecture},
    booktitle={29. Workshop Methoden und Beschreibungssprachen zur Modellierung und
    Verifikation von Schaltungen und Systemen (MBMV 2026)}, author={Hannemann, Kai
    Arne and Luchterhandt, Lars and Müller, Wolfgang and Ulbricht, Markus and Lu,
    Li and Scheytt, J. Christoph}, year={2026} }'
  chicago: 'Hannemann, Kai Arne, Lars Luchterhandt, Wolfgang Müller, Markus Ulbricht,
    Li Lu, and J. Christoph Scheytt. “TETRISC on Rocket Chip: A Scalable and Adaptive
    RISC-V Multicore Architecture.” In <i>29. Workshop Methoden Und Beschreibungssprachen
    Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2026)</i>,
    2026.'
  ieee: 'K. A. Hannemann, L. Luchterhandt, W. Müller, M. Ulbricht, L. Lu, and J. C.
    Scheytt, “TETRISC on Rocket Chip: A Scalable and Adaptive RISC-V Multicore Architecture,”
    presented at the 29. Workshop Methoden und Beschreibungssprachen zur Modellierung
    und Verifikation von Schaltungen und Systemen (MBMV 2026), Würzburg, 2026.'
  mla: 'Hannemann, Kai Arne, et al. “TETRISC on Rocket Chip: A Scalable and Adaptive
    RISC-V Multicore Architecture.” <i>29. Workshop Methoden Und Beschreibungssprachen
    Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2026)</i>,
    2026.'
  short: 'K.A. Hannemann, L. Luchterhandt, W. Müller, M. Ulbricht, L. Lu, J.C. Scheytt,
    in: 29. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation
    von Schaltungen Und Systemen (MBMV 2026), 2026.'
conference:
  end_date: 2026-03-18
  location: Würzburg
  name: 29. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation
    von Schaltungen und Systemen (MBMV 2026)
  start_date: 2026-03-17
date_created: 2026-05-08T17:18:10Z
date_updated: 2026-07-16T11:05:58Z
department:
- _id: '58'
language:
- iso: eng
publication: 29. Workshop Methoden und Beschreibungssprachen zur Modellierung und
  Verifikation von Schaltungen und Systemen (MBMV 2026)
status: public
title: 'TETRISC on Rocket Chip: A Scalable and Adaptive RISC-V Multicore Architecture'
type: conference
user_id: '63972'
year: '2026'
...
---
_id: '58861'
author:
- first_name: Lars
  full_name: Luchterhandt, Lars
  id: '74648'
  last_name: Luchterhandt
- first_name: Vivek
  full_name: Govindasamy, Vivek
  last_name: Govindasamy
- first_name: Yutong
  full_name: Wang, Yutong
  last_name: Wang
- first_name: Rainer
  full_name: Dömer, Rainer
  last_name: Dömer
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: J. Christoph
  full_name: Scheytt, J. Christoph
  id: '37144'
  last_name: Scheytt
  orcid: '0000-0002-5950-6618 '
citation:
  ama: 'Luchterhandt L, Govindasamy V, Wang Y, Dömer R, Müller W, Scheytt JC. Case
    Study on Combining Open-Source Tool Flows for Grids of Processing Cells. In: <i>OSSMPIC
    - Open Source Solutions for Massively Parallel Integrated Circuits</i>. ; 2025.'
  apa: Luchterhandt, L., Govindasamy, V., Wang, Y., Dömer, R., Müller, W., &#38; Scheytt,
    J. C. (2025). Case Study on Combining Open-Source Tool Flows for Grids of Processing
    Cells. <i>OSSMPIC - Open Source Solutions for Massively Parallel Integrated Circuits</i>.
  bibtex: '@inproceedings{Luchterhandt_Govindasamy_Wang_Dömer_Müller_Scheytt_2025,
    place={Lyon, France}, title={Case Study on Combining Open-Source Tool Flows for
    Grids of Processing Cells}, booktitle={OSSMPIC - Open Source Solutions for Massively
    Parallel Integrated Circuits}, author={Luchterhandt, Lars and Govindasamy, Vivek
    and Wang, Yutong and Dömer, Rainer and Müller, Wolfgang and Scheytt, J. Christoph},
    year={2025} }'
  chicago: Luchterhandt, Lars, Vivek Govindasamy, Yutong Wang, Rainer Dömer, Wolfgang
    Müller, and J. Christoph Scheytt. “Case Study on Combining Open-Source Tool Flows
    for Grids of Processing Cells.” In <i>OSSMPIC - Open Source Solutions for Massively
    Parallel Integrated Circuits</i>. Lyon, France, 2025.
  ieee: L. Luchterhandt, V. Govindasamy, Y. Wang, R. Dömer, W. Müller, and J. C. Scheytt,
    “Case Study on Combining Open-Source Tool Flows for Grids of Processing Cells,”
    2025.
  mla: Luchterhandt, Lars, et al. “Case Study on Combining Open-Source Tool Flows
    for Grids of Processing Cells.” <i>OSSMPIC - Open Source Solutions for Massively
    Parallel Integrated Circuits</i>, 2025.
  short: 'L. Luchterhandt, V. Govindasamy, Y. Wang, R. Dömer, W. Müller, J.C. Scheytt,
    in: OSSMPIC - Open Source Solutions for Massively Parallel Integrated Circuits,
    Lyon, France, 2025.'
date_created: 2025-02-26T14:40:23Z
date_updated: 2026-07-16T14:58:16Z
department:
- _id: '58'
language:
- iso: eng
place: Lyon, France
project:
- _id: '52'
  name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing'
publication: OSSMPIC - Open Source Solutions for Massively Parallel Integrated Circuits
status: public
title: Case Study on Combining Open-Source Tool Flows for Grids of Processing Cells
type: conference
user_id: '16243'
year: '2025'
...
---
_id: '66520'
author:
- first_name: Lars
  full_name: Luchterhandt, Lars
  id: '74648'
  last_name: Luchterhandt
- first_name: Vivek
  full_name: Govindasamy, Vivek
  last_name: Govindasamy
- first_name: Yutong
  full_name: Wang, Yutong
  last_name: Wang
- first_name: Christoph
  full_name: Scheytt, Christoph
  id: '37144'
  last_name: Scheytt
  orcid: '0000-0002-5950-6618 '
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Rainer
  full_name: Dömer, Rainer
  last_name: Dömer
citation:
  ama: 'Luchterhandt L, Govindasamy V, Wang Y, Scheytt C, Müller W, Dömer R. A Quantitative
    Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor
    Grids. In: <i>2025 Forum on Specification &#38;amp;Amp; Design Languages (FDL)</i>.
    IEEE; 2025. doi:<a href="https://doi.org/10.1109/fdl68117.2025.11165408">10.1109/fdl68117.2025.11165408</a>'
  apa: Luchterhandt, L., Govindasamy, V., Wang, Y., Scheytt, C., Müller, W., &#38;
    Dömer, R. (2025). A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in
    System Level Design of RISC-V Processor Grids. <i>2025 Forum on Specification
    &#38;amp;Amp; Design Languages (FDL)</i>. <a href="https://doi.org/10.1109/fdl68117.2025.11165408">https://doi.org/10.1109/fdl68117.2025.11165408</a>
  bibtex: '@inproceedings{Luchterhandt_Govindasamy_Wang_Scheytt_Müller_Dömer_2025,
    title={A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level
    Design of RISC-V Processor Grids}, DOI={<a href="https://doi.org/10.1109/fdl68117.2025.11165408">10.1109/fdl68117.2025.11165408</a>},
    booktitle={2025 Forum on Specification &#38;amp;amp; Design Languages (FDL)},
    publisher={IEEE}, author={Luchterhandt, Lars and Govindasamy, Vivek and Wang,
    Yutong and Scheytt, Christoph and Müller, Wolfgang and Dömer, Rainer}, year={2025}
    }'
  chicago: Luchterhandt, Lars, Vivek Govindasamy, Yutong Wang, Christoph Scheytt,
    Wolfgang Müller, and Rainer Dömer. “A Quantitative Guide to Navigate Speed/Accuracy
    Tradeoffs in System Level Design of RISC-V Processor Grids.” In <i>2025 Forum
    on Specification &#38;amp;Amp; Design Languages (FDL)</i>. IEEE, 2025. <a href="https://doi.org/10.1109/fdl68117.2025.11165408">https://doi.org/10.1109/fdl68117.2025.11165408</a>.
  ieee: 'L. Luchterhandt, V. Govindasamy, Y. Wang, C. Scheytt, W. Müller, and R. Dömer,
    “A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design
    of RISC-V Processor Grids,” 2025, doi: <a href="https://doi.org/10.1109/fdl68117.2025.11165408">10.1109/fdl68117.2025.11165408</a>.'
  mla: Luchterhandt, Lars, et al. “A Quantitative Guide to Navigate Speed/Accuracy
    Tradeoffs in System Level Design of RISC-V Processor Grids.” <i>2025 Forum on
    Specification &#38;amp;Amp; Design Languages (FDL)</i>, IEEE, 2025, doi:<a href="https://doi.org/10.1109/fdl68117.2025.11165408">10.1109/fdl68117.2025.11165408</a>.
  short: 'L. Luchterhandt, V. Govindasamy, Y. Wang, C. Scheytt, W. Müller, R. Dömer,
    in: 2025 Forum on Specification &#38;amp;Amp; Design Languages (FDL), IEEE, 2025.'
date_created: 2026-07-16T15:15:02Z
date_updated: 2026-07-16T15:17:01Z
department:
- _id: '58'
doi: 10.1109/fdl68117.2025.11165408
language:
- iso: eng
publication: 2025 Forum on Specification &amp;amp; Design Languages (FDL)
publication_status: published
publisher: IEEE
status: public
title: A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design
  of RISC-V Processor Grids
type: conference
user_id: '16243'
year: '2025'
...
---
_id: '45778'
abstract:
- lang: eng
  text: "RISC-V has received worldwide acceptance in the industry and by the academic
    community. As of today, multiple\r\nRISC-V applications and variants are under
    investigation for embedded IoT systems, from resource-limited single-core\r\nprocessors
    up to multi-core systems for High-Performance Computing (HPC). Recently, the Grid
    of Processing Cells\r\n(GPC) platform has been proposed as a scalable parallel
    grid-oriented network of processor cores with local memories.\r\nThis paper describes
    a prototype design of the GPC platform for hardware implementation at Register-Transfer
    Level\r\n(RTL) based on modified RISC-V Rocket processors with scratchpad memories.
    It introduces a scalable Chisel-based\r\nimplementation of the modified Rocket
    cores with RTL generation and a functional test using Verilator simulation. This\r\nwork
    also includes the adaptation of the Chipyard software toolchain to extend the
    compiler to multi-core grids with\r\ndifferent local address spaces."
author:
- first_name: Lars
  full_name: Luchterhandt, Lars
  id: '74648'
  last_name: Luchterhandt
- first_name: Tom
  full_name: Nellius, Tom
  last_name: Nellius
- first_name: Robert
  full_name: Beck, Robert
  last_name: Beck
- first_name: Rainer
  full_name: Dömer, Rainer
  last_name: Dömer
- first_name: Pascal
  full_name: Kneuper, Pascal
  id: '47367'
  last_name: Kneuper
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Babak
  full_name: Sadiye, Babak
  id: '93634'
  last_name: Sadiye
citation:
  ama: 'Luchterhandt L, Nellius T, Beck R, et al. Implementation of Different Communication
    Structures for a Rocket Chip Based RISC-V Grid of Processing Cells. In: <i>MBMV
    2024 - 27. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation
    von Schaltungen Und Systemen“</i>. VDE Verlag; 2024.'
  apa: Luchterhandt, L., Nellius, T., Beck, R., Dömer, R., Kneuper, P., Müller, W.,
    &#38; Sadiye, B. (2024). Implementation of Different Communication Structures
    for a Rocket Chip Based RISC-V Grid of Processing Cells. <i>MBMV 2024 - 27. Workshop
    Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen
    Und Systemen“</i>. MBMV 2023 - 26. Workshop, Freiburg, , Germany,  Freiburg.
  bibtex: '@inproceedings{Luchterhandt_Nellius_Beck_Dömer_Kneuper_Müller_Sadiye_2024,
    title={Implementation of Different Communication Structures for a Rocket Chip
    Based RISC-V Grid of Processing Cells}, booktitle={MBMV 2024 - 27. Workshop Methoden
    und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und
    Systemen“}, publisher={VDE Verlag}, author={Luchterhandt, Lars and Nellius, Tom
    and Beck, Robert and Dömer, Rainer and Kneuper, Pascal and Müller, Wolfgang and
    Sadiye, Babak}, year={2024} }'
  chicago: Luchterhandt, Lars, Tom Nellius, Robert Beck, Rainer Dömer, Pascal Kneuper,
    Wolfgang Müller, and Babak Sadiye. “Implementation of Different Communication
    Structures for a Rocket Chip Based RISC-V Grid of Processing Cells.” In <i>MBMV
    2024 - 27. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation
    von Schaltungen Und Systemen“</i>. VDE Verlag, 2024.
  ieee: L. Luchterhandt <i>et al.</i>, “Implementation of Different Communication
    Structures for a Rocket Chip Based RISC-V Grid of Processing Cells,” presented
    at the MBMV 2023 - 26. Workshop, Freiburg, , Germany,  Freiburg, 2024.
  mla: Luchterhandt, Lars, et al. “Implementation of Different Communication Structures
    for a Rocket Chip Based RISC-V Grid of Processing Cells.” <i>MBMV 2024 - 27. Workshop
    Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen
    Und Systemen“</i>, VDE Verlag, 2024.
  short: 'L. Luchterhandt, T. Nellius, R. Beck, R. Dömer, P. Kneuper, W. Müller, B.
    Sadiye, in: MBMV 2024 - 27. Workshop Methoden Und Beschreibungssprachen Zur Modellierung
    Und Verifikation von Schaltungen Und Systemen“, VDE Verlag, 2024.'
conference:
  end_date: 2023.03.24
  location: Germany,  Freiburg
  name: 'MBMV 2023 - 26. Workshop, Freiburg, '
  start_date: 2023.03.23
date_created: 2023-06-26T12:32:07Z
date_updated: 2026-07-16T15:02:40Z
department:
- _id: '58'
language:
- iso: eng
publication: MBMV 2024 - 27. Workshop Methoden und Beschreibungssprachen zur Modellierung
  und Verifikation von Schaltungen und Systemen“
publisher: VDE Verlag
status: public
title: Implementation of Different Communication Structures for a Rocket Chip Based
  RISC-V Grid of Processing Cells
type: conference
user_id: '16243'
year: '2024'
...
---
_id: '45775'
abstract:
- lang: eng
  text: "RISC-V has received worldwide acceptance in the industry and by the academic
    community. As of today, multiple\r\nRISC-V applications and variants are under
    investigation for embedded IoT systems, from resource-limited single-core\r\nprocessors
    up to multi-core systems for High-Performance Computing (HPC). Recently, the Grid
    of Processing Cells\r\n(GPC) platform has been proposed as a scalable parallel
    grid-oriented network of processor cores with local memories.\r\nThis paper describes
    a prototype design of the GPC platform for hardware implementation at Register-Transfer
    Level\r\n(RTL) based on modified RISC-V Rocket processors with scratchpad memories.
    It introduces a scalable Chisel-based\r\nimplementation of the modified Rocket
    cores with RTL generation and a functional test using Verilator simulation. This\r\nwork
    also includes the adaptation of the Chipyard software toolchain to extend the
    compiler to multi-core grids with\r\ndifferent local address spaces."
author:
- first_name: Lars
  full_name: Luchterhandt, Lars
  id: '74648'
  last_name: Luchterhandt
- first_name: Tom
  full_name: Nellius, Tom
  last_name: Nellius
- first_name: Robert
  full_name: Beck, Robert
  last_name: Beck
- first_name: Rainer
  full_name: Dömer, Rainer
  last_name: Dömer
- first_name: Pascal
  full_name: Kneuper, Pascal
  id: '47367'
  last_name: Kneuper
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
- first_name: Babak
  full_name: Sadiye, Babak
  id: '93634'
  last_name: Sadiye
citation:
  ama: 'Luchterhandt L, Nellius T, Beck R, et al. Towards a Rocket Chip Based Implementation
    of the RISC-V GPC Architecture. In: <i>MBMV 2023 - 26. Workshop "Methoden Und
    Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“,
    MBMV 2023, Freiburg</i>. VDE Verlag; 2023.'
  apa: Luchterhandt, L., Nellius, T., Beck, R., Dömer, R., Kneuper, P., Müller, W.,
    &#38; Sadiye, B. (2023). Towards a Rocket Chip Based Implementation of the RISC-V
    GPC Architecture. <i>MBMV 2023 - 26. Workshop "Methoden Und Beschreibungssprachen
    Zur Modellierung Und Verifikation von Schaltungen Und Systemen“, MBMV 2023, Freiburg</i>.
    MBMV 2023, Freiburg, Freiburg.
  bibtex: '@inproceedings{Luchterhandt_Nellius_Beck_Dömer_Kneuper_Müller_Sadiye_2023,
    title={Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture},
    booktitle={MBMV 2023 - 26. Workshop "Methoden und Beschreibungssprachen zur Modellierung
    und Verifikation von Schaltungen und Systemen“, MBMV 2023, Freiburg}, publisher={VDE
    Verlag}, author={Luchterhandt, Lars and Nellius, Tom and Beck, Robert and Dömer,
    Rainer and Kneuper, Pascal and Müller, Wolfgang and Sadiye, Babak}, year={2023}
    }'
  chicago: Luchterhandt, Lars, Tom Nellius, Robert Beck, Rainer Dömer, Pascal Kneuper,
    Wolfgang Müller, and Babak Sadiye. “Towards a Rocket Chip Based Implementation
    of the RISC-V GPC Architecture.” In <i>MBMV 2023 - 26. Workshop "Methoden Und
    Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen“,
    MBMV 2023, Freiburg</i>. VDE Verlag, 2023.
  ieee: L. Luchterhandt <i>et al.</i>, “Towards a Rocket Chip Based Implementation
    of the RISC-V GPC Architecture,” presented at the MBMV 2023, Freiburg, Freiburg,
    2023.
  mla: Luchterhandt, Lars, et al. “Towards a Rocket Chip Based Implementation of the
    RISC-V GPC Architecture.” <i>MBMV 2023 - 26. Workshop "Methoden Und Beschreibungssprachen
    Zur Modellierung Und Verifikation von Schaltungen Und Systemen“, MBMV 2023, Freiburg</i>,
    VDE Verlag, 2023.
  short: 'L. Luchterhandt, T. Nellius, R. Beck, R. Dömer, P. Kneuper, W. Müller, B.
    Sadiye, in: MBMV 2023 - 26. Workshop "Methoden Und Beschreibungssprachen Zur Modellierung
    Und Verifikation von Schaltungen Und Systemen“, MBMV 2023, Freiburg, VDE Verlag,
    2023.'
conference:
  end_date: 2023.03.24
  location: Freiburg
  name: MBMV 2023, Freiburg
  start_date: 2023.03.23
date_created: 2023-06-26T11:47:42Z
date_updated: 2026-07-16T15:01:40Z
language:
- iso: eng
publication: MBMV 2023 - 26. Workshop "Methoden und Beschreibungssprachen zur Modellierung
  und Verifikation von Schaltungen und Systemen“, MBMV 2023, Freiburg
publisher: VDE Verlag
status: public
title: Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture
type: conference
user_id: '16243'
year: '2023'
...