@inproceedings{52743, author = {{Hellebrand, Sybille and Sadeghi-Kohan, Somayeh and Wunderlich, Hans-Joachim}}, booktitle = {{International Symposium of EDA (ISEDA), Xi'an, China, May 10-13, 2024}}, location = {{Xi'an, China}}, pages = {{1}}, title = {{{Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle}}}, year = {{2024}}, } @misc{50284, author = {{Stiballe, Alisa and Reimer, Jan Dennis and Sadeghi-Kohan, Somayeh and Hellebrand, Sybille}}, publisher = {{37. ITG / GMM / GI -Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'24), Feb. 2024}}, title = {{{Modeling Crosstalk-induced Interconnect Delay with Polynomial Regression}}}, year = {{2024}}, } @misc{51799, author = {{Ustimova, Magdalina and Sadeghi-Kohan, Somayeh and Hellebrand, Sybille}}, publisher = {{37. ITG / GMM / GI -Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'24), Feb. 2024}}, title = {{{Crosstalk-Aware Simulation of Interconnects Using Artificial Neural Networks}}}, year = {{2024}}, } @inproceedings{46738, author = {{Sadeghi-Kohan, Somayeh and Reimer, Jan Dennis and Hellebrand, Sybille and Wunderlich, Hans-Joachim}}, booktitle = {{IEEE Asian Test Symposium (ATS'23), October 2023}}, title = {{{Optimizing the Streaming of Sensor Data with Approximate Communication}}}, year = {{2023}}, } @article{46264, abstract = {{System-level interconnects provide the backbone for increasingly complex systems on a chip. Their vulnerability to electromigration and crosstalk can lead to serious reliability and safety issues during the system lifetime. This article presents an approach for periodic in-system testing which maintains a reliability profile to detect potential problems before they actually cause a failure. Relying on a common infrastructure for EM-aware system workload management and test, it minimizes the stress induced by the test itself and contributes to the self-healing of system-induced electromigration degradations. }}, author = {{Sadeghi-Kohan, Somayeh and Hellebrand, Sybille and Wunderlich, Hans-Joachim}}, issn = {{2168-2356}}, journal = {{IEEE Design &Test}}, keywords = {{Electrical and Electronic Engineering, Hardware and Architecture, Software}}, pages = {{1--1}}, publisher = {{Institute of Electrical and Electronics Engineers (IEEE)}}, title = {{{Workload-Aware Periodic Interconnect BIST}}}, doi = {{10.1109/mdat.2023.3298849}}, year = {{2023}}, } @misc{35204, author = {{Ghazal, Abdulkarim and Sadeghi-Kohan, Somayeh and Reimer, Jan Dennis and Hellebrand, Sybille}}, keywords = {{WORKSHOP}}, pages = {{2}}, publisher = {{35. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'23), Feb. 2023}}, title = {{{On Cryptography Effects on Interconnect Reliability}}}, year = {{2023}}, } @inproceedings{41875, author = {{Badran, Abdalrhman and Sadeghi-Kohan, Somayeh and Reimer, Jan Dennis and Hellebrand, Sybille}}, booktitle = {{28th IEEE European Test Symposium (ETS'23), May 2023}}, title = {{{Approximate Computing: Balancing Performance, Power, Reliability, and Safety}}}, year = {{2023}}, } @inproceedings{46739, author = {{Sadeghi-Kohan, Somayeh and Hellebrand, Sybille and Wunderlich, Hans-Joachim}}, booktitle = {{2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)}}, publisher = {{IEEE}}, title = {{{Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication}}}, doi = {{10.1109/dsn-w58399.2023.00056}}, year = {{2023}}, } @article{29351, abstract = {{Safety-critical systems have to follow extremely high dependability requirements as specified in the standards for automotive, air, and space applications. The required high fault coverage at runtime is usually obtained by a combination of concurrent error detection or correction and periodic tests within rather short time intervals. The concurrent scheme ensures the integrity of computed results while the periodic test has to identify potential aging problems and to prevent any fault accumulation which may invalidate the concurrent error detection mechanism. Such periodic built-in self-test (BIST) schemes are already commercialized for memories and for random logic. The paper at hand extends this approach to interconnect structures. A BIST scheme is presented which targets interconnect defects before they will actually affect the system functionality at nominal speed. A BIST schedule is developed which significantly reduces aging caused by electromigration during the lifetime application of the periodic test.}}, author = {{Sadeghi-Kohan, Somayeh and Hellebrand, Sybille and Wunderlich, Hans-Joachim}}, issn = {{0923-8174}}, journal = {{Journal of Electronic Testing}}, keywords = {{Electrical and Electronic Engineering}}, publisher = {{Springer Science and Business Media LLC}}, title = {{{Stress-Aware Periodic Test of Interconnects}}}, doi = {{10.1007/s10836-021-05979-5}}, year = {{2022}}, } @misc{29890, author = {{Sadeghi-Kohan, Somayeh and Hellebrand, Sybille and Wunderlich, Hans-Joachim}}, keywords = {{WORKSHOP}}, pages = {{2}}, publisher = {{European Workshop on Silicon Lifecycle Management, March 18, 2022}}, title = {{{EM-Aware Interconnect BIST}}}, year = {{2022}}, } @inproceedings{19422, author = {{Sprenger, Alexander and Sadeghi-Kohan, Somayeh and Reimer, Jan Dennis and Hellebrand, Sybille}}, booktitle = {{IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020}}, title = {{{Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study}}}, year = {{2020}}, } @misc{15419, author = {{Sadeghi-Kohan, Somayeh and Hellebrand, Sybille}}, keywords = {{WORKSHOP}}, pages = {{4}}, publisher = {{32. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'20), 16. - 18. Februar 2020}}, title = {{{Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects}}}, year = {{2020}}, } @inproceedings{29200, author = {{Sadeghi-Kohan, Somayeh and Hellebrand, Sybille}}, booktitle = {{38th IEEE VLSI Test Symposium (VTS)}}, publisher = {{IEEE}}, title = {{{Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects}}}, doi = {{10.1109/vts48691.2020.9107591}}, year = {{2020}}, } @inproceedings{29460, abstract = {{STT-RAM cells can be considered as an alternative or a hybrid addition to today's SRAM-based cache memories. This is mostly because of their scalability and low leakage power. Moreover, their data storing mechanism (storing the value as resistance) makes them very suitable and applicable for multivalue cache architectures. This feature results in system performance enhancement without any area overhead. On the other hand, the required two-step read/write procedure in multilevel cells results in a non-uniform time access and energy and power overhead on the system. In this paper, we propose a new architecture to dynamically swap data between soft (fast read access) and hard (slow read access) bits in ML cell. Moreover, by reconfiguring cache block size, the proposed architecture can switch between ML and SL modes at runtime. In other words, the swapping method places the hot part of each cache block into soft-bits and the less accessed part into the hard-bits. The SL/ML switching method benefits from the low latency and energy of SL mode and the high storing capacity of ML mode at the same time. Although experimental results show that our proposed method slightly increases the miss rate compared with the conventional ML caches, the performance and energy are improved by 4.9% and 6.5%, respectively. Also, the storage overhead of our method is about 1% that is negligible.}}, author = {{Rezaeizadeh Rookerd, Ramin and Sadeghi-Kohan, Somayeh and Navabi, Zainalabedin}}, booktitle = {{Proceedings of the 2018 on Great Lakes Symposium on VLSI}}, publisher = {{ACM}}, title = {{{Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture}}}, doi = {{10.1145/3194554.3194599}}, year = {{2018}}, } @inproceedings{29459, abstract = {{Transistor and interconnect wearout is accelerated with transistor scaling resulting in timing variations and consequently reliability challenges in digital circuits. With the emergence of new issues like Electro-migration these problems are getting more crucial. Age monitoring methods can be used to predict and deal with the aging problem. Selecting appropriate locations for placement of aging monitors is an important issue. In this work we propose a procedure for selection of appropriate internal nodes that expose smaller overheads to the circuit, using correlation between nodes and the shareability amongst them. To select internal nodes, we first prune some nodes based on some attributes and thus provide a near-optimal solution that can effectively get a number of internal nodes and consider the effects of electro-migration as well. We have applied our proposed scheme to several processors and ITC benchmarks and have looked at its effectiveness for these circuits.}}, author = {{Sadeghi-Kohan, Somayeh and Vafaei, Arash and Navabi, Zainalabedin}}, booktitle = {{2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS)}}, publisher = {{IEEE}}, title = {{{Near-Optimal Node Selection Procedure for Aging Monitor Placement}}}, doi = {{10.1109/iolts.2018.8474120}}, year = {{2018}}, } @article{29462, abstract = {{Time-variant age information of different parts of a system can be used for system-level performance improvement through high-level task scheduling, thus extending the life-time of the system. Progressive age information should provide the age state that the system is in, and the rate that it is being aged at. In this paper, we propose a structure that monitors certain paths of a circuit and detects its gradual age growth, and provides the aging rate and aging state of the circuit. The proposed monitors are placed on a selected set of nodes that represent a timing bottleneck of the system. These monitors sample expected data on these nodes, and compare them with the expected values. The timing of sampling changes as the circuit ages and its delay increases. The timing of sampling will provide a measure of aging advancement of a circuit. To assess the efficacy of the proposed method and compare it with other state-of-the-art aging monitors, we use them on selected nodes of the execution unit of different processors, as well as some circuits from ITC99 benchmarks. The results reveal that the precision of our proposed method is between 0.12 (ns) to 0.401 (ns). Its Area and power overhead are negligible and are about 2.13 and 0.69 percent respectively.}}, author = {{Sadeghi-Kohan, Somayeh and Kamal, Mehdi and Navabi, Zainalabedin}}, issn = {{2168-6750}}, journal = {{IEEE Transactions on Emerging Topics in Computing}}, keywords = {{Age advancement, age monitoring clock, aging rate, self-adjusting monitors}}, number = {{3}}, pages = {{627--641}}, publisher = {{Institute of Electrical and Electronics Engineers (IEEE)}}, title = {{{Self-Adjusting Monitor for Measuring Aging Rate and Advancement}}}, doi = {{10.1109/tetc.2017.2771441}}, volume = {{8}}, year = {{2017}}, } @inproceedings{29463, abstract = {{In this paper we propose to think out of the box and discuss an approach for universal mitigation of Negative Bias Temperature Instability (NBTI) induced aging untied from the limitations of its modelling. The cost-effective approach exploits a simple property of a randomized design, i.e., the equalized signal probability and switching activity at gate inputs. The techniques considered for structural design randomization involve both the hardware architecture and embedded software layers. Ultimately, the proposed approach aims at extending the reliable lifetime of nanoelectronic systems.}}, author = {{Jenihhin, Maksim and Kamkin, Alexander and Navabi, Zainalabedin and Sadeghi-Kohan, Somayeh}}, booktitle = {{2016 IEEE East-West Design & Test Symposium (EWDTS)}}, publisher = {{IEEE}}, title = {{{Universal mitigation of NBTI-induced aging by design randomization}}}, doi = {{10.1109/ewdts.2016.7807635}}, year = {{2017}}, } @inproceedings{29465, abstract = {{Transistor and interconnect wearout is accelerated with transistor scaling resulting in timing variations and consequently reliability challenges in digital circuits. Age monitoring methods can be used to predict and deal with the aging problem. Selecting appropriate locations for placement of hardware aging monitors is an important issue. In this work we propose a procedure for selection of appropriate internal nodes in combinational clouds between pipeline stages or combinational parts of a sequential circuit to place hardware monitors that can effectively provide aging information of various components of a modern digital system. In order to implement the node selection procedure, we propose an object-oriented model. Object-oriented model of a circuit along with a probabilistic and logical simulation engine that we have developed can effectively be used for implementation and also fast evaluation of the proposed node selection mechanism. The proposed object-oriented C+ + models can be integrated into a SystemC RTL model making it possible to perform mixed-level simulation, and integrated evaluation of a complete system. We have applied our proposed scheme to several processors including MIPS, ARM, ALPHA and MiniRISC and have looked at its effectiveness for these processors.}}, author = {{Sadeghi-Kohan, Somayeh and Kamran, Arezoo and Forooghifar, Farnaz and Navabi, Zainalabedin}}, booktitle = {{2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)}}, publisher = {{IEEE}}, title = {{{Aging in digital circuits and age monitoring: Object-oriented modeling and evaluation}}}, doi = {{10.1109/dtis.2015.7127373}}, year = {{2015}}, } @inproceedings{29466, abstract = {{Transistor and interconnect wearout is accelerated with transistor scaling that results in timing variations. Progressive age measurement of a circuit can help a better prevention mechanism for reducing more aging. This requires age monitors that collect progressive age information of the circuit. This paper focuses on monitor structures for implementation of progressive age detection. The monitors are self-adjusting that they adjust themselves to detect progressive changes in the timing of a circuit. Furthermore, the monitors are designed for low hardware overhead, and certainty in reported timing changes.}}, author = {{Sadeghi-Kohan, Somayeh and Kamal, Mehdi and McNeil, John and Prinetto, Paolo and Navabi, Zain}}, booktitle = {{2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)}}, publisher = {{IEEE}}, title = {{{Online self adjusting progressive age monitoring of timing variations}}}, doi = {{10.1109/dtis.2015.7127368}}, year = {{2015}}, } @article{46266, author = {{Alizadeh, Bijan and Behnam, Payman and Sadeghi-Kohan, Somayeh}}, issn = {{0018-9340}}, journal = {{IEEE Transactions on Computers}}, keywords = {{Computational Theory and Mathematics, Hardware and Architecture, Theoretical Computer Science, Software}}, pages = {{1--1}}, publisher = {{Institute of Electrical and Electronics Engineers (IEEE)}}, title = {{{A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs}}}, doi = {{10.1109/tc.2014.2329687}}, year = {{2014}}, }