---
_id: '52743'
author:
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
- first_name: Somayeh
full_name: Sadeghi-Kohan, Somayeh
id: '78614'
last_name: Sadeghi-Kohan
orcid: https://orcid.org/0000-0001-7246-0610
- first_name: Hans-Joachim
full_name: Wunderlich, Hans-Joachim
last_name: Wunderlich
citation:
ama: 'Hellebrand S, Sadeghi-Kohan S, Wunderlich H-J. Functional Safety and Reliability
of Interconnects throughout the Silicon Life Cycle. In: International Symposium
of EDA (ISEDA), Xi’an, China, May 10-13, 2024. ; :1.'
apa: Hellebrand, S., Sadeghi-Kohan, S., & Wunderlich, H.-J. (n.d.). Functional
Safety and Reliability of Interconnects throughout the Silicon Life Cycle. International
Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, 1.
bibtex: '@inproceedings{Hellebrand_Sadeghi-Kohan_Wunderlich, title={Functional Safety
and Reliability of Interconnects throughout the Silicon Life Cycle}, booktitle={International
Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024}, author={Hellebrand,
Sybille and Sadeghi-Kohan, Somayeh and Wunderlich, Hans-Joachim}, pages={1} }'
chicago: Hellebrand, Sybille, Somayeh Sadeghi-Kohan, and Hans-Joachim Wunderlich.
“Functional Safety and Reliability of Interconnects throughout the Silicon Life
Cycle.” In International Symposium of EDA (ISEDA), Xi’an, China, May 10-13,
2024, 1, n.d.
ieee: S. Hellebrand, S. Sadeghi-Kohan, and H.-J. Wunderlich, “Functional Safety
and Reliability of Interconnects throughout the Silicon Life Cycle,” in International
Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024, Xi’an, China, p.
1.
mla: Hellebrand, Sybille, et al. “Functional Safety and Reliability of Interconnects
throughout the Silicon Life Cycle.” International Symposium of EDA (ISEDA),
Xi’an, China, May 10-13, 2024, p. 1.
short: 'S. Hellebrand, S. Sadeghi-Kohan, H.-J. Wunderlich, in: International Symposium
of EDA (ISEDA), Xi’an, China, May 10-13, 2024, n.d., p. 1.'
conference:
end_date: 2024-05-13
location: Xi'an, China
name: International Symposium of EDA (ISEDA)
start_date: 2024-05-10
date_created: 2024-03-22T16:57:53Z
date_updated: 2024-03-22T17:06:02Z
department:
- _id: '48'
language:
- iso: eng
page: '1'
publication: International Symposium of EDA (ISEDA), Xi'an, China, May 10-13, 2024
publication_status: accepted
status: public
title: Functional Safety and Reliability of Interconnects throughout the Silicon Life
Cycle
type: conference
user_id: '209'
year: '2024'
...
---
_id: '50284'
author:
- first_name: Alisa
full_name: Stiballe, Alisa
last_name: Stiballe
- first_name: Jan Dennis
full_name: Reimer, Jan Dennis
id: '36703'
last_name: Reimer
- first_name: Somayeh
full_name: Sadeghi-Kohan, Somayeh
id: '78614'
last_name: Sadeghi-Kohan
orcid: https://orcid.org/0000-0001-7246-0610
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
citation:
ama: Stiballe A, Reimer JD, Sadeghi-Kohan S, Hellebrand S. Modeling Crosstalk-Induced
Interconnect Delay with Polynomial Regression. 37. ITG / GMM / GI -Workshop
“Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’24), Feb.
2024; 2024.
apa: Stiballe, A., Reimer, J. D., Sadeghi-Kohan, S., & Hellebrand, S. (2024).
Modeling Crosstalk-induced Interconnect Delay with Polynomial Regression.
37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen
und Systemen” (TuZ’24), Feb. 2024.
bibtex: '@book{Stiballe_Reimer_Sadeghi-Kohan_Hellebrand_2024, place={Darmstadt,
Germany}, title={Modeling Crosstalk-induced Interconnect Delay with Polynomial
Regression}, publisher={37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit
von Schaltungen und Systemen” (TuZ’24), Feb. 2024}, author={Stiballe, Alisa and
Reimer, Jan Dennis and Sadeghi-Kohan, Somayeh and Hellebrand, Sybille}, year={2024}
}'
chicago: 'Stiballe, Alisa, Jan Dennis Reimer, Somayeh Sadeghi-Kohan, and Sybille
Hellebrand. Modeling Crosstalk-Induced Interconnect Delay with Polynomial Regression.
Darmstadt, Germany: 37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit
von Schaltungen und Systemen” (TuZ’24), Feb. 2024, 2024.'
ieee: 'A. Stiballe, J. D. Reimer, S. Sadeghi-Kohan, and S. Hellebrand, Modeling
Crosstalk-induced Interconnect Delay with Polynomial Regression. Darmstadt,
Germany: 37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen
und Systemen” (TuZ’24), Feb. 2024, 2024.'
mla: Stiballe, Alisa, et al. Modeling Crosstalk-Induced Interconnect Delay with
Polynomial Regression. 37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit
von Schaltungen und Systemen” (TuZ’24), Feb. 2024, 2024.
short: A. Stiballe, J.D. Reimer, S. Sadeghi-Kohan, S. Hellebrand, Modeling Crosstalk-Induced
Interconnect Delay with Polynomial Regression, 37. ITG / GMM / GI -Workshop “Testmethoden
und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’24), Feb. 2024, Darmstadt,
Germany, 2024.
date_created: 2024-01-08T08:47:32Z
date_updated: 2024-03-22T17:12:39Z
department:
- _id: '48'
language:
- iso: eng
place: Darmstadt, Germany
publication_status: published
publisher: 37. ITG / GMM / GI -Workshop "Testmethoden und Zuverlässigkeit von Schaltungen
und Systemen" (TuZ'24), Feb. 2024
status: public
title: Modeling Crosstalk-induced Interconnect Delay with Polynomial Regression
type: misc
user_id: '209'
year: '2024'
...
---
_id: '51799'
author:
- first_name: 'Magdalina '
full_name: 'Ustimova, Magdalina '
last_name: Ustimova
- first_name: Somayeh
full_name: Sadeghi-Kohan, Somayeh
id: '78614'
last_name: Sadeghi-Kohan
orcid: https://orcid.org/0000-0001-7246-0610
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
citation:
ama: Ustimova M, Sadeghi-Kohan S, Hellebrand S. Crosstalk-Aware Simulation of
Interconnects Using Artificial Neural Networks. 37. ITG / GMM / GI -Workshop
“Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’24), Feb.
2024; 2024.
apa: Ustimova, M., Sadeghi-Kohan, S., & Hellebrand, S. (2024). Crosstalk-Aware
Simulation of Interconnects Using Artificial Neural Networks. 37. ITG / GMM
/ GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
(TuZ’24), Feb. 2024.
bibtex: '@book{Ustimova_Sadeghi-Kohan_Hellebrand_2024, place={Darmstadt, Germany},
title={Crosstalk-Aware Simulation of Interconnects Using Artificial Neural Networks},
publisher={37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von
Schaltungen und Systemen” (TuZ’24), Feb. 2024}, author={Ustimova, Magdalina and
Sadeghi-Kohan, Somayeh and Hellebrand, Sybille}, year={2024} }'
chicago: 'Ustimova, Magdalina , Somayeh Sadeghi-Kohan, and Sybille Hellebrand. Crosstalk-Aware
Simulation of Interconnects Using Artificial Neural Networks. Darmstadt, Germany:
37. ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen
und Systemen” (TuZ’24), Feb. 2024, 2024.'
ieee: 'M. Ustimova, S. Sadeghi-Kohan, and S. Hellebrand, Crosstalk-Aware Simulation
of Interconnects Using Artificial Neural Networks. Darmstadt, Germany: 37.
ITG / GMM / GI -Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und
Systemen” (TuZ’24), Feb. 2024, 2024.'
mla: Ustimova, Magdalina, et al. Crosstalk-Aware Simulation of Interconnects
Using Artificial Neural Networks. 37. ITG / GMM / GI -Workshop “Testmethoden
und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’24), Feb. 2024, 2024.
short: M. Ustimova, S. Sadeghi-Kohan, S. Hellebrand, Crosstalk-Aware Simulation
of Interconnects Using Artificial Neural Networks, 37. ITG / GMM / GI -Workshop
“Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’24), Feb.
2024, Darmstadt, Germany, 2024.
date_created: 2024-02-23T12:07:20Z
date_updated: 2024-03-22T17:12:00Z
language:
- iso: eng
place: Darmstadt, Germany
publication_status: published
publisher: 37. ITG / GMM / GI -Workshop "Testmethoden und Zuverlässigkeit von Schaltungen
und Systemen" (TuZ'24), Feb. 2024
status: public
title: Crosstalk-Aware Simulation of Interconnects Using Artificial Neural Networks
type: misc
user_id: '209'
year: '2024'
...
---
_id: '46738'
author:
- first_name: Somayeh
full_name: Sadeghi-Kohan, Somayeh
id: '78614'
last_name: Sadeghi-Kohan
orcid: https://orcid.org/0000-0001-7246-0610
- first_name: Jan Dennis
full_name: Reimer, Jan Dennis
id: '36703'
last_name: Reimer
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
- first_name: Hans-Joachim
full_name: Wunderlich, Hans-Joachim
last_name: Wunderlich
citation:
ama: 'Sadeghi-Kohan S, Reimer JD, Hellebrand S, Wunderlich H-J. Optimizing the Streaming
of Sensor Data with Approximate Communication. In: IEEE Asian Test Symposium
(ATS’23), October 2023. ; 2023.'
apa: Sadeghi-Kohan, S., Reimer, J. D., Hellebrand, S., & Wunderlich, H.-J. (2023).
Optimizing the Streaming of Sensor Data with Approximate Communication. IEEE
Asian Test Symposium (ATS’23), October 2023. IEEE Asian Test Symposium (ATS’23).
bibtex: '@inproceedings{Sadeghi-Kohan_Reimer_Hellebrand_Wunderlich_2023, place={Beijing,
China}, title={Optimizing the Streaming of Sensor Data with Approximate Communication},
booktitle={IEEE Asian Test Symposium (ATS’23), October 2023}, author={Sadeghi-Kohan,
Somayeh and Reimer, Jan Dennis and Hellebrand, Sybille and Wunderlich, Hans-Joachim},
year={2023} }'
chicago: Sadeghi-Kohan, Somayeh, Jan Dennis Reimer, Sybille Hellebrand, and Hans-Joachim
Wunderlich. “Optimizing the Streaming of Sensor Data with Approximate Communication.”
In IEEE Asian Test Symposium (ATS’23), October 2023. Beijing, China, 2023.
ieee: S. Sadeghi-Kohan, J. D. Reimer, S. Hellebrand, and H.-J. Wunderlich, “Optimizing
the Streaming of Sensor Data with Approximate Communication,” presented at the
IEEE Asian Test Symposium (ATS’23), 2023.
mla: Sadeghi-Kohan, Somayeh, et al. “Optimizing the Streaming of Sensor Data with
Approximate Communication.” IEEE Asian Test Symposium (ATS’23), October 2023,
2023.
short: 'S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, H.-J. Wunderlich, in: IEEE
Asian Test Symposium (ATS’23), October 2023, Beijing, China, 2023.'
conference:
end_date: 2023-10-17
name: IEEE Asian Test Symposium (ATS'23)
start_date: 2023-10-14
date_created: 2023-08-26T08:47:52Z
date_updated: 2024-01-08T08:49:08Z
department:
- _id: '48'
language:
- iso: eng
place: Beijing, China
publication: IEEE Asian Test Symposium (ATS'23), October 2023
status: public
title: Optimizing the Streaming of Sensor Data with Approximate Communication
type: conference
user_id: '36703'
year: '2023'
...
---
_id: '46264'
abstract:
- lang: eng
text: "System-level interconnects provide the\r\nbackbone for increasingly complex
systems on a chip. Their\r\nvulnerability to electromigration and crosstalk can
lead to\r\nserious reliability and safety issues during the system lifetime.\r\nThis
article presents an approach for periodic in-system testing\r\nwhich maintains
a reliability profile to detect potential\r\nproblems before they actually cause
a failure. Relying on a\r\ncommon infrastructure for EM-aware system workload\r\nmanagement
and test, it minimizes the stress induced by the\r\ntest itself and contributes
to the self-healing of system-induced\r\nelectromigration degradations. "
article_type: original
author:
- first_name: Somayeh
full_name: Sadeghi-Kohan, Somayeh
id: '78614'
last_name: Sadeghi-Kohan
orcid: https://orcid.org/0000-0001-7246-0610
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
- first_name: Hans-Joachim
full_name: Wunderlich, Hans-Joachim
last_name: Wunderlich
citation:
ama: Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. Workload-Aware Periodic Interconnect
BIST. IEEE Design &Test. Published online 2023:1-1. doi:10.1109/mdat.2023.3298849
apa: Sadeghi-Kohan, S., Hellebrand, S., & Wunderlich, H.-J. (2023). Workload-Aware
Periodic Interconnect BIST. IEEE Design &Test, 1–1. https://doi.org/10.1109/mdat.2023.3298849
bibtex: '@article{Sadeghi-Kohan_Hellebrand_Wunderlich_2023, title={Workload-Aware
Periodic Interconnect BIST}, DOI={10.1109/mdat.2023.3298849},
journal={IEEE Design &Test}, publisher={Institute of Electrical and Electronics
Engineers (IEEE)}, author={Sadeghi-Kohan, Somayeh and Hellebrand, Sybille and
Wunderlich, Hans-Joachim}, year={2023}, pages={1–1} }'
chicago: Sadeghi-Kohan, Somayeh, Sybille Hellebrand, and Hans-Joachim Wunderlich.
“Workload-Aware Periodic Interconnect BIST.” IEEE Design &Test, 2023,
1–1. https://doi.org/10.1109/mdat.2023.3298849.
ieee: 'S. Sadeghi-Kohan, S. Hellebrand, and H.-J. Wunderlich, “Workload-Aware Periodic
Interconnect BIST,” IEEE Design &Test, pp. 1–1, 2023, doi: 10.1109/mdat.2023.3298849.'
mla: Sadeghi-Kohan, Somayeh, et al. “Workload-Aware Periodic Interconnect BIST.”
IEEE Design &Test, Institute of Electrical and Electronics Engineers
(IEEE), 2023, pp. 1–1, doi:10.1109/mdat.2023.3298849.
short: S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, IEEE Design &Test
(2023) 1–1.
date_created: 2023-08-02T11:07:43Z
date_updated: 2024-03-22T17:15:10Z
department:
- _id: '48'
doi: 10.1109/mdat.2023.3298849
keyword:
- Electrical and Electronic Engineering
- Hardware and Architecture
- Software
language:
- iso: eng
main_file_link:
- url: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10194315
page: 1-1
publication: IEEE Design &Test
publication_identifier:
issn:
- 2168-2356
- 2168-2364
publication_status: published
publisher: Institute of Electrical and Electronics Engineers (IEEE)
status: public
title: Workload-Aware Periodic Interconnect BIST
type: journal_article
user_id: '209'
year: '2023'
...
---
_id: '35204'
author:
- first_name: Abdulkarim
full_name: Ghazal, Abdulkarim
last_name: Ghazal
- first_name: Somayeh
full_name: Sadeghi-Kohan, Somayeh
id: '78614'
last_name: Sadeghi-Kohan
- first_name: Jan Dennis
full_name: Reimer, Jan Dennis
id: '36703'
last_name: Reimer
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
citation:
ama: Ghazal A, Sadeghi-Kohan S, Reimer JD, Hellebrand S. On Cryptography Effects
on Interconnect Reliability. 35. Workshop “Testmethoden und Zuverlässigkeit
von Schaltungen und Systemen” (TuZ’23), Feb. 2023; 2023.
apa: Ghazal, A., Sadeghi-Kohan, S., Reimer, J. D., & Hellebrand, S. (2023).
On Cryptography Effects on Interconnect Reliability. 35. Workshop “Testmethoden
und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023.
bibtex: '@book{Ghazal_Sadeghi-Kohan_Reimer_Hellebrand_2023, place={Erfurt, Germany},
title={On Cryptography Effects on Interconnect Reliability}, publisher={35. Workshop
“Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb.
2023}, author={Ghazal, Abdulkarim and Sadeghi-Kohan, Somayeh and Reimer, Jan Dennis
and Hellebrand, Sybille}, year={2023} }'
chicago: 'Ghazal, Abdulkarim, Somayeh Sadeghi-Kohan, Jan Dennis Reimer, and Sybille
Hellebrand. On Cryptography Effects on Interconnect Reliability. Erfurt,
Germany: 35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
(TuZ’23), Feb. 2023, 2023.'
ieee: 'A. Ghazal, S. Sadeghi-Kohan, J. D. Reimer, and S. Hellebrand, On Cryptography
Effects on Interconnect Reliability. Erfurt, Germany: 35. Workshop “Testmethoden
und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23), Feb. 2023, 2023.'
mla: Ghazal, Abdulkarim, et al. On Cryptography Effects on Interconnect Reliability.
35. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’23),
Feb. 2023, 2023.
short: A. Ghazal, S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, On Cryptography
Effects on Interconnect Reliability, 35. Workshop “Testmethoden und Zuverlässigkeit
von Schaltungen und Systemen” (TuZ’23), Feb. 2023, Erfurt, Germany, 2023.
date_created: 2023-01-04T10:20:41Z
date_updated: 2023-04-06T21:06:37Z
department:
- _id: '48'
keyword:
- WORKSHOP
language:
- iso: eng
page: '2'
place: Erfurt, Germany
publisher: 35. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen"
(TuZ'23), Feb. 2023
status: public
title: On Cryptography Effects on Interconnect Reliability
type: misc
user_id: '36703'
year: '2023'
...
---
_id: '41875'
author:
- first_name: 'Abdalrhman '
full_name: 'Badran, Abdalrhman '
last_name: Badran
- first_name: Somayeh
full_name: Sadeghi-Kohan, Somayeh
id: '78614'
last_name: Sadeghi-Kohan
- first_name: Jan Dennis
full_name: Reimer, Jan Dennis
id: '36703'
last_name: Reimer
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
citation:
ama: 'Badran A, Sadeghi-Kohan S, Reimer JD, Hellebrand S. Approximate Computing:
Balancing Performance, Power, Reliability, and Safety. In: 28th IEEE European
Test Symposium (ETS’23), May 2023. ; 2023.'
apa: 'Badran, A., Sadeghi-Kohan, S., Reimer, J. D., & Hellebrand, S. (2023).
Approximate Computing: Balancing Performance, Power, Reliability, and Safety.
28th IEEE European Test Symposium (ETS’23), May 2023.'
bibtex: '@inproceedings{Badran_Sadeghi-Kohan_Reimer_Hellebrand_2023, place={Venice,
Italy}, title={Approximate Computing: Balancing Performance, Power, Reliability,
and Safety}, booktitle={28th IEEE European Test Symposium (ETS’23), May 2023},
author={Badran, Abdalrhman and Sadeghi-Kohan, Somayeh and Reimer, Jan Dennis
and Hellebrand, Sybille}, year={2023} }'
chicago: 'Badran, Abdalrhman , Somayeh Sadeghi-Kohan, Jan Dennis Reimer, and Sybille
Hellebrand. “Approximate Computing: Balancing Performance, Power, Reliability,
and Safety.” In 28th IEEE European Test Symposium (ETS’23), May 2023. Venice,
Italy, 2023.'
ieee: 'A. Badran, S. Sadeghi-Kohan, J. D. Reimer, and S. Hellebrand, “Approximate
Computing: Balancing Performance, Power, Reliability, and Safety,” 2023.'
mla: 'Badran, Abdalrhman, et al. “Approximate Computing: Balancing Performance,
Power, Reliability, and Safety.” 28th IEEE European Test Symposium (ETS’23),
May 2023, 2023.'
short: 'A. Badran, S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, in: 28th IEEE European
Test Symposium (ETS’23), May 2023, Venice, Italy, 2023.'
conference:
end_date: 2023-05-26
start_date: 2023-05-22
date_created: 2023-02-07T13:57:34Z
date_updated: 2023-06-19T14:21:47Z
language:
- iso: eng
place: Venice, Italy
publication: 28th IEEE European Test Symposium (ETS'23), May 2023
status: public
title: 'Approximate Computing: Balancing Performance, Power, Reliability, and Safety'
type: conference
user_id: '36703'
year: '2023'
...
---
_id: '46739'
author:
- first_name: Somayeh
full_name: Sadeghi-Kohan, Somayeh
id: '78614'
last_name: Sadeghi-Kohan
orcid: https://orcid.org/0000-0001-7246-0610
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
- first_name: Hans-Joachim
full_name: Wunderlich, Hans-Joachim
last_name: Wunderlich
citation:
ama: 'Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. Low Power Streaming of Sensor
Data Using Gray Code-Based Approximate Communication. In: 2023 53rd Annual
IEEE/IFIP International Conference on Dependable Systems and Networks Workshops
(DSN-W). IEEE; 2023. doi:10.1109/dsn-w58399.2023.00056'
apa: Sadeghi-Kohan, S., Hellebrand, S., & Wunderlich, H.-J. (2023). Low Power
Streaming of Sensor Data Using Gray Code-Based Approximate Communication. 2023
53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks
Workshops (DSN-W). https://doi.org/10.1109/dsn-w58399.2023.00056
bibtex: '@inproceedings{Sadeghi-Kohan_Hellebrand_Wunderlich_2023, title={Low Power
Streaming of Sensor Data Using Gray Code-Based Approximate Communication}, DOI={10.1109/dsn-w58399.2023.00056},
booktitle={2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems
and Networks Workshops (DSN-W)}, publisher={IEEE}, author={Sadeghi-Kohan, Somayeh
and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2023} }'
chicago: Sadeghi-Kohan, Somayeh, Sybille Hellebrand, and Hans-Joachim Wunderlich.
“Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication.”
In 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems
and Networks Workshops (DSN-W). IEEE, 2023. https://doi.org/10.1109/dsn-w58399.2023.00056.
ieee: 'S. Sadeghi-Kohan, S. Hellebrand, and H.-J. Wunderlich, “Low Power Streaming
of Sensor Data Using Gray Code-Based Approximate Communication,” 2023, doi: 10.1109/dsn-w58399.2023.00056.'
mla: Sadeghi-Kohan, Somayeh, et al. “Low Power Streaming of Sensor Data Using Gray
Code-Based Approximate Communication.” 2023 53rd Annual IEEE/IFIP International
Conference on Dependable Systems and Networks Workshops (DSN-W), IEEE, 2023,
doi:10.1109/dsn-w58399.2023.00056.
short: 'S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, in: 2023 53rd Annual
IEEE/IFIP International Conference on Dependable Systems and Networks Workshops
(DSN-W), IEEE, 2023.'
date_created: 2023-08-26T10:48:31Z
date_updated: 2023-08-26T10:49:07Z
department:
- _id: '48'
doi: 10.1109/dsn-w58399.2023.00056
language:
- iso: eng
publication: 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems
and Networks Workshops (DSN-W)
publication_status: published
publisher: IEEE
status: public
title: Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication
type: conference
user_id: '78614'
year: '2023'
...
---
_id: '29351'
abstract:
- lang: eng
text: Safety-critical systems have to follow extremely high dependability requirements
as specified in the standards for automotive, air, and space applications. The
required high fault coverage at runtime is usually obtained by a combination of
concurrent error detection or correction and periodic tests within rather short
time intervals. The concurrent scheme ensures the integrity of computed results
while the periodic test has to identify potential aging problems and to prevent
any fault accumulation which may invalidate the concurrent error detection mechanism.
Such periodic built-in self-test (BIST) schemes are already commercialized for
memories and for random logic. The paper at hand extends this approach to interconnect
structures. A BIST scheme is presented which targets interconnect defects before
they will actually affect the system functionality at nominal speed. A BIST schedule
is developed which significantly reduces aging caused by electromigration during
the lifetime application of the periodic test.
article_type: original
author:
- first_name: Somayeh
full_name: Sadeghi-Kohan, Somayeh
id: '78614'
last_name: Sadeghi-Kohan
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
- first_name: Hans-Joachim
full_name: Wunderlich, Hans-Joachim
last_name: Wunderlich
citation:
ama: Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. Stress-Aware Periodic Test of
Interconnects. Journal of Electronic Testing. Published online 2022. doi:10.1007/s10836-021-05979-5
apa: Sadeghi-Kohan, S., Hellebrand, S., & Wunderlich, H.-J. (2022). Stress-Aware
Periodic Test of Interconnects. Journal of Electronic Testing. https://doi.org/10.1007/s10836-021-05979-5
bibtex: '@article{Sadeghi-Kohan_Hellebrand_Wunderlich_2022, title={Stress-Aware
Periodic Test of Interconnects}, DOI={10.1007/s10836-021-05979-5},
journal={Journal of Electronic Testing}, publisher={Springer Science and Business
Media LLC}, author={Sadeghi-Kohan, Somayeh and Hellebrand, Sybille and Wunderlich,
Hans-Joachim}, year={2022} }'
chicago: Sadeghi-Kohan, Somayeh, Sybille Hellebrand, and Hans-Joachim Wunderlich.
“Stress-Aware Periodic Test of Interconnects.” Journal of Electronic Testing,
2022. https://doi.org/10.1007/s10836-021-05979-5.
ieee: 'S. Sadeghi-Kohan, S. Hellebrand, and H.-J. Wunderlich, “Stress-Aware Periodic
Test of Interconnects,” Journal of Electronic Testing, 2022, doi: 10.1007/s10836-021-05979-5.'
mla: Sadeghi-Kohan, Somayeh, et al. “Stress-Aware Periodic Test of Interconnects.”
Journal of Electronic Testing, Springer Science and Business Media LLC,
2022, doi:10.1007/s10836-021-05979-5.
short: S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, Journal of Electronic
Testing (2022).
date_created: 2022-01-14T11:16:34Z
date_updated: 2022-05-11T16:10:01Z
department:
- _id: '48'
doi: 10.1007/s10836-021-05979-5
keyword:
- Electrical and Electronic Engineering
language:
- iso: eng
publication: Journal of Electronic Testing
publication_identifier:
issn:
- 0923-8174
- 1573-0727
publication_status: published
publisher: Springer Science and Business Media LLC
status: public
title: Stress-Aware Periodic Test of Interconnects
type: journal_article
user_id: '209'
year: '2022'
...
---
_id: '29890'
author:
- first_name: Somayeh
full_name: Sadeghi-Kohan, Somayeh
id: '78614'
last_name: Sadeghi-Kohan
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
- first_name: Hans-Joachim
full_name: Wunderlich, Hans-Joachim
last_name: Wunderlich
citation:
ama: Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. EM-Aware Interconnect BIST.
European Workshop on Silicon Lifecycle Management, March 18, 2022; 2022.
apa: Sadeghi-Kohan, S., Hellebrand, S., & Wunderlich, H.-J. (2022). EM-Aware
Interconnect BIST. European Workshop on Silicon Lifecycle Management, March
18, 2022.
bibtex: '@book{Sadeghi-Kohan_Hellebrand_Wunderlich_2022, place={Online}, title={EM-Aware
Interconnect BIST}, publisher={European Workshop on Silicon Lifecycle Management,
March 18, 2022}, author={Sadeghi-Kohan, Somayeh and Hellebrand, Sybille and Wunderlich,
Hans-Joachim}, year={2022} }'
chicago: 'Sadeghi-Kohan, Somayeh, Sybille Hellebrand, and Hans-Joachim Wunderlich.
EM-Aware Interconnect BIST. Online: European Workshop on Silicon Lifecycle
Management, March 18, 2022, 2022.'
ieee: 'S. Sadeghi-Kohan, S. Hellebrand, and H.-J. Wunderlich, EM-Aware Interconnect
BIST. Online: European Workshop on Silicon Lifecycle Management, March 18,
2022, 2022.'
mla: Sadeghi-Kohan, Somayeh, et al. EM-Aware Interconnect BIST. European
Workshop on Silicon Lifecycle Management, March 18, 2022, 2022.
short: S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, EM-Aware Interconnect
BIST, European Workshop on Silicon Lifecycle Management, March 18, 2022, Online,
2022.
date_created: 2022-02-19T14:21:24Z
date_updated: 2022-05-11T17:07:24Z
department:
- _id: '48'
keyword:
- WORKSHOP
language:
- iso: eng
page: '2'
place: Online
publication_status: published
publisher: European Workshop on Silicon Lifecycle Management, March 18, 2022
status: public
title: EM-Aware Interconnect BIST
type: misc
user_id: '209'
year: '2022'
...
---
_id: '19422'
author:
- first_name: Alexander
full_name: Sprenger, Alexander
id: '22707'
last_name: Sprenger
- first_name: Somayeh
full_name: Sadeghi-Kohan, Somayeh
id: '78614'
last_name: Sadeghi-Kohan
- first_name: Jan Dennis
full_name: Reimer, Jan Dennis
id: '36703'
last_name: Reimer
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
citation:
ama: 'Sprenger A, Sadeghi-Kohan S, Reimer JD, Hellebrand S. Variation-Aware Test
for Logic Interconnects using Neural Networks - A Case Study. In: IEEE International
Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20),
October 2020. ; 2020.'
apa: Sprenger, A., Sadeghi-Kohan, S., Reimer, J. D., & Hellebrand, S. (2020).
Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study.
IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology
Systems (DFT’20), October 2020.
bibtex: '@inproceedings{Sprenger_Sadeghi-Kohan_Reimer_Hellebrand_2020, place={Virtual
Conference - Originally Frascati (Rome), Italy}, title={Variation-Aware Test for
Logic Interconnects using Neural Networks - A Case Study}, booktitle={IEEE International
Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20),
October 2020}, author={Sprenger, Alexander and Sadeghi-Kohan, Somayeh and Reimer,
Jan Dennis and Hellebrand, Sybille}, year={2020} }'
chicago: Sprenger, Alexander, Somayeh Sadeghi-Kohan, Jan Dennis Reimer, and Sybille
Hellebrand. “Variation-Aware Test for Logic Interconnects Using Neural Networks
- A Case Study.” In IEEE International Symposium on Defect and Fault Tolerance
in VLSI and Nanotechnology Systems (DFT’20), October 2020. Virtual Conference
- Originally Frascati (Rome), Italy, 2020.
ieee: A. Sprenger, S. Sadeghi-Kohan, J. D. Reimer, and S. Hellebrand, “Variation-Aware
Test for Logic Interconnects using Neural Networks - A Case Study,” 2020.
mla: Sprenger, Alexander, et al. “Variation-Aware Test for Logic Interconnects Using
Neural Networks - A Case Study.” IEEE International Symposium on Defect and
Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020,
2020.
short: 'A. Sprenger, S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, in: IEEE International
Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20),
October 2020, Virtual Conference - Originally Frascati (Rome), Italy, 2020.'
conference:
end_date: 2020-10-21
start_date: 2020-10-19
date_created: 2020-09-15T14:03:02Z
date_updated: 2022-02-19T14:16:58Z
department:
- _id: '48'
language:
- iso: eng
place: Virtual Conference - Originally Frascati (Rome), Italy
publication: IEEE International Symposium on Defect and Fault Tolerance in VLSI and
Nanotechnology Systems (DFT’20), October 2020
publication_status: published
status: public
title: Variation-Aware Test for Logic Interconnects using Neural Networks - A Case
Study
type: conference
user_id: '209'
year: '2020'
...
---
_id: '15419'
author:
- first_name: Somayeh
full_name: Sadeghi-Kohan, Somayeh
id: '78614'
last_name: Sadeghi-Kohan
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
citation:
ama: Sadeghi-Kohan S, Hellebrand S. Dynamic Multi-Frequency Test Method for Hidden
Interconnect Defects. 32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen
und Systemen” (TuZ’20), 16. - 18. Februar 2020; 2020.
apa: Sadeghi-Kohan, S., & Hellebrand, S. (2020). Dynamic Multi-Frequency
Test Method for Hidden Interconnect Defects. 32. Workshop “Testmethoden und
Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020.
bibtex: '@book{Sadeghi-Kohan_Hellebrand_2020, place={Ludwigsburg}, title={Dynamic
Multi-Frequency Test Method for Hidden Interconnect Defects}, publisher={32. Workshop
“Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16.
- 18. Februar 2020}, author={Sadeghi-Kohan, Somayeh and Hellebrand, Sybille},
year={2020} }'
chicago: 'Sadeghi-Kohan, Somayeh, and Sybille Hellebrand. Dynamic Multi-Frequency
Test Method for Hidden Interconnect Defects. Ludwigsburg: 32. Workshop “Testmethoden
und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar
2020, 2020.'
ieee: 'S. Sadeghi-Kohan and S. Hellebrand, Dynamic Multi-Frequency Test Method
for Hidden Interconnect Defects. Ludwigsburg: 32. Workshop “Testmethoden und
Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020,
2020.'
mla: Sadeghi-Kohan, Somayeh, and Sybille Hellebrand. Dynamic Multi-Frequency
Test Method for Hidden Interconnect Defects. 32. Workshop “Testmethoden und
Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020,
2020.
short: S. Sadeghi-Kohan, S. Hellebrand, Dynamic Multi-Frequency Test Method for
Hidden Interconnect Defects, 32. Workshop “Testmethoden und Zuverlässigkeit von
Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020, Ludwigsburg, 2020.
date_created: 2019-12-29T16:13:58Z
date_updated: 2022-04-04T12:30:02Z
department:
- _id: '48'
keyword:
- WORKSHOP
language:
- iso: eng
page: '4'
place: Ludwigsburg
publication_status: published
publisher: 32. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen"
(TuZ'20), 16. - 18. Februar 2020
status: public
title: Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects
type: misc
user_id: '209'
year: '2020'
...
---
_id: '29200'
author:
- first_name: Somayeh
full_name: Sadeghi-Kohan, Somayeh
id: '78614'
last_name: Sadeghi-Kohan
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
citation:
ama: 'Sadeghi-Kohan S, Hellebrand S. Dynamic Multi-Frequency Test Method for Hidden
Interconnect Defects. In: 38th IEEE VLSI Test Symposium (VTS). IEEE; 2020.
doi:10.1109/vts48691.2020.9107591'
apa: Sadeghi-Kohan, S., & Hellebrand, S. (2020). Dynamic Multi-Frequency Test
Method for Hidden Interconnect Defects. 38th IEEE VLSI Test Symposium (VTS).
https://doi.org/10.1109/vts48691.2020.9107591
bibtex: '@inproceedings{Sadeghi-Kohan_Hellebrand_2020, place={Virtual Conference
- Originally San Diego, CA, USA}, title={Dynamic Multi-Frequency Test Method for
Hidden Interconnect Defects}, DOI={10.1109/vts48691.2020.9107591},
booktitle={38th IEEE VLSI Test Symposium (VTS)}, publisher={IEEE}, author={Sadeghi-Kohan,
Somayeh and Hellebrand, Sybille}, year={2020} }'
chicago: 'Sadeghi-Kohan, Somayeh, and Sybille Hellebrand. “Dynamic Multi-Frequency
Test Method for Hidden Interconnect Defects.” In 38th IEEE VLSI Test Symposium
(VTS). Virtual Conference - Originally San Diego, CA, USA: IEEE, 2020. https://doi.org/10.1109/vts48691.2020.9107591.'
ieee: 'S. Sadeghi-Kohan and S. Hellebrand, “Dynamic Multi-Frequency Test Method
for Hidden Interconnect Defects,” 2020, doi: 10.1109/vts48691.2020.9107591.'
mla: Sadeghi-Kohan, Somayeh, and Sybille Hellebrand. “Dynamic Multi-Frequency Test
Method for Hidden Interconnect Defects.” 38th IEEE VLSI Test Symposium (VTS),
IEEE, 2020, doi:10.1109/vts48691.2020.9107591.
short: 'S. Sadeghi-Kohan, S. Hellebrand, in: 38th IEEE VLSI Test Symposium (VTS),
IEEE, Virtual Conference - Originally San Diego, CA, USA, 2020.'
date_created: 2022-01-10T08:38:34Z
date_updated: 2022-05-11T17:06:38Z
department:
- _id: '48'
doi: 10.1109/vts48691.2020.9107591
language:
- iso: eng
place: Virtual Conference - Originally San Diego, CA, USA
publication: 38th IEEE VLSI Test Symposium (VTS)
publication_status: published
publisher: IEEE
status: public
title: Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects
type: conference
user_id: '209'
year: '2020'
...
---
_id: '29460'
abstract:
- lang: eng
text: STT-RAM cells can be considered as an alternative or a hybrid addition to
today's SRAM-based cache memories. This is mostly because of their scalability
and low leakage power. Moreover, their data storing mechanism (storing the value
as resistance) makes them very suitable and applicable for multivalue cache architectures.
This feature results in system performance enhancement without any area overhead.
On the other hand, the required two-step read/write procedure in multilevel cells
results in a non-uniform time access and energy and power overhead on the system.
In this paper, we propose a new architecture to dynamically swap data between
soft (fast read access) and hard (slow read access) bits in ML cell. Moreover,
by reconfiguring cache block size, the proposed architecture can switch between
ML and SL modes at runtime. In other words, the swapping method places the hot
part of each cache block into soft-bits and the less accessed part into the hard-bits.
The SL/ML switching method benefits from the low latency and energy of SL mode
and the high storing capacity of ML mode at the same time. Although experimental
results show that our proposed method slightly increases the miss rate compared
with the conventional ML caches, the performance and energy are improved by 4.9%
and 6.5%, respectively. Also, the storage overhead of our method is about 1% that
is negligible.
author:
- first_name: Ramin
full_name: Rezaeizadeh Rookerd, Ramin
last_name: Rezaeizadeh Rookerd
- first_name: Somayeh
full_name: Sadeghi-Kohan, Somayeh
id: '78614'
last_name: Sadeghi-Kohan
- first_name: Zainalabedin
full_name: Navabi, Zainalabedin
last_name: Navabi
citation:
ama: 'Rezaeizadeh Rookerd R, Sadeghi-Kohan S, Navabi Z. Performance and Energy Enhancement
through an Online Single/Multi Level Mode Switching Cache Architecture. In: Proceedings
of the 2018 on Great Lakes Symposium on VLSI. ACM; 2018. doi:10.1145/3194554.3194599'
apa: Rezaeizadeh Rookerd, R., Sadeghi-Kohan, S., & Navabi, Z. (2018). Performance
and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache
Architecture. Proceedings of the 2018 on Great Lakes Symposium on VLSI.
https://doi.org/10.1145/3194554.3194599
bibtex: '@inproceedings{Rezaeizadeh Rookerd_Sadeghi-Kohan_Navabi_2018, title={Performance
and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache
Architecture}, DOI={10.1145/3194554.3194599},
booktitle={Proceedings of the 2018 on Great Lakes Symposium on VLSI}, publisher={ACM},
author={Rezaeizadeh Rookerd, Ramin and Sadeghi-Kohan, Somayeh and Navabi, Zainalabedin},
year={2018} }'
chicago: Rezaeizadeh Rookerd, Ramin, Somayeh Sadeghi-Kohan, and Zainalabedin Navabi.
“Performance and Energy Enhancement through an Online Single/Multi Level Mode
Switching Cache Architecture.” In Proceedings of the 2018 on Great Lakes Symposium
on VLSI. ACM, 2018. https://doi.org/10.1145/3194554.3194599.
ieee: 'R. Rezaeizadeh Rookerd, S. Sadeghi-Kohan, and Z. Navabi, “Performance and
Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture,”
2018, doi: 10.1145/3194554.3194599.'
mla: Rezaeizadeh Rookerd, Ramin, et al. “Performance and Energy Enhancement through
an Online Single/Multi Level Mode Switching Cache Architecture.” Proceedings
of the 2018 on Great Lakes Symposium on VLSI, ACM, 2018, doi:10.1145/3194554.3194599.
short: 'R. Rezaeizadeh Rookerd, S. Sadeghi-Kohan, Z. Navabi, in: Proceedings of
the 2018 on Great Lakes Symposium on VLSI, ACM, 2018.'
date_created: 2022-01-19T13:42:27Z
date_updated: 2022-01-19T13:44:17Z
department:
- _id: '48'
doi: 10.1145/3194554.3194599
language:
- iso: eng
publication: Proceedings of the 2018 on Great Lakes Symposium on VLSI
publication_status: published
publisher: ACM
status: public
title: Performance and Energy Enhancement through an Online Single/Multi Level Mode
Switching Cache Architecture
type: conference
user_id: '78614'
year: '2018'
...
---
_id: '29459'
abstract:
- lang: eng
text: Transistor and interconnect wearout is accelerated with transistor scaling
resulting in timing variations and consequently reliability challenges in digital
circuits. With the emergence of new issues like Electro-migration these problems
are getting more crucial. Age monitoring methods can be used to predict and deal
with the aging problem. Selecting appropriate locations for placement of aging
monitors is an important issue. In this work we propose a procedure for selection
of appropriate internal nodes that expose smaller overheads to the circuit, using
correlation between nodes and the shareability amongst them. To select internal
nodes, we first prune some nodes based on some attributes and thus provide a near-optimal
solution that can effectively get a number of internal nodes and consider the
effects of electro-migration as well. We have applied our proposed scheme to several
processors and ITC benchmarks and have looked at its effectiveness for these circuits.
author:
- first_name: Somayeh
full_name: Sadeghi-Kohan, Somayeh
id: '78614'
last_name: Sadeghi-Kohan
orcid: https://orcid.org/0000-0001-7246-0610
- first_name: Arash
full_name: Vafaei, Arash
last_name: Vafaei
- first_name: Zainalabedin
full_name: Navabi, Zainalabedin
last_name: Navabi
citation:
ama: 'Sadeghi-Kohan S, Vafaei A, Navabi Z. Near-Optimal Node Selection Procedure
for Aging Monitor Placement. In: 2018 IEEE 24th International Symposium on
On-Line Testing And Robust System Design (IOLTS). IEEE; 2018. doi:10.1109/iolts.2018.8474120'
apa: Sadeghi-Kohan, S., Vafaei, A., & Navabi, Z. (2018). Near-Optimal Node Selection
Procedure for Aging Monitor Placement. 2018 IEEE 24th International Symposium
on On-Line Testing And Robust System Design (IOLTS). https://doi.org/10.1109/iolts.2018.8474120
bibtex: '@inproceedings{Sadeghi-Kohan_Vafaei_Navabi_2018, title={Near-Optimal Node
Selection Procedure for Aging Monitor Placement}, DOI={10.1109/iolts.2018.8474120},
booktitle={2018 IEEE 24th International Symposium on On-Line Testing And Robust
System Design (IOLTS)}, publisher={IEEE}, author={Sadeghi-Kohan, Somayeh and Vafaei,
Arash and Navabi, Zainalabedin}, year={2018} }'
chicago: Sadeghi-Kohan, Somayeh, Arash Vafaei, and Zainalabedin Navabi. “Near-Optimal
Node Selection Procedure for Aging Monitor Placement.” In 2018 IEEE 24th International
Symposium on On-Line Testing And Robust System Design (IOLTS). IEEE, 2018.
https://doi.org/10.1109/iolts.2018.8474120.
ieee: 'S. Sadeghi-Kohan, A. Vafaei, and Z. Navabi, “Near-Optimal Node Selection
Procedure for Aging Monitor Placement,” 2018, doi: 10.1109/iolts.2018.8474120.'
mla: Sadeghi-Kohan, Somayeh, et al. “Near-Optimal Node Selection Procedure for Aging
Monitor Placement.” 2018 IEEE 24th International Symposium on On-Line Testing
And Robust System Design (IOLTS), IEEE, 2018, doi:10.1109/iolts.2018.8474120.
short: 'S. Sadeghi-Kohan, A. Vafaei, Z. Navabi, in: 2018 IEEE 24th International
Symposium on On-Line Testing And Robust System Design (IOLTS), IEEE, 2018.'
date_created: 2022-01-19T13:35:37Z
date_updated: 2023-08-02T11:36:15Z
department:
- _id: '48'
doi: 10.1109/iolts.2018.8474120
extern: '1'
language:
- iso: eng
publication: 2018 IEEE 24th International Symposium on On-Line Testing And Robust
System Design (IOLTS)
publication_status: published
publisher: IEEE
status: public
title: Near-Optimal Node Selection Procedure for Aging Monitor Placement
type: conference
user_id: '78614'
year: '2018'
...
---
_id: '29462'
abstract:
- lang: eng
text: Time-variant age information of different parts of a system can be used for
system-level performance improvement through high-level task scheduling, thus
extending the life-time of the system. Progressive age information should provide
the age state that the system is in, and the rate that it is being aged at. In
this paper, we propose a structure that monitors certain paths of a circuit and
detects its gradual age growth, and provides the aging rate and aging state of
the circuit. The proposed monitors are placed on a selected set of nodes that
represent a timing bottleneck of the system. These monitors sample expected data
on these nodes, and compare them with the expected values. The timing of sampling
changes as the circuit ages and its delay increases. The timing of sampling will
provide a measure of aging advancement of a circuit. To assess the efficacy of
the proposed method and compare it with other state-of-the-art aging monitors,
we use them on selected nodes of the execution unit of different processors, as
well as some circuits from ITC99 benchmarks. The results reveal that the precision
of our proposed method is between 0.12 (ns) to 0.401 (ns). Its Area and power
overhead are negligible and are about 2.13 and 0.69 percent respectively.
author:
- first_name: Somayeh
full_name: Sadeghi-Kohan, Somayeh
id: '78614'
last_name: Sadeghi-Kohan
orcid: https://orcid.org/0000-0001-7246-0610
- first_name: Mehdi
full_name: Kamal, Mehdi
last_name: Kamal
- first_name: Zainalabedin
full_name: Navabi, Zainalabedin
last_name: Navabi
citation:
ama: Sadeghi-Kohan S, Kamal M, Navabi Z. Self-Adjusting Monitor for Measuring Aging
Rate and Advancement. IEEE Transactions on Emerging Topics in Computing.
2017;8(3):627-641. doi:10.1109/tetc.2017.2771441
apa: Sadeghi-Kohan, S., Kamal, M., & Navabi, Z. (2017). Self-Adjusting Monitor
for Measuring Aging Rate and Advancement. IEEE Transactions on Emerging Topics
in Computing, 8(3), 627–641. https://doi.org/10.1109/tetc.2017.2771441
bibtex: '@article{Sadeghi-Kohan_Kamal_Navabi_2017, title={Self-Adjusting Monitor
for Measuring Aging Rate and Advancement}, volume={8}, DOI={10.1109/tetc.2017.2771441},
number={3}, journal={IEEE Transactions on Emerging Topics in Computing}, publisher={Institute
of Electrical and Electronics Engineers (IEEE)}, author={Sadeghi-Kohan, Somayeh
and Kamal, Mehdi and Navabi, Zainalabedin}, year={2017}, pages={627–641} }'
chicago: 'Sadeghi-Kohan, Somayeh, Mehdi Kamal, and Zainalabedin Navabi. “Self-Adjusting
Monitor for Measuring Aging Rate and Advancement.” IEEE Transactions on Emerging
Topics in Computing 8, no. 3 (2017): 627–41. https://doi.org/10.1109/tetc.2017.2771441.'
ieee: 'S. Sadeghi-Kohan, M. Kamal, and Z. Navabi, “Self-Adjusting Monitor for Measuring
Aging Rate and Advancement,” IEEE Transactions on Emerging Topics in Computing,
vol. 8, no. 3, pp. 627–641, 2017, doi: 10.1109/tetc.2017.2771441.'
mla: Sadeghi-Kohan, Somayeh, et al. “Self-Adjusting Monitor for Measuring Aging
Rate and Advancement.” IEEE Transactions on Emerging Topics in Computing,
vol. 8, no. 3, Institute of Electrical and Electronics Engineers (IEEE), 2017,
pp. 627–41, doi:10.1109/tetc.2017.2771441.
short: S. Sadeghi-Kohan, M. Kamal, Z. Navabi, IEEE Transactions on Emerging Topics
in Computing 8 (2017) 627–641.
date_created: 2022-01-19T13:45:51Z
date_updated: 2023-08-02T11:36:30Z
department:
- _id: '48'
doi: 10.1109/tetc.2017.2771441
extern: '1'
intvolume: ' 8'
issue: '3'
keyword:
- Age advancement
- age monitoring clock
- aging rate
- self-adjusting monitors
language:
- iso: eng
page: 627-641
publication: IEEE Transactions on Emerging Topics in Computing
publication_identifier:
issn:
- 2168-6750
- 2376-4562
publication_status: published
publisher: Institute of Electrical and Electronics Engineers (IEEE)
status: public
title: Self-Adjusting Monitor for Measuring Aging Rate and Advancement
type: journal_article
user_id: '78614'
volume: 8
year: '2017'
...
---
_id: '29463'
abstract:
- lang: eng
text: In this paper we propose to think out of the box and discuss an approach for
universal mitigation of Negative Bias Temperature Instability (NBTI) induced aging
untied from the limitations of its modelling. The cost-effective approach exploits
a simple property of a randomized design, i.e., the equalized signal probability
and switching activity at gate inputs. The techniques considered for structural
design randomization involve both the hardware architecture and embedded software
layers. Ultimately, the proposed approach aims at extending the reliable lifetime
of nanoelectronic systems.
author:
- first_name: Maksim
full_name: Jenihhin, Maksim
last_name: Jenihhin
- first_name: Alexander
full_name: Kamkin, Alexander
last_name: Kamkin
- first_name: Zainalabedin
full_name: Navabi, Zainalabedin
last_name: Navabi
- first_name: Somayeh
full_name: Sadeghi-Kohan, Somayeh
id: '78614'
last_name: Sadeghi-Kohan
orcid: https://orcid.org/0000-0001-7246-0610
citation:
ama: 'Jenihhin M, Kamkin A, Navabi Z, Sadeghi-Kohan S. Universal mitigation of NBTI-induced
aging by design randomization. In: 2016 IEEE East-West Design & Test Symposium
(EWDTS). IEEE; 2017. doi:10.1109/ewdts.2016.7807635'
apa: Jenihhin, M., Kamkin, A., Navabi, Z., & Sadeghi-Kohan, S. (2017). Universal
mitigation of NBTI-induced aging by design randomization. 2016 IEEE East-West
Design & Test Symposium (EWDTS). https://doi.org/10.1109/ewdts.2016.7807635
bibtex: '@inproceedings{Jenihhin_Kamkin_Navabi_Sadeghi-Kohan_2017, title={Universal
mitigation of NBTI-induced aging by design randomization}, DOI={10.1109/ewdts.2016.7807635},
booktitle={2016 IEEE East-West Design & Test Symposium (EWDTS)}, publisher={IEEE},
author={Jenihhin, Maksim and Kamkin, Alexander and Navabi, Zainalabedin and Sadeghi-Kohan,
Somayeh}, year={2017} }'
chicago: Jenihhin, Maksim, Alexander Kamkin, Zainalabedin Navabi, and Somayeh Sadeghi-Kohan.
“Universal Mitigation of NBTI-Induced Aging by Design Randomization.” In 2016
IEEE East-West Design & Test Symposium (EWDTS). IEEE, 2017. https://doi.org/10.1109/ewdts.2016.7807635.
ieee: 'M. Jenihhin, A. Kamkin, Z. Navabi, and S. Sadeghi-Kohan, “Universal mitigation
of NBTI-induced aging by design randomization,” 2017, doi: 10.1109/ewdts.2016.7807635.'
mla: Jenihhin, Maksim, et al. “Universal Mitigation of NBTI-Induced Aging by Design
Randomization.” 2016 IEEE East-West Design & Test Symposium (EWDTS),
IEEE, 2017, doi:10.1109/ewdts.2016.7807635.
short: 'M. Jenihhin, A. Kamkin, Z. Navabi, S. Sadeghi-Kohan, in: 2016 IEEE East-West
Design & Test Symposium (EWDTS), IEEE, 2017.'
date_created: 2022-01-19T13:50:13Z
date_updated: 2023-08-02T11:36:43Z
department:
- _id: '48'
doi: 10.1109/ewdts.2016.7807635
extern: '1'
language:
- iso: eng
publication: 2016 IEEE East-West Design & Test Symposium (EWDTS)
publication_status: published
publisher: IEEE
status: public
title: Universal mitigation of NBTI-induced aging by design randomization
type: conference
user_id: '78614'
year: '2017'
...
---
_id: '29465'
abstract:
- lang: eng
text: Transistor and interconnect wearout is accelerated with transistor scaling
resulting in timing variations and consequently reliability challenges in digital
circuits. Age monitoring methods can be used to predict and deal with the aging
problem. Selecting appropriate locations for placement of hardware aging monitors
is an important issue. In this work we propose a procedure for selection of appropriate
internal nodes in combinational clouds between pipeline stages or combinational
parts of a sequential circuit to place hardware monitors that can effectively
provide aging information of various components of a modern digital system. In
order to implement the node selection procedure, we propose an object-oriented
model. Object-oriented model of a circuit along with a probabilistic and logical
simulation engine that we have developed can effectively be used for implementation
and also fast evaluation of the proposed node selection mechanism. The proposed
object-oriented C+ + models can be integrated into a SystemC RTL model making
it possible to perform mixed-level simulation, and integrated evaluation of a
complete system. We have applied our proposed scheme to several processors including
MIPS, ARM, ALPHA and MiniRISC and have looked at its effectiveness for these processors.
author:
- first_name: Somayeh
full_name: Sadeghi-Kohan, Somayeh
id: '78614'
last_name: Sadeghi-Kohan
orcid: https://orcid.org/0000-0001-7246-0610
- first_name: Arezoo
full_name: Kamran, Arezoo
last_name: Kamran
- first_name: Farnaz
full_name: Forooghifar, Farnaz
last_name: Forooghifar
- first_name: Zainalabedin
full_name: Navabi, Zainalabedin
last_name: Navabi
citation:
ama: 'Sadeghi-Kohan S, Kamran A, Forooghifar F, Navabi Z. Aging in digital circuits
and age monitoring: Object-oriented modeling and evaluation. In: 2015 10th
International Conference on Design & Technology of Integrated Systems in Nanoscale
Era (DTIS). IEEE; 2015. doi:10.1109/dtis.2015.7127373'
apa: 'Sadeghi-Kohan, S., Kamran, A., Forooghifar, F., & Navabi, Z. (2015). Aging
in digital circuits and age monitoring: Object-oriented modeling and evaluation.
2015 10th International Conference on Design & Technology of Integrated
Systems in Nanoscale Era (DTIS). https://doi.org/10.1109/dtis.2015.7127373'
bibtex: '@inproceedings{Sadeghi-Kohan_Kamran_Forooghifar_Navabi_2015, title={Aging
in digital circuits and age monitoring: Object-oriented modeling and evaluation},
DOI={10.1109/dtis.2015.7127373},
booktitle={2015 10th International Conference on Design & Technology of Integrated
Systems in Nanoscale Era (DTIS)}, publisher={IEEE}, author={Sadeghi-Kohan, Somayeh
and Kamran, Arezoo and Forooghifar, Farnaz and Navabi, Zainalabedin}, year={2015}
}'
chicago: 'Sadeghi-Kohan, Somayeh, Arezoo Kamran, Farnaz Forooghifar, and Zainalabedin
Navabi. “Aging in Digital Circuits and Age Monitoring: Object-Oriented Modeling
and Evaluation.” In 2015 10th International Conference on Design & Technology
of Integrated Systems in Nanoscale Era (DTIS). IEEE, 2015. https://doi.org/10.1109/dtis.2015.7127373.'
ieee: 'S. Sadeghi-Kohan, A. Kamran, F. Forooghifar, and Z. Navabi, “Aging in digital
circuits and age monitoring: Object-oriented modeling and evaluation,” 2015, doi:
10.1109/dtis.2015.7127373.'
mla: 'Sadeghi-Kohan, Somayeh, et al. “Aging in Digital Circuits and Age Monitoring:
Object-Oriented Modeling and Evaluation.” 2015 10th International Conference
on Design & Technology of Integrated Systems in Nanoscale Era (DTIS),
IEEE, 2015, doi:10.1109/dtis.2015.7127373.'
short: 'S. Sadeghi-Kohan, A. Kamran, F. Forooghifar, Z. Navabi, in: 2015 10th International
Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS),
IEEE, 2015.'
date_created: 2022-01-19T13:51:35Z
date_updated: 2023-08-02T11:35:56Z
department:
- _id: '48'
doi: 10.1109/dtis.2015.7127373
extern: '1'
language:
- iso: eng
publication: 2015 10th International Conference on Design & Technology of Integrated
Systems in Nanoscale Era (DTIS)
publication_status: published
publisher: IEEE
status: public
title: 'Aging in digital circuits and age monitoring: Object-oriented modeling and
evaluation'
type: conference
user_id: '78614'
year: '2015'
...
---
_id: '29466'
abstract:
- lang: eng
text: Transistor and interconnect wearout is accelerated with transistor scaling
that results in timing variations. Progressive age measurement of a circuit can
help a better prevention mechanism for reducing more aging. This requires age
monitors that collect progressive age information of the circuit. This paper focuses
on monitor structures for implementation of progressive age detection. The monitors
are self-adjusting that they adjust themselves to detect progressive changes in
the timing of a circuit. Furthermore, the monitors are designed for low hardware
overhead, and certainty in reported timing changes.
author:
- first_name: Somayeh
full_name: Sadeghi-Kohan, Somayeh
id: '78614'
last_name: Sadeghi-Kohan
orcid: https://orcid.org/0000-0001-7246-0610
- first_name: Mehdi
full_name: Kamal, Mehdi
last_name: Kamal
- first_name: John
full_name: McNeil, John
last_name: McNeil
- first_name: Paolo
full_name: Prinetto, Paolo
last_name: Prinetto
- first_name: Zain
full_name: Navabi, Zain
last_name: Navabi
citation:
ama: 'Sadeghi-Kohan S, Kamal M, McNeil J, Prinetto P, Navabi Z. Online self adjusting
progressive age monitoring of timing variations. In: 2015 10th International
Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).
IEEE; 2015. doi:10.1109/dtis.2015.7127368'
apa: Sadeghi-Kohan, S., Kamal, M., McNeil, J., Prinetto, P., & Navabi, Z. (2015).
Online self adjusting progressive age monitoring of timing variations. 2015
10th International Conference on Design & Technology of Integrated Systems
in Nanoscale Era (DTIS). https://doi.org/10.1109/dtis.2015.7127368
bibtex: '@inproceedings{Sadeghi-Kohan_Kamal_McNeil_Prinetto_Navabi_2015, title={Online
self adjusting progressive age monitoring of timing variations}, DOI={10.1109/dtis.2015.7127368},
booktitle={2015 10th International Conference on Design & Technology of Integrated
Systems in Nanoscale Era (DTIS)}, publisher={IEEE}, author={Sadeghi-Kohan, Somayeh
and Kamal, Mehdi and McNeil, John and Prinetto, Paolo and Navabi, Zain}, year={2015}
}'
chicago: Sadeghi-Kohan, Somayeh, Mehdi Kamal, John McNeil, Paolo Prinetto, and Zain
Navabi. “Online Self Adjusting Progressive Age Monitoring of Timing Variations.”
In 2015 10th International Conference on Design & Technology of Integrated
Systems in Nanoscale Era (DTIS). IEEE, 2015. https://doi.org/10.1109/dtis.2015.7127368.
ieee: 'S. Sadeghi-Kohan, M. Kamal, J. McNeil, P. Prinetto, and Z. Navabi, “Online
self adjusting progressive age monitoring of timing variations,” 2015, doi: 10.1109/dtis.2015.7127368.'
mla: Sadeghi-Kohan, Somayeh, et al. “Online Self Adjusting Progressive Age Monitoring
of Timing Variations.” 2015 10th International Conference on Design & Technology
of Integrated Systems in Nanoscale Era (DTIS), IEEE, 2015, doi:10.1109/dtis.2015.7127368.
short: 'S. Sadeghi-Kohan, M. Kamal, J. McNeil, P. Prinetto, Z. Navabi, in: 2015
10th International Conference on Design & Technology of Integrated Systems
in Nanoscale Era (DTIS), IEEE, 2015.'
date_created: 2022-01-19T13:52:32Z
date_updated: 2023-08-02T11:36:58Z
department:
- _id: '48'
doi: 10.1109/dtis.2015.7127368
extern: '1'
language:
- iso: eng
publication: 2015 10th International Conference on Design & Technology of Integrated
Systems in Nanoscale Era (DTIS)
publication_status: published
publisher: IEEE
status: public
title: Online self adjusting progressive age monitoring of timing variations
type: conference
user_id: '78614'
year: '2015'
...
---
_id: '46266'
author:
- first_name: Bijan
full_name: Alizadeh, Bijan
last_name: Alizadeh
- first_name: Payman
full_name: Behnam, Payman
last_name: Behnam
- first_name: Somayeh
full_name: Sadeghi-Kohan, Somayeh
id: '78614'
last_name: Sadeghi-Kohan
orcid: https://orcid.org/0000-0001-7246-0610
citation:
ama: Alizadeh B, Behnam P, Sadeghi-Kohan S. A Scalable Formal Debugging Approach
with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for
RTL Datapath Designs. IEEE Transactions on Computers. Published online
2014:1-1. doi:10.1109/tc.2014.2329687
apa: Alizadeh, B., Behnam, P., & Sadeghi-Kohan, S. (2014). A Scalable Formal
Debugging Approach with Auto-Correction Capability based on Static Slicing and
Dynamic Ranking for RTL Datapath Designs. IEEE Transactions on Computers,
1–1. https://doi.org/10.1109/tc.2014.2329687
bibtex: '@article{Alizadeh_Behnam_Sadeghi-Kohan_2014, title={A Scalable Formal Debugging
Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking
for RTL Datapath Designs}, DOI={10.1109/tc.2014.2329687},
journal={IEEE Transactions on Computers}, publisher={Institute of Electrical and
Electronics Engineers (IEEE)}, author={Alizadeh, Bijan and Behnam, Payman and
Sadeghi-Kohan, Somayeh}, year={2014}, pages={1–1} }'
chicago: Alizadeh, Bijan, Payman Behnam, and Somayeh Sadeghi-Kohan. “A Scalable
Formal Debugging Approach with Auto-Correction Capability Based on Static Slicing
and Dynamic Ranking for RTL Datapath Designs.” IEEE Transactions on Computers,
2014, 1–1. https://doi.org/10.1109/tc.2014.2329687.
ieee: 'B. Alizadeh, P. Behnam, and S. Sadeghi-Kohan, “A Scalable Formal Debugging
Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking
for RTL Datapath Designs,” IEEE Transactions on Computers, pp. 1–1, 2014,
doi: 10.1109/tc.2014.2329687.'
mla: Alizadeh, Bijan, et al. “A Scalable Formal Debugging Approach with Auto-Correction
Capability Based on Static Slicing and Dynamic Ranking for RTL Datapath Designs.”
IEEE Transactions on Computers, Institute of Electrical and Electronics
Engineers (IEEE), 2014, pp. 1–1, doi:10.1109/tc.2014.2329687.
short: B. Alizadeh, P. Behnam, S. Sadeghi-Kohan, IEEE Transactions on Computers
(2014) 1–1.
date_created: 2023-08-02T11:15:22Z
date_updated: 2023-08-02T11:32:37Z
department:
- _id: '48'
doi: 10.1109/tc.2014.2329687
extern: '1'
keyword:
- Computational Theory and Mathematics
- Hardware and Architecture
- Theoretical Computer Science
- Software
language:
- iso: eng
page: 1-1
publication: IEEE Transactions on Computers
publication_identifier:
issn:
- 0018-9340
publication_status: published
publisher: Institute of Electrical and Electronics Engineers (IEEE)
status: public
title: A Scalable Formal Debugging Approach with Auto-Correction Capability based
on Static Slicing and Dynamic Ranking for RTL Datapath Designs
type: journal_article
user_id: '78614'
year: '2014'
...