---
_id: '61152'
abstract:
- lang: eng
  text: While neural network quantization effectively reduces the cost of matrix multiplications,
    aggressive quantization can expose non-matrix-multiply operations as significant
    performance and resource bottlenecks on embedded systems. Addressing such bottlenecks
    requires a comprehensive approach to tailoring the precision across operations
    in the inference computation. To this end, we introduce scaled-integer range analysis
    (SIRA), a static analysis technique employing interval arithmetic to determine
    the range, scale, and bias for tensors in quantized neural networks. We show how
    this information can be exploited to reduce the resource footprint of FPGA dataflow
    neural network accelerators via tailored bitwidth adaptation for accumulators
    and downstream operations, aggregation of scales and biases, and conversion of
    consecutive elementwise operations to thresholding operations. We integrate SIRA-driven
    optimizations into the open-source FINN framework, then evaluate their effectiveness
    across a range of quantized neural network workloads and compare implementation
    alternatives for non-matrix-multiply operations. We demonstrate an average reduction
    of 17\% for LUTs, 66\% for DSPs, and 22\% for accumulator bitwidths with SIRA
    optimizations, providing detailed benchmark analysis and analytical models to
    guide the implementation style for non-matrix layers. Finally, we open-source
    SIRA to facilitate community exploration of its benefits across various applications
    and hardware platforms.
author:
- first_name: Yaman
  full_name: Umuroglu, Yaman
  last_name: Umuroglu
- first_name: Christoph
  full_name: Berganski, Christoph
  id: '98854'
  last_name: Berganski
- first_name: Felix
  full_name: Jentzsch, Felix
  id: '55631'
  last_name: Jentzsch
  orcid: 0000-0003-4987-5708
- first_name: Michal
  full_name: Danilowicz, Michal
  last_name: Danilowicz
- first_name: Tomasz
  full_name: Kryjak, Tomasz
  last_name: Kryjak
- first_name: Charalampos
  full_name: Bezaitis, Charalampos
  last_name: Bezaitis
- first_name: Magnus
  full_name: Sjalander, Magnus
  last_name: Sjalander
- first_name: Ian
  full_name: Colbert, Ian
  last_name: Colbert
- first_name: Thomas
  full_name: Preusser, Thomas
  last_name: Preusser
- first_name: Jakoba
  full_name: Petri-Koenig, Jakoba
  last_name: Petri-Koenig
- first_name: Michaela
  full_name: Blott, Michaela
  last_name: Blott
citation:
  ama: 'Umuroglu Y, Berganski C, Jentzsch F, et al. SIRA: Scaled-Integer Range Analysis
    for Optimizing FPGA Dataflow Neural Network Accelerators. <i>ACM Transactions
    on Reconfigurable Technology and Systems</i>. doi:<a href="https://doi.org/10.1145/3807510">10.1145/3807510</a>'
  apa: 'Umuroglu, Y., Berganski, C., Jentzsch, F., Danilowicz, M., Kryjak, T., Bezaitis,
    C., Sjalander, M., Colbert, I., Preusser, T., Petri-Koenig, J., &#38; Blott, M.
    (n.d.). SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural
    Network Accelerators. <i>ACM Transactions on Reconfigurable Technology and Systems</i>.
    <a href="https://doi.org/10.1145/3807510">https://doi.org/10.1145/3807510</a>'
  bibtex: '@article{Umuroglu_Berganski_Jentzsch_Danilowicz_Kryjak_Bezaitis_Sjalander_Colbert_Preusser_Petri-Koenig_et
    al., title={SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural
    Network Accelerators}, DOI={<a href="https://doi.org/10.1145/3807510">10.1145/3807510</a>},
    journal={ACM Transactions on Reconfigurable Technology and Systems}, author={Umuroglu,
    Yaman and Berganski, Christoph and Jentzsch, Felix and Danilowicz, Michal and
    Kryjak, Tomasz and Bezaitis, Charalampos and Sjalander, Magnus and Colbert, Ian
    and Preusser, Thomas and Petri-Koenig, Jakoba and et al.} }'
  chicago: 'Umuroglu, Yaman, Christoph Berganski, Felix Jentzsch, Michal Danilowicz,
    Tomasz Kryjak, Charalampos Bezaitis, Magnus Sjalander, et al. “SIRA: Scaled-Integer
    Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators.” <i>ACM
    Transactions on Reconfigurable Technology and Systems</i>, n.d. <a href="https://doi.org/10.1145/3807510">https://doi.org/10.1145/3807510</a>.'
  ieee: 'Y. Umuroglu <i>et al.</i>, “SIRA: Scaled-Integer Range Analysis for Optimizing
    FPGA Dataflow Neural Network Accelerators,” <i>ACM Transactions on Reconfigurable
    Technology and Systems</i>, doi: <a href="https://doi.org/10.1145/3807510">10.1145/3807510</a>.'
  mla: 'Umuroglu, Yaman, et al. “SIRA: Scaled-Integer Range Analysis for Optimizing
    FPGA Dataflow Neural Network Accelerators.” <i>ACM Transactions on Reconfigurable
    Technology and Systems</i>, doi:<a href="https://doi.org/10.1145/3807510">10.1145/3807510</a>.'
  short: Y. Umuroglu, C. Berganski, F. Jentzsch, M. Danilowicz, T. Kryjak, C. Bezaitis,
    M. Sjalander, I. Colbert, T. Preusser, J. Petri-Koenig, M. Blott, ACM Transactions
    on Reconfigurable Technology and Systems (n.d.).
date_created: 2025-09-08T14:10:39Z
date_updated: 2026-04-20T12:58:15Z
department:
- _id: '78'
doi: 10.1145/3807510
language:
- iso: eng
publication: ACM Transactions on Reconfigurable Technology and Systems
publication_identifier:
  issn:
  - 1936-7406
publication_status: submitted
status: public
title: 'SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network
  Accelerators'
type: journal_article
user_id: '98854'
year: '2026'
...
---
_id: '56481'
author:
- first_name: Christoph
  full_name: Berganski, Christoph
  id: '98854'
  last_name: Berganski
- first_name: Felix
  full_name: Jentzsch, Felix
  id: '55631'
  last_name: Jentzsch
  orcid: 0000-0003-4987-5708
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Max
  full_name: Kuhmichel, Max
  last_name: Kuhmichel
- first_name: Heiner
  full_name: Giefers, Heiner
  last_name: Giefers
citation:
  ama: 'Berganski C, Jentzsch F, Platzner M, Kuhmichel M, Giefers H. FINN-T: Compiling
    Custom Dataflow Accelerators for Quantized Transformers. In: ; 2024.'
  apa: 'Berganski, C., Jentzsch, F., Platzner, M., Kuhmichel, M., &#38; Giefers, H.
    (2024). <i>FINN-T: Compiling Custom Dataflow Accelerators for Quantized Transformers</i>.
    International Conference on Field Programmable Technology, Sydney.'
  bibtex: '@inproceedings{Berganski_Jentzsch_Platzner_Kuhmichel_Giefers_2024, title={FINN-T:
    Compiling Custom Dataflow Accelerators for Quantized Transformers}, author={Berganski,
    Christoph and Jentzsch, Felix and Platzner, Marco and Kuhmichel, Max and Giefers,
    Heiner}, year={2024} }'
  chicago: 'Berganski, Christoph, Felix Jentzsch, Marco Platzner, Max Kuhmichel, and
    Heiner Giefers. “FINN-T: Compiling Custom Dataflow Accelerators for Quantized
    Transformers,” 2024.'
  ieee: 'C. Berganski, F. Jentzsch, M. Platzner, M. Kuhmichel, and H. Giefers, “FINN-T:
    Compiling Custom Dataflow Accelerators for Quantized Transformers,” presented
    at the International Conference on Field Programmable Technology, Sydney, 2024.'
  mla: 'Berganski, Christoph, et al. <i>FINN-T: Compiling Custom Dataflow Accelerators
    for Quantized Transformers</i>. 2024.'
  short: 'C. Berganski, F. Jentzsch, M. Platzner, M. Kuhmichel, H. Giefers, in: 2024.'
conference:
  end_date: 2024-12-12
  location: Sydney
  name: International Conference on Field Programmable Technology
  start_date: 2024-12-10
date_created: 2024-10-10T07:49:13Z
date_updated: 2024-10-10T07:52:06Z
department:
- _id: '78'
language:
- iso: eng
status: public
title: 'FINN-T: Compiling Custom Dataflow Accelerators for Quantized Transformers'
type: conference
user_id: '98854'
year: '2024'
...