@inproceedings{46920,
  author       = {{Koester, Dirk and Güldenpenning, Iris and Schack, Thomas}},
  booktitle    = {{Tagungsband des 48. Kongress der Deutschen Gesellschaft für Psychologie (DGPs)}},
  title        = {{{Zur Funktion motorischer Expertisen in der Bewegungswahrnehmung: Eine EEG-Studie}}},
  year         = {{2012}},
}

@inproceedings{46919,
  author       = {{Koester, Dirk and Güldenpenning, Iris and Schack, Thomas}},
  booktitle    = {{48. Kongress der Deutschen Gesellschaft für Psychologie (DGPs)}},
  editor       = {{Riemann, R.}},
  location     = {{Bielefeld}},
  pages        = {{169}},
  publisher    = {{Pabst Science Publishers}},
  title        = {{{Zur Funktion motorischer Expertise in der Bewegungswahrnehmung: Eine EEG-Studie}}},
  year         = {{2012}},
}

@inproceedings{46918,
  author       = {{Güldenpenning, Iris and Braun, Jelena and Schack, Thomas}},
  booktitle    = {{48. Kongress der Deutschen Gesellschaft für Psychologie (DGPS)}},
  editor       = {{Riemann, R.}},
  location     = {{Bielefeld}},
  pages        = {{391--392}},
  publisher    = {{Pabst Science Publishers}},
  title        = {{{Unconscious processing of feint and non-feint actions}}},
  year         = {{2012}},
}

@inproceedings{2106,
  abstract     = {{Although the benefits of FPGAs for accelerating scientific codes are widely acknowledged, the use of FPGA accelerators in scientific computing is not widespread because reaping these benefits requires knowledge of hardware design methods and tools that is typically not available with domain scientists. A promising but hardly investigated approach is to develop tool flows that keep the common languages for scientific code (C,C++, and Fortran) and allow the developer to augment the source code with OpenMPlike directives for instructing the compiler which parts of the application shall be offloaded the FPGA accelerator.
In this work we study whether the promise of effective FPGA acceleration with an OpenMP-like programming effort
can actually be held. Our target system is the Convey HC-1 reconfigurable computer for which an OpenMP-like
programming environment exists. As case study we use an application from computational nanophotonics. Our results
show that a developer without previous FPGA experience could create an FPGA-accelerated application that is competitive to an optimized OpenMP-parallelized CPU version running on a two socket quad-core server. Finally, we discuss our experiences with this tool flow and the Convey HC-1 from a productivity and economic point of view.}},
  author       = {{Meyer, Björn and Schumacher, Jörn and Plessl, Christian and Förstner, Jens}},
  booktitle    = {{Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}},
  keywords     = {{funding-upb-forschungspreis, funding-maxup, tet_topic_hpc}},
  pages        = {{189--196}},
  publisher    = {{IEEE}},
  title        = {{{Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?}}},
  doi          = {{10.1109/FPL.2012.6339370}},
  year         = {{2012}},
}

@article{2108,
  author       = {{Schumacher, Tobias and Plessl, Christian and Platzner, Marco}},
  issn         = {{0141-9331}},
  journal      = {{Microprocessors and Microsystems}},
  keywords     = {{funding-altera}},
  number       = {{2}},
  pages        = {{110--126}},
  title        = {{{IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators}}},
  doi          = {{10.1016/j.micpro.2011.04.002}},
  volume       = {{36}},
  year         = {{2012}},
}

@inproceedings{615,
  abstract     = {{Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, the accuracy of the simulations is to some extent questionable and they require a high computational effort if a detailed thermal model is used.For experimental evaluation of real-world temperature management methods, often synthetic heat sources are employed. Therefore, in this paper we investigated the question if we can create significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments in contrast to simulations. Therefore, we have developed eight different heat-generating cores that use different subsets of the FPGA resources. Our experimental results show that, according to the built-in thermal diode of our Xilinx Virtex-5 FPGA, we can increase the chip temperature by 134 degree C in less than 12 minutes by only utilizing about 21% of the slices.}},
  author       = {{Happe, Markus and Hangmann, Hendrik and Agne, Andreas and Plessl, Christian}},
  booktitle    = {{Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)}},
  pages        = {{1--8}},
  publisher    = {{IEEE}},
  title        = {{{Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators}}},
  doi          = {{10.1109/ReConFig.2012.6416745}},
  year         = {{2012}},
}

@inproceedings{591,
  abstract     = {{One major obstacle for a wide spread FPGA usage in general-purpose computing is the development tool flow that requires much higher effort than for pure software solutions. Convey Computer promises a solution to this problem for their HC-1 platform, where the FPGAs are configured to run as a vector processor and the software source code can be annotated with pragmas that guide an automated vectorization process. We investigate this approach for a stereo matching algorithm that has abundant parallelism and a number of different computational patterns. We note that for this case study the automated vectorization in its current state doesn’t hold its productivity promise. However, we also show that using the Vector Personality can yield a significant speedups compared to CPU implementations in two of three investigated phases of the algorithm. Those speedups don’t match custom FPGA implementations, but can come with much reduced development effort.}},
  author       = {{Kenter, Tobias and Plessl, Christian and Schmitz, Henning}},
  booktitle    = {{Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}},
  pages        = {{1--8}},
  publisher    = {{IEEE}},
  title        = {{{Pragma based parallelization - Trading hardware efficiency for ease of use?}}},
  doi          = {{10.1109/ReConFig.2012.6416773}},
  year         = {{2012}},
}

@inproceedings{609,
  abstract     = {{Today's design and operation principles and methods do not scale well with future reconfigurable computing systems due to an increased complexity in system architectures and applications, run-time dynamics and corresponding requirements. Hence, novel design and operation principles and methods are needed that possibly break drastically with the static ones we have built into our systems and the fixed abstraction layers we have cherished over the last decades. Thus, we propose a HW/SW platform that collects and maintains information about its state and progress which enables the system to reason about its behavior (self-awareness) and utilizes its knowledge to effectively and autonomously adapt its behavior to changing requirements (self-expression).To enable self-awareness, our compute nodes collect information using a variety of sensors, i.e. performance counters and thermal diodes, and use internal self-awareness models that process these information. For self-awareness, on-line learning is crucial such that the node learns and continuously updates its models at run-time to react to changing conditions. To enable self-expression, we break with the classic design-time abstraction layers of hardware, operating system and software. In contrast, our system is able to vertically migrate functionalities between the layers at run-time to exploit trade-offs between abstraction and optimization.This paper presents a heterogeneous multi-core architecture, that enables self-awareness and self-expression, an operating system for our proposed hardware/software platform and a novel self-expression method.}},
  author       = {{Happe, Markus and Agne, Andreas and Plessl, Christian and Platzner, Marco}},
  booktitle    = {{Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)}},
  pages        = {{8--9}},
  title        = {{{Hardware/Software Platform for Self-aware Compute Nodes}}},
  year         = {{2012}},
}

@inproceedings{567,
  abstract     = {{Heterogeneous machines are gaining momentum in the High Performance Computing field, due to the theoretical speedups and power consumption. In practice, while some applications meet the performance expectations, heterogeneous architectures still require a tremendous effort from the application developers. This work presents a code generation method to port codes into heterogeneous platforms, based on transformations of the control flow into function calls. The results show that the cost of the function-call mechanism is affordable for the tested HPC kernels. The complete toolchain, based on the LLVM compiler infrastructure, is fully automated once the sequential specification is provided.}},
  author       = {{Barrio, Pablo and Carreras, Carlos and Sierra, Roberto and Kenter, Tobias and Plessl, Christian}},
  booktitle    = {{Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)}},
  pages        = {{559--565}},
  publisher    = {{IEEE}},
  title        = {{{Turning control flow graphs into function calls: Code generation for heterogeneous architectures}}},
  doi          = {{10.1109/HPCSim.2012.6266973}},
  year         = {{2012}},
}

@inproceedings{612,
  abstract     = {{While numerous publications have presented ring oscillator designs for temperature measurements a detailed study of the ring oscillator's design space is still missing. In this work, we introduce metrics for comparing the performance and area efficiency of ring oscillators and a methodology for determining these metrics. As a result, we present a systematic study of the design space for ring oscillators for a Xilinx Virtex-5 platform FPGA.}},
  author       = {{Rüthing, Christoph and Happe, Markus and Agne, Andreas and Plessl, Christian}},
  booktitle    = {{Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)}},
  pages        = {{559--562}},
  publisher    = {{IEEE}},
  title        = {{{Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs}}},
  doi          = {{10.1109/FPL.2012.6339370}},
  year         = {{2012}},
}

@inproceedings{2180,
  author       = {{Beisel, Tobias and Wiersema, Tobias and Plessl, Christian and Brinkmann, André}},
  booktitle    = {{Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS)}},
  keywords     = {{funding-enhance}},
  title        = {{{Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux}}},
  year         = {{2012}},
}

@article{2177,
  author       = {{Grad, Mariusz and Plessl, Christian}},
  journal      = {{Int. Journal of Reconfigurable Computing (IJRC)}},
  publisher    = {{Hindawi Publishing Corp.}},
  title        = {{{On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors}}},
  doi          = {{10.1155/2012/418315}},
  year         = {{2012}},
}

@article{64754,
  author       = {{Walter, Boris}},
  issn         = {{0012-3862}},
  journal      = {{Dissertationes Mathematicae}},
  keywords     = {{58D05, 22E65, 22E67, 26E15, 26E20, 46E10, 46E40, 46E50, 46T05, 46T10, 46T20, 58D15}},
  pages        = {{126}},
  title        = {{{Weighted diffeomorphism groups of Banach spaces and weighted mapping groups}}},
  doi          = {{10.4064/dm484-0-1}},
  volume       = {{484}},
  year         = {{2012}},
}

@article{64672,
  author       = {{Glöckner, Helge}},
  issn         = {{0166-8641}},
  journal      = {{Topology and its Applications}},
  keywords     = {{46A03, 46F05, 22D15, 42A85, 46A11, 46A32}},
  number       = {{13}},
  pages        = {{2990–3001}},
  title        = {{{Upper bounds for continuous seminorms and special properties of bilinear maps}}},
  doi          = {{10.1016/j.topol.2012.05.010}},
  volume       = {{159}},
  year         = {{2012}},
}

@article{64673,
  author       = {{Glöckner, Helge and Langkamp, Bastian}},
  issn         = {{0166-8641}},
  journal      = {{Topology and its Applications}},
  keywords     = {{46H20, 46A45, 22E65}},
  number       = {{9}},
  pages        = {{2420–2422}},
  title        = {{{Topological algebras of rapidly decreasing matrices and generalizations}}},
  doi          = {{10.1016/j.topol.2011.09.048}},
  volume       = {{159}},
  year         = {{2012}},
}

@article{64674,
  author       = {{Glöckner, Helge}},
  issn         = {{0022-1236}},
  journal      = {{Journal of Functional Analysis}},
  keywords     = {{46A03, 46A13, 46E10, 46F05}},
  number       = {{5}},
  pages        = {{2013–2030}},
  title        = {{{Continuity of bilinear maps on direct sums of topological vector spaces}}},
  doi          = {{10.1016/j.jfa.2011.12.018}},
  volume       = {{262}},
  year         = {{2012}},
}

@article{64671,
  author       = {{Glöckner, Helge and Neeb, Karl-Hermann}},
  issn         = {{0039-3223}},
  journal      = {{Studia Mathematica}},
  keywords     = {{22E65, 34G10, 46H05}},
  number       = {{2}},
  pages        = {{95–109}},
  title        = {{{When unit groups of continuous inverse algebras are regular Lie groups}}},
  doi          = {{10.4064/sm211-2-1}},
  volume       = {{211}},
  year         = {{2012}},
}

@article{62788,
  abstract     = {{<jats:title>Abstract</jats:title><jats:p>We present a novel approach for the simulation of solid to solid phase‐transformations in polycrystalline materials. To facilitate the utilization of a non‐affine micro‐sphere formulation with volumetric‐deviatoric split, we introduce Helmholtz free energy functions depending on volumetric and deviatoric strain measures for the underlying scalar‐valued phase‐transformation model. As an extension of affine micro‐sphere models [5], the non‐affine micro‐sphere formulation with volumetric‐deviatoric split allows to capture different Young's moduli and Poisson's ratios on the macro‐scale [1]. As a consequence, the temperature‐dependent free energy assigned to each individual phase takes the form of an elliptic paraboloid in volumetric‐deviatoric strain space, where the energy landscape of the overall material is obtained from the contributions of the individual constituents. For the evolution of volume fractions, we use an approach based on statistical physics–taking into account actual Gibbs energy barriers and transformation probabilities [2]. The computation of individual energy barriers between the phases considered is enabled by numerical minimization of parametric intersection curves of elliptic Gibbs energy paraboloids. (© 2012 Wiley‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)</jats:p>}},
  author       = {{Ostwald, Richard and Bartel, Thorsten and Menzel, Andreas}},
  issn         = {{1617-7061}},
  journal      = {{PAMM}},
  number       = {{1}},
  pages        = {{277--278}},
  publisher    = {{Wiley}},
  title        = {{{Simulation of phase‐transformations based on numerical minimization of intersecting Gibbs energy potentials}}},
  doi          = {{10.1002/pamm.201210129}},
  volume       = {{12}},
  year         = {{2012}},
}

@article{62787,
  author       = {{Ostwald, Richard and Bartel, Thorsten and Menzel, Andreas}},
  issn         = {{0927-0256}},
  journal      = {{Computational Materials Science}},
  pages        = {{12--16}},
  publisher    = {{Elsevier BV}},
  title        = {{{Phase-transformations interacting with plasticity – A micro-sphere model applied to TRIP steel}}},
  doi          = {{10.1016/j.commatsci.2012.05.015}},
  volume       = {{64}},
  year         = {{2012}},
}

@article{62808,
  abstract     = {{Conventional alkaline solutions used for capacitive performance of electrodeposited cobalt hydroxides have a number of disadvantages as they are corrosive, environmentally unfriendly and provide a small working potential range. In this study, the capacitive properties of electrodeposited cobalt hydroxide/oxide were investigated in 1 M Na2SO4 solution with pH 5.5 by means of cyclic voltammetry, galvanostatic charging/discharging experiments and electrochemical impedance spectroscopy. The capacitance of the cobalt hydroxide/oxide was demonstrated to have high values of 141 F g−1 at scan rate 8 mV s−1 in this 1 M Na2SO4 solution. The anodic potential range is extended by 0.8–1.3 V vs. Ag/AgCl. A good cyclic stability and reversibility were observed.}},
  author       = {{Fedorov, Fedor S. and Linnemann, Julia and Tschulik, Kristina and Giebeler, Lars and Uhlemann, Margitta and Gebert, Annett}},
  issn         = {{0013-4686}},
  journal      = {{Electrochimica Acta}},
  keywords     = {{electrodeposition, cobalt hydroxide, supercapacitors}},
  pages        = {{166--170}},
  publisher    = {{Elsevier BV}},
  title        = {{{Capacitance performance of cobalt hydroxide-based capacitors with utilization of near-neutral electrolytes}}},
  doi          = {{10.1016/j.electacta.2012.11.123}},
  volume       = {{90}},
  year         = {{2012}},
}