[{"citation":{"ieee":"M. Lass, Bringing Massive Parallelism and Hardware Acceleration to Linear Scaling Density Functional Theory Through Targeted Approximations. Paderborn: Universität Paderborn, 2022.","short":"M. Lass, Bringing Massive Parallelism and Hardware Acceleration to Linear Scaling Density Functional Theory Through Targeted Approximations, Universität Paderborn, Paderborn, 2022.","mla":"Lass, Michael. Bringing Massive Parallelism and Hardware Acceleration to Linear Scaling Density Functional Theory Through Targeted Approximations. Universität Paderborn, 2022, doi:10.17619/UNIPB/1-1281.","bibtex":"@book{Lass_2022, place={Paderborn}, title={Bringing Massive Parallelism and Hardware Acceleration to Linear Scaling Density Functional Theory Through Targeted Approximations}, DOI={10.17619/UNIPB/1-1281}, publisher={Universität Paderborn}, author={Lass, Michael}, year={2022} }","ama":"Lass M. Bringing Massive Parallelism and Hardware Acceleration to Linear Scaling Density Functional Theory Through Targeted Approximations. Universität Paderborn; 2022. doi:10.17619/UNIPB/1-1281","apa":"Lass, M. (2022). Bringing Massive Parallelism and Hardware Acceleration to Linear Scaling Density Functional Theory Through Targeted Approximations. Universität Paderborn. https://doi.org/10.17619/UNIPB/1-1281","chicago":"Lass, Michael. Bringing Massive Parallelism and Hardware Acceleration to Linear Scaling Density Functional Theory Through Targeted Approximations. Paderborn: Universität Paderborn, 2022. https://doi.org/10.17619/UNIPB/1-1281."},"type":"dissertation","year":"2022","supervisor":[{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"}],"language":[{"iso":"eng"}],"_id":"32414","date_updated":"2022-07-25T18:14:23Z","doi":"10.17619/UNIPB/1-1281","author":[{"last_name":"Lass","id":"24135","first_name":"Michael","orcid":"0000-0002-5708-7632","full_name":"Lass, Michael"}],"publisher":"Universität Paderborn","department":[{"_id":"27"},{"_id":"518"}],"status":"public","date_created":"2022-07-25T18:13:51Z","place":"Paderborn","title":"Bringing Massive Parallelism and Hardware Acceleration to Linear Scaling Density Functional Theory Through Targeted Approximations","user_id":"24135"},{"project":[{"name":"SFB 901","_id":"1"},{"name":"SFB 901 - Project Area T","_id":"82"},{"name":"SFB 901 -Subproject T1","_id":"83"}],"date_created":"2020-12-21T13:59:55Z","status":"public","department":[{"_id":"78"}],"author":[{"last_name":"Thiele","full_name":"Thiele, Simon","first_name":"Simon"}],"user_id":"74287","title":"Implementing Machine Learning Functions as PYNQ FPGA Overlays","language":[{"iso":"eng"}],"supervisor":[{"orcid":"0000-0003-3789-6034","full_name":"Clausing, Lennart","first_name":"Lennart","id":"74287","last_name":"Clausing"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"}],"citation":{"short":"S. Thiele, Implementing Machine Learning Functions as PYNQ FPGA Overlays, 2020.","ieee":"S. Thiele, Implementing Machine Learning Functions as PYNQ FPGA Overlays. 2020.","chicago":"Thiele, Simon. Implementing Machine Learning Functions as PYNQ FPGA Overlays, 2020.","ama":"Thiele S. Implementing Machine Learning Functions as PYNQ FPGA Overlays.; 2020.","apa":"Thiele, S. (2020). Implementing Machine Learning Functions as PYNQ FPGA Overlays.","mla":"Thiele, Simon. Implementing Machine Learning Functions as PYNQ FPGA Overlays. 2020.","bibtex":"@book{Thiele_2020, title={Implementing Machine Learning Functions as PYNQ FPGA Overlays}, author={Thiele, Simon}, year={2020} }"},"type":"bachelorsthesis","year":"2020","_id":"20820","date_updated":"2022-01-06T06:54:40Z"},{"status":"public","date_created":"2020-12-21T14:02:42Z","project":[{"name":"SFB 901","_id":"1"},{"_id":"82","name":"SFB 901 - Project Area T"},{"name":"SFB 901 -Subproject T1","_id":"83"}],"author":[{"last_name":"Jaganath","full_name":"Jaganath, Vivek","first_name":"Vivek"}],"department":[{"_id":"78"}],"user_id":"74287","title":"Extension and Evaluation of Python-based High-Level Synthesis Tool Flows","language":[{"iso":"eng"}],"supervisor":[{"orcid":"0000-0003-3789-6034","full_name":"Clausing, Lennart","first_name":"Lennart","id":"74287","last_name":"Clausing"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"}],"type":"mastersthesis","year":"2020","citation":{"short":"V. Jaganath, Extension and Evaluation of Python-Based High-Level Synthesis Tool Flows, 2020.","ieee":"V. Jaganath, Extension and Evaluation of Python-based High-Level Synthesis Tool Flows. 2020.","ama":"Jaganath V. Extension and Evaluation of Python-Based High-Level Synthesis Tool Flows.; 2020.","apa":"Jaganath, V. (2020). Extension and Evaluation of Python-based High-Level Synthesis Tool Flows.","chicago":"Jaganath, Vivek. Extension and Evaluation of Python-Based High-Level Synthesis Tool Flows, 2020.","bibtex":"@book{Jaganath_2020, title={Extension and Evaluation of Python-based High-Level Synthesis Tool Flows}, author={Jaganath, Vivek}, year={2020} }","mla":"Jaganath, Vivek. Extension and Evaluation of Python-Based High-Level Synthesis Tool Flows. 2020."},"_id":"20821","date_updated":"2022-01-06T06:54:40Z"},{"user_id":"398","title":"Design and Implementation of a ReconOS-based TensorFlow Lite Delegate Architecture","abstract":[{"text":"Modern machine learning (ML) techniques continue to move into the embedded system space because traditional centralized compute resources do not suit certain application domains, for example in mobile or real-time environments. Google’s TensorFlow Lite (TFLite) framework supports this shift from cloud to edge computing and makes ML inference accessible on resource-constrained devices. While it offers the possibility to partially delegate computation to hardware accelerators, there is no such “delegate” available to utilize the promising characteristics of reconfigurable hardware.\r\nThis thesis incorporates modern platform FPGAs into TFLite by implementing a modular delegate framework, which allows accelerators within the programmable logic to take over the execution of neural network layers. To facilitate the necessary hardware/software codesign, the FPGA delegate is based on the operating system for reconfigurable\r\ncomputing (ReconOS), whose partial reconfiguration support enables the instantiation of model-tailored accelerator architectures. In the hardware back-end, a streaming-based prototype accelerator for the MobileNet model family showcases the working order of the platform, but falls short of the desired performance. Thus, it indicates the need for further exploration of alternative accelerator designs, which the delegate could automatically synthesize to meet a model’s demands.","lang":"eng"}],"project":[{"_id":"1","grant_number":"160364472","name":"SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen in dynamischen Märkten "},{"name":"SFB 901 - T: SFB 901 - Project Area T","_id":"82"},{"name":"SFB 901 - T1: SFB 901 -Subproject T1","_id":"83"}],"date_created":"2021-03-10T07:09:14Z","status":"public","department":[{"_id":"78"}],"author":[{"last_name":"Jentzsch","full_name":"Jentzsch, Felix P.","first_name":"Felix P."}],"_id":"21433","date_updated":"2023-07-09T17:12:52Z","supervisor":[{"last_name":"Lienen","id":"60323","first_name":"Christian","full_name":"Lienen, Christian"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"}],"language":[{"iso":"eng"}],"type":"mastersthesis","year":"2020","citation":{"ieee":"F. P. Jentzsch, Design and Implementation of a ReconOS-based TensorFlow Lite Delegate Architecture. 2020.","short":"F.P. Jentzsch, Design and Implementation of a ReconOS-Based TensorFlow Lite Delegate Architecture, 2020.","bibtex":"@book{Jentzsch_2020, title={Design and Implementation of a ReconOS-based TensorFlow Lite Delegate Architecture}, author={Jentzsch, Felix P.}, year={2020} }","mla":"Jentzsch, Felix P. Design and Implementation of a ReconOS-Based TensorFlow Lite Delegate Architecture. 2020.","ama":"Jentzsch FP. Design and Implementation of a ReconOS-Based TensorFlow Lite Delegate Architecture.; 2020.","apa":"Jentzsch, F. P. (2020). Design and Implementation of a ReconOS-based TensorFlow Lite Delegate Architecture.","chicago":"Jentzsch, Felix P. Design and Implementation of a ReconOS-Based TensorFlow Lite Delegate Architecture, 2020."}},{"_id":"14849","date_updated":"2022-01-06T06:52:08Z","year":"2019","type":"dissertation","citation":{"mla":"Vaz, Gavin Francis. Using Just-in-Time Code Generation to Transparently Accelerate Applications in Heterogeneous Systems. Universität Paderborn, 2019.","bibtex":"@book{Vaz_2019, title={Using Just-in-Time Code Generation to Transparently Accelerate Applications in Heterogeneous Systems}, publisher={Universität Paderborn}, author={Vaz, Gavin Francis}, year={2019} }","apa":"Vaz, G. F. (2019). Using Just-in-Time Code Generation to Transparently Accelerate Applications in Heterogeneous Systems. Universität Paderborn.","ama":"Vaz GF. Using Just-in-Time Code Generation to Transparently Accelerate Applications in Heterogeneous Systems. Universität Paderborn; 2019.","chicago":"Vaz, Gavin Francis. Using Just-in-Time Code Generation to Transparently Accelerate Applications in Heterogeneous Systems. Universität Paderborn, 2019.","ieee":"G. F. Vaz, Using Just-in-Time Code Generation to Transparently Accelerate Applications in Heterogeneous Systems. Universität Paderborn, 2019.","short":"G.F. Vaz, Using Just-in-Time Code Generation to Transparently Accelerate Applications in Heterogeneous Systems, Universität Paderborn, 2019."},"language":[{"iso":"eng"}],"supervisor":[{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"ddc":["040"],"title":"Using Just-in-Time Code Generation to Transparently Accelerate Applications in Heterogeneous Systems","user_id":"477","date_created":"2019-11-07T14:13:54Z","project":[{"name":"SFB 901","_id":"1"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"14","name":"SFB 901 - Subproject C2"}],"has_accepted_license":"1","status":"public","department":[{"_id":"518"}],"file_date_updated":"2019-11-07T14:13:14Z","author":[{"id":"30332","last_name":"Vaz","full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis"}],"publisher":"Universität Paderborn","file":[{"success":1,"relation":"main_file","content_type":"application/pdf","date_updated":"2019-11-07T14:13:14Z","creator":"florida","file_id":"14850","file_size":1462659,"access_level":"closed","file_name":"PhDThesis_GavinVaz_2019-07-11.pdf","date_created":"2019-11-07T14:13:14Z"}]},{"project":[{"_id":"1","name":"SFB 901: SFB 901"},{"_id":"4","name":"SFB 901 - C: SFB 901 - Project Area C"},{"_id":"14","name":"SFB 901 - C2: SFB 901 - Subproject C2"}],"date_created":"2022-11-30T14:36:04Z","status":"public","department":[{"_id":"27"}],"author":[{"first_name":"Heinrich","full_name":"Riebler, Heinrich","last_name":"Riebler","id":"8961"}],"title":"Efficient parallel branch-and-bound search on FPGAs using work stealing and instance-specific designs","user_id":"15504","type":"dissertation","citation":{"ieee":"H. Riebler, Efficient parallel branch-and-bound search on FPGAs using work stealing and instance-specific designs. 2019.","short":"H. Riebler, Efficient Parallel Branch-and-Bound Search on FPGAs Using Work Stealing and Instance-Specific Designs, 2019.","mla":"Riebler, Heinrich. Efficient Parallel Branch-and-Bound Search on FPGAs Using Work Stealing and Instance-Specific Designs. 2019, doi:10.17619/UNIPB/1-830.","bibtex":"@book{Riebler_2019, title={Efficient parallel branch-and-bound search on FPGAs using work stealing and instance-specific designs}, DOI={10.17619/UNIPB/1-830}, author={Riebler, Heinrich}, year={2019} }","ama":"Riebler H. Efficient Parallel Branch-and-Bound Search on FPGAs Using Work Stealing and Instance-Specific Designs.; 2019. doi:10.17619/UNIPB/1-830","apa":"Riebler, H. (2019). Efficient parallel branch-and-bound search on FPGAs using work stealing and instance-specific designs. https://doi.org/10.17619/UNIPB/1-830","chicago":"Riebler, Heinrich. Efficient Parallel Branch-and-Bound Search on FPGAs Using Work Stealing and Instance-Specific Designs, 2019. https://doi.org/10.17619/UNIPB/1-830."},"year":"2019","language":[{"iso":"eng"}],"supervisor":[{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"doi":"10.17619/UNIPB/1-830","date_updated":"2022-11-30T14:44:15Z","_id":"34167"},{"project":[{"name":"SFB 901","_id":"1"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"14","name":"SFB 901 - Subproject C2"}],"date_created":"2018-11-07T15:14:26Z","status":"public","department":[{"_id":"27"},{"_id":"518"}],"publisher":"Universität Paderborn","author":[{"last_name":"Filmwala","full_name":"Filmwala, Tasneem","first_name":"Tasneem"}],"title":"Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate it on FPGA Platform","user_id":"477","type":"mastersthesis","citation":{"bibtex":"@book{Filmwala_2018, title={Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate it on FPGA Platform}, publisher={Universität Paderborn}, author={Filmwala, Tasneem}, year={2018} }","mla":"Filmwala, Tasneem. Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate It on FPGA Platform. Universität Paderborn, 2018.","chicago":"Filmwala, Tasneem. Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate It on FPGA Platform. Universität Paderborn, 2018.","ama":"Filmwala T. Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate It on FPGA Platform. Universität Paderborn; 2018.","apa":"Filmwala, T. (2018). Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate it on FPGA Platform. Universität Paderborn.","ieee":"T. Filmwala, Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate it on FPGA Platform. Universität Paderborn, 2018.","short":"T. Filmwala, Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate It on FPGA Platform, Universität Paderborn, 2018."},"year":"2018","supervisor":[{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"language":[{"iso":"eng"}],"_id":"5414","date_updated":"2022-01-06T07:01:52Z"},{"project":[{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"14","name":"SFB 901 - Subproject C2"}],"date_created":"2018-11-07T16:16:56Z","status":"public","department":[{"_id":"27"},{"_id":"518"}],"publisher":"Universität Paderborn","author":[{"last_name":"Gadewar","first_name":"Onkar","full_name":"Gadewar, Onkar"}],"title":"Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL","user_id":"477","year":"2018","type":"mastersthesis","citation":{"short":"O. Gadewar, Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL, Universität Paderborn, 2018.","ieee":"O. Gadewar, Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL. Universität Paderborn, 2018.","apa":"Gadewar, O. (2018). Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL. Universität Paderborn.","ama":"Gadewar O. Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL. Universität Paderborn; 2018.","chicago":"Gadewar, Onkar. Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL. Universität Paderborn, 2018.","mla":"Gadewar, Onkar. Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL. Universität Paderborn, 2018.","bibtex":"@book{Gadewar_2018, title={Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL}, publisher={Universität Paderborn}, author={Gadewar, Onkar}, year={2018} }"},"supervisor":[{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"language":[{"iso":"eng"}],"date_updated":"2022-01-06T07:01:53Z","_id":"5421"},{"language":[{"iso":"eng"}],"date_updated":"2022-01-12T16:32:23Z","oa":"1","department":[{"_id":"27"},{"_id":"518"}],"project":[{"name":"SFB 901","_id":"1"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"14","name":"SFB 901 - Subproject C2"}],"title":"Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA","main_file_link":[{"open_access":"1"}],"supervisor":[{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"}],"year":"2018","citation":{"chicago":"Ramaswami, Arjun. Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA. Universität Paderborn, 2018.","apa":"Ramaswami, A. (2018). Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA. Universität Paderborn.","ama":"Ramaswami A. Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA. Universität Paderborn; 2018.","mla":"Ramaswami, Arjun. Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA. Universität Paderborn, 2018.","bibtex":"@book{Ramaswami_2018, title={Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA}, publisher={Universität Paderborn}, author={Ramaswami, Arjun}, year={2018} }","short":"A. Ramaswami, Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA, Universität Paderborn, 2018.","ieee":"A. Ramaswami, Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA. Universität Paderborn, 2018."},"type":"mastersthesis","_id":"5417","file":[{"file_name":"masterthesis.pdf","date_created":"2020-06-15T11:29:38Z","access_level":"closed","creator":"arjunr","file_id":"17093","file_size":1297585,"success":1,"relation":"main_file","content_type":"application/pdf","date_updated":"2020-06-15T11:29:38Z"}],"file_date_updated":"2020-06-15T11:29:38Z","keyword":["FFT: FPGA","CP2K","OpenCL"],"author":[{"last_name":"Ramaswami","id":"49171","first_name":"Arjun","orcid":"https://orcid.org/0000-0002-0909-1178","full_name":"Ramaswami, Arjun"}],"publisher":"Universität Paderborn","date_created":"2018-11-07T16:08:32Z","has_accepted_license":"1","status":"public","abstract":[{"lang":"eng","text":"Molecular Dynamic (MD) simulations are computationally intensive and accelerating them using specialized hardware is a topic of investigation in many studies. One of the routines in the critical path of MD simulations is the three-dimensional Fast Fourier Transformation (FFT3d). The potential in accelerating FFT3d using hardware is usually bound by bandwidth and memory. Therefore, designing a high throughput solution for an FPGA that overcomes this problem is challenging.\r\nIn this thesis, the feasibility of offloading FFT3d computations to FPGA implemented using OpenCL is investigated. In order to mask the latency in memory access, an FFT3d that overlaps computation with communication is designed. The implementa- tion of this design is synthesized for the Arria 10 GX 1150 FPGA and evaluated with the FFTW benchmark. Analysis shows a better performance using FPGA over CPU for larger FFT sizes, with the 643 FFT showing a 70% improvement in runtime using FPGAs.\r\nThis FFT3d design is integrated with CP2K to explore the potential in accelerating molecular dynamic simulations. Evaluation of CP2K simulations using FPGA shows a 41% improvement in runtime in FFT3d computations over CPU for larger FFT3d designs."}],"user_id":"49171","ddc":["000"]},{"project":[{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"14","name":"SFB 901 - Subproject C2"}],"date_created":"2018-11-07T16:10:00Z","status":"public","department":[{"_id":"27"},{"_id":"518"}],"author":[{"full_name":"Tölke, Christian","first_name":"Christian","last_name":"Tölke"}],"publisher":"Universität Paderborn","title":"Sicherheit von hybriden FPGA-Systemen in der industriellen Automatisierungstechnik -- Anforderungen und Umsetzung","user_id":"477","type":"mastersthesis","citation":{"ieee":"C. Tölke, Sicherheit von hybriden FPGA-Systemen in der industriellen Automatisierungstechnik -- Anforderungen und Umsetzung. Universität Paderborn, 2016.","short":"C. Tölke, Sicherheit von Hybriden FPGA-Systemen in Der Industriellen Automatisierungstechnik -- Anforderungen Und Umsetzung, Universität Paderborn, 2016.","mla":"Tölke, Christian. Sicherheit von Hybriden FPGA-Systemen in Der Industriellen Automatisierungstechnik -- Anforderungen Und Umsetzung. Universität Paderborn, 2016.","bibtex":"@book{Tölke_2016, title={Sicherheit von hybriden FPGA-Systemen in der industriellen Automatisierungstechnik -- Anforderungen und Umsetzung}, publisher={Universität Paderborn}, author={Tölke, Christian}, year={2016} }","ama":"Tölke C. Sicherheit von Hybriden FPGA-Systemen in Der Industriellen Automatisierungstechnik -- Anforderungen Und Umsetzung. Universität Paderborn; 2016.","apa":"Tölke, C. (2016). Sicherheit von hybriden FPGA-Systemen in der industriellen Automatisierungstechnik -- Anforderungen und Umsetzung. Universität Paderborn.","chicago":"Tölke, Christian. Sicherheit von Hybriden FPGA-Systemen in Der Industriellen Automatisierungstechnik -- Anforderungen Und Umsetzung. Universität Paderborn, 2016."},"year":"2016","language":[{"iso":"eng"}],"supervisor":[{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"_id":"5418","date_updated":"2022-01-06T07:01:52Z"}]