---
_id: '32414'
author:
- first_name: Michael
  full_name: Lass, Michael
  id: '24135'
  last_name: Lass
  orcid: 0000-0002-5708-7632
citation:
  ama: Lass M. <i>Bringing Massive Parallelism and Hardware Acceleration to Linear
    Scaling Density Functional Theory Through Targeted Approximations</i>. Universität
    Paderborn; 2022. doi:<a href="https://doi.org/10.17619/UNIPB/1-1281">10.17619/UNIPB/1-1281</a>
  apa: Lass, M. (2022). <i>Bringing Massive Parallelism and Hardware Acceleration
    to Linear Scaling Density Functional Theory Through Targeted Approximations</i>.
    Universität Paderborn. <a href="https://doi.org/10.17619/UNIPB/1-1281">https://doi.org/10.17619/UNIPB/1-1281</a>
  bibtex: '@book{Lass_2022, place={Paderborn}, title={Bringing Massive Parallelism
    and Hardware Acceleration to Linear Scaling Density Functional Theory Through
    Targeted Approximations}, DOI={<a href="https://doi.org/10.17619/UNIPB/1-1281">10.17619/UNIPB/1-1281</a>},
    publisher={Universität Paderborn}, author={Lass, Michael}, year={2022} }'
  chicago: 'Lass, Michael. <i>Bringing Massive Parallelism and Hardware Acceleration
    to Linear Scaling Density Functional Theory Through Targeted Approximations</i>.
    Paderborn: Universität Paderborn, 2022. <a href="https://doi.org/10.17619/UNIPB/1-1281">https://doi.org/10.17619/UNIPB/1-1281</a>.'
  ieee: 'M. Lass, <i>Bringing Massive Parallelism and Hardware Acceleration to Linear
    Scaling Density Functional Theory Through Targeted Approximations</i>. Paderborn:
    Universität Paderborn, 2022.'
  mla: Lass, Michael. <i>Bringing Massive Parallelism and Hardware Acceleration to
    Linear Scaling Density Functional Theory Through Targeted Approximations</i>.
    Universität Paderborn, 2022, doi:<a href="https://doi.org/10.17619/UNIPB/1-1281">10.17619/UNIPB/1-1281</a>.
  short: M. Lass, Bringing Massive Parallelism and Hardware Acceleration to Linear
    Scaling Density Functional Theory Through Targeted Approximations, Universität
    Paderborn, Paderborn, 2022.
date_created: 2022-07-25T18:13:51Z
date_updated: 2022-07-25T18:14:23Z
department:
- _id: '27'
- _id: '518'
doi: 10.17619/UNIPB/1-1281
language:
- iso: eng
place: Paderborn
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
title: Bringing Massive Parallelism and Hardware Acceleration to Linear Scaling Density
  Functional Theory Through Targeted Approximations
type: dissertation
user_id: '24135'
year: '2022'
...
---
_id: '20820'
author:
- first_name: Simon
  full_name: Thiele, Simon
  last_name: Thiele
citation:
  ama: Thiele S. <i>Implementing Machine Learning Functions as PYNQ FPGA Overlays</i>.;
    2020.
  apa: Thiele, S. (2020). <i>Implementing Machine Learning Functions as PYNQ FPGA
    Overlays</i>.
  bibtex: '@book{Thiele_2020, title={Implementing Machine Learning Functions as PYNQ
    FPGA Overlays}, author={Thiele, Simon}, year={2020} }'
  chicago: Thiele, Simon. <i>Implementing Machine Learning Functions as PYNQ FPGA
    Overlays</i>, 2020.
  ieee: S. Thiele, <i>Implementing Machine Learning Functions as PYNQ FPGA Overlays</i>.
    2020.
  mla: Thiele, Simon. <i>Implementing Machine Learning Functions as PYNQ FPGA Overlays</i>.
    2020.
  short: S. Thiele, Implementing Machine Learning Functions as PYNQ FPGA Overlays,
    2020.
date_created: 2020-12-21T13:59:55Z
date_updated: 2022-01-06T06:54:40Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '1'
  name: SFB 901
- _id: '82'
  name: SFB 901 - Project Area T
- _id: '83'
  name: SFB 901 -Subproject T1
status: public
supervisor:
- first_name: Lennart
  full_name: Clausing, Lennart
  id: '74287'
  last_name: Clausing
  orcid: 0000-0003-3789-6034
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
title: Implementing Machine Learning Functions as PYNQ FPGA Overlays
type: bachelorsthesis
user_id: '74287'
year: '2020'
...
---
_id: '20821'
author:
- first_name: Vivek
  full_name: Jaganath, Vivek
  last_name: Jaganath
citation:
  ama: Jaganath V. <i>Extension and Evaluation of Python-Based High-Level Synthesis
    Tool Flows</i>.; 2020.
  apa: Jaganath, V. (2020). <i>Extension and Evaluation of Python-based High-Level
    Synthesis Tool Flows</i>.
  bibtex: '@book{Jaganath_2020, title={Extension and Evaluation of Python-based High-Level
    Synthesis Tool Flows}, author={Jaganath, Vivek}, year={2020} }'
  chicago: Jaganath, Vivek. <i>Extension and Evaluation of Python-Based High-Level
    Synthesis Tool Flows</i>, 2020.
  ieee: V. Jaganath, <i>Extension and Evaluation of Python-based High-Level Synthesis
    Tool Flows</i>. 2020.
  mla: Jaganath, Vivek. <i>Extension and Evaluation of Python-Based High-Level Synthesis
    Tool Flows</i>. 2020.
  short: V. Jaganath, Extension and Evaluation of Python-Based High-Level Synthesis
    Tool Flows, 2020.
date_created: 2020-12-21T14:02:42Z
date_updated: 2022-01-06T06:54:40Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '1'
  name: SFB 901
- _id: '82'
  name: SFB 901 - Project Area T
- _id: '83'
  name: SFB 901 -Subproject T1
status: public
supervisor:
- first_name: Lennart
  full_name: Clausing, Lennart
  id: '74287'
  last_name: Clausing
  orcid: 0000-0003-3789-6034
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
title: Extension and Evaluation of Python-based High-Level Synthesis Tool Flows
type: mastersthesis
user_id: '74287'
year: '2020'
...
---
_id: '21433'
abstract:
- lang: eng
  text: "Modern machine learning (ML) techniques continue to move into the embedded
    system space because traditional centralized compute resources do not suit certain
    application domains, for example in mobile or real-time environments. Google’s
    TensorFlow Lite (TFLite) framework supports this shift from cloud to edge computing
    and makes ML inference accessible on resource-constrained devices. While it offers
    the possibility to partially delegate computation to hardware accelerators, there
    is no such “delegate” available to utilize the promising characteristics of reconfigurable
    hardware.\r\nThis thesis incorporates modern platform FPGAs into TFLite by implementing
    a modular delegate framework, which allows accelerators within the programmable
    logic to take over the execution of neural network layers. To facilitate the necessary
    hardware/software codesign, the FPGA delegate is based on the operating system
    for reconfigurable\r\ncomputing (ReconOS), whose partial reconfiguration support
    enables the instantiation of model-tailored accelerator architectures. In the
    hardware back-end, a streaming-based prototype accelerator for the MobileNet model
    family showcases the working order of the platform, but falls short of the desired
    performance. Thus, it indicates the need for further exploration of alternative
    accelerator designs, which the delegate could automatically synthesize to meet
    a model’s demands."
author:
- first_name: Felix P.
  full_name: Jentzsch, Felix P.
  last_name: Jentzsch
citation:
  ama: Jentzsch FP. <i>Design and Implementation of a ReconOS-Based TensorFlow Lite
    Delegate Architecture</i>.; 2020.
  apa: Jentzsch, F. P. (2020). <i>Design and Implementation of a ReconOS-based TensorFlow
    Lite Delegate Architecture</i>.
  bibtex: '@book{Jentzsch_2020, title={Design and Implementation of a ReconOS-based
    TensorFlow Lite Delegate Architecture}, author={Jentzsch, Felix P.}, year={2020}
    }'
  chicago: Jentzsch, Felix P. <i>Design and Implementation of a ReconOS-Based TensorFlow
    Lite Delegate Architecture</i>, 2020.
  ieee: F. P. Jentzsch, <i>Design and Implementation of a ReconOS-based TensorFlow
    Lite Delegate Architecture</i>. 2020.
  mla: Jentzsch, Felix P. <i>Design and Implementation of a ReconOS-Based TensorFlow
    Lite Delegate Architecture</i>. 2020.
  short: F.P. Jentzsch, Design and Implementation of a ReconOS-Based TensorFlow Lite
    Delegate Architecture, 2020.
date_created: 2021-03-10T07:09:14Z
date_updated: 2023-07-09T17:12:52Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '1'
  grant_number: '160364472'
  name: 'SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen
    in dynamischen Märkten '
- _id: '82'
  name: 'SFB 901 - T: SFB 901 - Project Area T'
- _id: '83'
  name: 'SFB 901 - T1: SFB 901 -Subproject T1'
status: public
supervisor:
- first_name: Christian
  full_name: Lienen, Christian
  id: '60323'
  last_name: Lienen
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
title: Design and Implementation of a ReconOS-based TensorFlow Lite Delegate Architecture
type: mastersthesis
user_id: '398'
year: '2020'
...
---
_id: '14849'
author:
- first_name: Gavin Francis
  full_name: Vaz, Gavin Francis
  id: '30332'
  last_name: Vaz
citation:
  ama: Vaz GF. <i>Using Just-in-Time Code Generation to Transparently Accelerate Applications
    in Heterogeneous Systems</i>. Universität Paderborn; 2019.
  apa: Vaz, G. F. (2019). <i>Using Just-in-Time Code Generation to Transparently Accelerate
    Applications in Heterogeneous Systems</i>. Universität Paderborn.
  bibtex: '@book{Vaz_2019, title={Using Just-in-Time Code Generation to Transparently
    Accelerate Applications in Heterogeneous Systems}, publisher={Universität Paderborn},
    author={Vaz, Gavin Francis}, year={2019} }'
  chicago: Vaz, Gavin Francis. <i>Using Just-in-Time Code Generation to Transparently
    Accelerate Applications in Heterogeneous Systems</i>. Universität Paderborn, 2019.
  ieee: G. F. Vaz, <i>Using Just-in-Time Code Generation to Transparently Accelerate
    Applications in Heterogeneous Systems</i>. Universität Paderborn, 2019.
  mla: Vaz, Gavin Francis. <i>Using Just-in-Time Code Generation to Transparently
    Accelerate Applications in Heterogeneous Systems</i>. Universität Paderborn, 2019.
  short: G.F. Vaz, Using Just-in-Time Code Generation to Transparently Accelerate
    Applications in Heterogeneous Systems, Universität Paderborn, 2019.
date_created: 2019-11-07T14:13:54Z
date_updated: 2022-01-06T06:52:08Z
ddc:
- '040'
department:
- _id: '518'
file:
- access_level: closed
  content_type: application/pdf
  creator: florida
  date_created: 2019-11-07T14:13:14Z
  date_updated: 2019-11-07T14:13:14Z
  file_id: '14850'
  file_name: PhDThesis_GavinVaz_2019-07-11.pdf
  file_size: 1462659
  relation: main_file
  success: 1
file_date_updated: 2019-11-07T14:13:14Z
has_accepted_license: '1'
language:
- iso: eng
project:
- _id: '1'
  name: SFB 901
- _id: '4'
  name: SFB 901 - Project Area C
- _id: '14'
  name: SFB 901 - Subproject C2
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
title: Using Just-in-Time Code Generation to Transparently Accelerate Applications
  in Heterogeneous Systems
type: dissertation
user_id: '477'
year: '2019'
...
---
_id: '34167'
author:
- first_name: Heinrich
  full_name: Riebler, Heinrich
  id: '8961'
  last_name: Riebler
citation:
  ama: Riebler H. <i>Efficient Parallel Branch-and-Bound Search on FPGAs Using Work
    Stealing and Instance-Specific Designs</i>.; 2019. doi:<a href="https://doi.org/10.17619/UNIPB/1-830">10.17619/UNIPB/1-830</a>
  apa: Riebler, H. (2019). <i>Efficient parallel branch-and-bound search on FPGAs
    using work stealing and instance-specific designs</i>. <a href="https://doi.org/10.17619/UNIPB/1-830">https://doi.org/10.17619/UNIPB/1-830</a>
  bibtex: '@book{Riebler_2019, title={Efficient parallel branch-and-bound search on
    FPGAs using work stealing and instance-specific designs}, DOI={<a href="https://doi.org/10.17619/UNIPB/1-830">10.17619/UNIPB/1-830</a>},
    author={Riebler, Heinrich}, year={2019} }'
  chicago: Riebler, Heinrich. <i>Efficient Parallel Branch-and-Bound Search on FPGAs
    Using Work Stealing and Instance-Specific Designs</i>, 2019. <a href="https://doi.org/10.17619/UNIPB/1-830">https://doi.org/10.17619/UNIPB/1-830</a>.
  ieee: H. Riebler, <i>Efficient parallel branch-and-bound search on FPGAs using work
    stealing and instance-specific designs</i>. 2019.
  mla: Riebler, Heinrich. <i>Efficient Parallel Branch-and-Bound Search on FPGAs Using
    Work Stealing and Instance-Specific Designs</i>. 2019, doi:<a href="https://doi.org/10.17619/UNIPB/1-830">10.17619/UNIPB/1-830</a>.
  short: H. Riebler, Efficient Parallel Branch-and-Bound Search on FPGAs Using Work
    Stealing and Instance-Specific Designs, 2019.
date_created: 2022-11-30T14:36:04Z
date_updated: 2022-11-30T14:44:15Z
department:
- _id: '27'
doi: 10.17619/UNIPB/1-830
language:
- iso: eng
project:
- _id: '1'
  name: 'SFB 901: SFB 901'
- _id: '4'
  name: 'SFB 901 - C: SFB 901 - Project Area C'
- _id: '14'
  name: 'SFB 901 - C2: SFB 901 - Subproject C2'
status: public
supervisor:
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
title: Efficient parallel branch-and-bound search on FPGAs using work stealing and
  instance-specific designs
type: dissertation
user_id: '15504'
year: '2019'
...
---
_id: '5414'
author:
- first_name: Tasneem
  full_name: Filmwala, Tasneem
  last_name: Filmwala
citation:
  ama: Filmwala T. <i>Study Effects of Approximation on Conjugate Gradient Algorithm
    and Accelerate It on FPGA Platform</i>. Universität Paderborn; 2018.
  apa: Filmwala, T. (2018). <i>Study Effects of Approximation on Conjugate Gradient
    Algorithm and Accelerate it on FPGA Platform</i>. Universität Paderborn.
  bibtex: '@book{Filmwala_2018, title={Study Effects of Approximation on Conjugate
    Gradient Algorithm and Accelerate it on FPGA Platform}, publisher={Universität
    Paderborn}, author={Filmwala, Tasneem}, year={2018} }'
  chicago: Filmwala, Tasneem. <i>Study Effects of Approximation on Conjugate Gradient
    Algorithm and Accelerate It on FPGA Platform</i>. Universität Paderborn, 2018.
  ieee: T. Filmwala, <i>Study Effects of Approximation on Conjugate Gradient Algorithm
    and Accelerate it on FPGA Platform</i>. Universität Paderborn, 2018.
  mla: Filmwala, Tasneem. <i>Study Effects of Approximation on Conjugate Gradient
    Algorithm and Accelerate It on FPGA Platform</i>. Universität Paderborn, 2018.
  short: T. Filmwala, Study Effects of Approximation on Conjugate Gradient Algorithm
    and Accelerate It on FPGA Platform, Universität Paderborn, 2018.
date_created: 2018-11-07T15:14:26Z
date_updated: 2022-01-06T07:01:52Z
department:
- _id: '27'
- _id: '518'
language:
- iso: eng
project:
- _id: '1'
  name: SFB 901
- _id: '4'
  name: SFB 901 - Project Area C
- _id: '14'
  name: SFB 901 - Subproject C2
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
title: Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate
  it on FPGA Platform
type: mastersthesis
user_id: '477'
year: '2018'
...
---
_id: '5421'
author:
- first_name: Onkar
  full_name: Gadewar, Onkar
  last_name: Gadewar
citation:
  ama: Gadewar O. <i>Programmable Programs? - Designing FPGA Overlay Architectures
    with OpenCL</i>. Universität Paderborn; 2018.
  apa: Gadewar, O. (2018). <i>Programmable Programs? - Designing FPGA Overlay Architectures
    with OpenCL</i>. Universität Paderborn.
  bibtex: '@book{Gadewar_2018, title={Programmable Programs? - Designing FPGA Overlay
    Architectures with OpenCL}, publisher={Universität Paderborn}, author={Gadewar,
    Onkar}, year={2018} }'
  chicago: Gadewar, Onkar. <i>Programmable Programs? - Designing FPGA Overlay Architectures
    with OpenCL</i>. Universität Paderborn, 2018.
  ieee: O. Gadewar, <i>Programmable Programs? - Designing FPGA Overlay Architectures
    with OpenCL</i>. Universität Paderborn, 2018.
  mla: Gadewar, Onkar. <i>Programmable Programs? - Designing FPGA Overlay Architectures
    with OpenCL</i>. Universität Paderborn, 2018.
  short: O. Gadewar, Programmable Programs? - Designing FPGA Overlay Architectures
    with OpenCL, Universität Paderborn, 2018.
date_created: 2018-11-07T16:16:56Z
date_updated: 2022-01-06T07:01:53Z
department:
- _id: '27'
- _id: '518'
language:
- iso: eng
project:
- _id: '1'
  name: SFB 901
- _id: '4'
  name: SFB 901 - Project Area C
- _id: '14'
  name: SFB 901 - Subproject C2
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
title: Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL
type: mastersthesis
user_id: '477'
year: '2018'
...
---
_id: '5417'
abstract:
- lang: eng
  text: "Molecular Dynamic (MD) simulations are computationally intensive and accelerating
    them using specialized hardware is a topic of investigation in many studies. One
    of the routines in the critical path of MD simulations is the three-dimensional
    Fast Fourier Transformation (FFT3d). The potential in accelerating FFT3d using
    hardware is usually bound by bandwidth and memory. Therefore, designing a high
    throughput solution for an FPGA that overcomes this problem is challenging.\r\nIn
    this thesis, the feasibility of offloading FFT3d computations to FPGA implemented
    using OpenCL is investigated. In order to mask the latency in memory access, an
    FFT3d that overlaps computation with communication is designed. The implementa-
    tion of this design is synthesized for the Arria 10 GX 1150 FPGA and evaluated
    with the FFTW benchmark. Analysis shows a better performance using FPGA over CPU
    for larger FFT sizes, with the 643 FFT showing a 70% improvement in runtime using
    FPGAs.\r\nThis FFT3d design is integrated with CP2K to explore the potential in
    accelerating molecular dynamic simulations. Evaluation of CP2K simulations using
    FPGA shows a 41% improvement in runtime in FFT3d computations over CPU for larger
    FFT3d designs."
author:
- first_name: Arjun
  full_name: Ramaswami, Arjun
  id: '49171'
  last_name: Ramaswami
  orcid: https://orcid.org/0000-0002-0909-1178
citation:
  ama: Ramaswami A. <i>Accelerating Molecular Dynamic Simulations by Offloading Fast
    Fourier Transformations to FPGA</i>. Universität Paderborn; 2018.
  apa: Ramaswami, A. (2018). <i>Accelerating Molecular Dynamic Simulations by Offloading
    Fast Fourier Transformations to FPGA</i>. Universität Paderborn.
  bibtex: '@book{Ramaswami_2018, title={Accelerating Molecular Dynamic Simulations
    by Offloading Fast Fourier Transformations to FPGA}, publisher={Universität Paderborn},
    author={Ramaswami, Arjun}, year={2018} }'
  chicago: Ramaswami, Arjun. <i>Accelerating Molecular Dynamic Simulations by Offloading
    Fast Fourier Transformations to FPGA</i>. Universität Paderborn, 2018.
  ieee: A. Ramaswami, <i>Accelerating Molecular Dynamic Simulations by Offloading
    Fast Fourier Transformations to FPGA</i>. Universität Paderborn, 2018.
  mla: Ramaswami, Arjun. <i>Accelerating Molecular Dynamic Simulations by Offloading
    Fast Fourier Transformations to FPGA</i>. Universität Paderborn, 2018.
  short: A. Ramaswami, Accelerating Molecular Dynamic Simulations by Offloading Fast
    Fourier Transformations to FPGA, Universität Paderborn, 2018.
date_created: 2018-11-07T16:08:32Z
date_updated: 2022-01-12T16:32:23Z
ddc:
- '000'
department:
- _id: '27'
- _id: '518'
file:
- access_level: closed
  content_type: application/pdf
  creator: arjunr
  date_created: 2020-06-15T11:29:38Z
  date_updated: 2020-06-15T11:29:38Z
  file_id: '17093'
  file_name: masterthesis.pdf
  file_size: 1297585
  relation: main_file
  success: 1
file_date_updated: 2020-06-15T11:29:38Z
has_accepted_license: '1'
keyword:
- 'FFT: FPGA'
- CP2K
- OpenCL
language:
- iso: eng
license: https://creativecommons.org/licenses/by-sa/4.0/
main_file_link:
- open_access: '1'
oa: '1'
project:
- _id: '1'
  name: SFB 901
- _id: '4'
  name: SFB 901 - Project Area C
- _id: '14'
  name: SFB 901 - Subproject C2
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
title: Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations
  to FPGA
type: mastersthesis
user_id: '49171'
year: '2018'
...
---
_id: '5418'
author:
- first_name: Christian
  full_name: Tölke, Christian
  last_name: Tölke
citation:
  ama: Tölke C. <i>Sicherheit von Hybriden FPGA-Systemen in Der Industriellen Automatisierungstechnik
    -- Anforderungen Und Umsetzung</i>. Universität Paderborn; 2016.
  apa: Tölke, C. (2016). <i>Sicherheit von hybriden FPGA-Systemen in der industriellen
    Automatisierungstechnik -- Anforderungen und Umsetzung</i>. Universität Paderborn.
  bibtex: '@book{Tölke_2016, title={Sicherheit von hybriden FPGA-Systemen in der industriellen
    Automatisierungstechnik -- Anforderungen und Umsetzung}, publisher={Universität
    Paderborn}, author={Tölke, Christian}, year={2016} }'
  chicago: Tölke, Christian. <i>Sicherheit von Hybriden FPGA-Systemen in Der Industriellen
    Automatisierungstechnik -- Anforderungen Und Umsetzung</i>. Universität Paderborn,
    2016.
  ieee: C. Tölke, <i>Sicherheit von hybriden FPGA-Systemen in der industriellen Automatisierungstechnik
    -- Anforderungen und Umsetzung</i>. Universität Paderborn, 2016.
  mla: Tölke, Christian. <i>Sicherheit von Hybriden FPGA-Systemen in Der Industriellen
    Automatisierungstechnik -- Anforderungen Und Umsetzung</i>. Universität Paderborn,
    2016.
  short: C. Tölke, Sicherheit von Hybriden FPGA-Systemen in Der Industriellen Automatisierungstechnik
    -- Anforderungen Und Umsetzung, Universität Paderborn, 2016.
date_created: 2018-11-07T16:10:00Z
date_updated: 2022-01-06T07:01:52Z
department:
- _id: '27'
- _id: '518'
language:
- iso: eng
project:
- _id: '1'
  name: SFB 901
- _id: '4'
  name: SFB 901 - Project Area C
- _id: '14'
  name: SFB 901 - Subproject C2
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
title: Sicherheit von hybriden FPGA-Systemen in der industriellen Automatisierungstechnik
  -- Anforderungen und Umsetzung
type: mastersthesis
user_id: '477'
year: '2016'
...
---
_id: '5420'
author:
- first_name: Gunnar
  full_name: Wüllrich, Gunnar
  last_name: Wüllrich
citation:
  ama: Wüllrich G. <i>Dynamic OpenCL Task Scheduling for Energy and Performance in
    a Heterogeneous Environment</i>. Universität Paderborn; 2016.
  apa: Wüllrich, G. (2016). <i>Dynamic OpenCL Task Scheduling for Energy and Performance
    in a Heterogeneous Environment</i>. Universität Paderborn.
  bibtex: '@book{Wüllrich_2016, title={Dynamic OpenCL Task Scheduling for Energy and
    Performance in a Heterogeneous Environment}, publisher={Universität Paderborn},
    author={Wüllrich, Gunnar}, year={2016} }'
  chicago: Wüllrich, Gunnar. <i>Dynamic OpenCL Task Scheduling for Energy and Performance
    in a Heterogeneous Environment</i>. Universität Paderborn, 2016.
  ieee: G. Wüllrich, <i>Dynamic OpenCL Task Scheduling for Energy and Performance
    in a Heterogeneous Environment</i>. Universität Paderborn, 2016.
  mla: Wüllrich, Gunnar. <i>Dynamic OpenCL Task Scheduling for Energy and Performance
    in a Heterogeneous Environment</i>. Universität Paderborn, 2016.
  short: G. Wüllrich, Dynamic OpenCL Task Scheduling for Energy and Performance in
    a Heterogeneous Environment, Universität Paderborn, 2016.
date_created: 2018-11-07T16:15:51Z
date_updated: 2022-01-06T07:01:53Z
department:
- _id: '27'
- _id: '518'
language:
- iso: eng
project:
- _id: '1'
  name: SFB 901
- _id: '4'
  name: SFB 901 - Project Area C
- _id: '14'
  name: SFB 901 - Subproject C2
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
title: Dynamic OpenCL Task Scheduling for Energy and Performance in a Heterogeneous
  Environment
type: mastersthesis
user_id: '477'
year: '2016'
...
---
_id: '161'
author:
- first_name: Tobias
  full_name: Kenter, Tobias
  id: '3145'
  last_name: Kenter
citation:
  ama: Kenter T. <i>Reconfigurable Accelerators in the World of General-Purpose Computing</i>.
    Universität Paderborn; 2016.
  apa: Kenter, T. (2016). <i>Reconfigurable Accelerators in the World of General-Purpose
    Computing</i>. Universität Paderborn.
  bibtex: '@book{Kenter_2016, title={Reconfigurable Accelerators in the World of General-Purpose
    Computing}, publisher={Universität Paderborn}, author={Kenter, Tobias}, year={2016}
    }'
  chicago: Kenter, Tobias. <i>Reconfigurable Accelerators in the World of General-Purpose
    Computing</i>. Universität Paderborn, 2016.
  ieee: T. Kenter, <i>Reconfigurable Accelerators in the World of General-Purpose
    Computing</i>. Universität Paderborn, 2016.
  mla: Kenter, Tobias. <i>Reconfigurable Accelerators in the World of General-Purpose
    Computing</i>. Universität Paderborn, 2016.
  short: T. Kenter, Reconfigurable Accelerators in the World of General-Purpose Computing,
    Universität Paderborn, 2016.
date_created: 2017-10-17T12:41:23Z
date_updated: 2022-01-06T06:52:43Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
file:
- access_level: closed
  content_type: application/pdf
  creator: florida
  date_created: 2018-03-21T12:46:48Z
  date_updated: 2018-03-21T12:46:48Z
  file_id: '1545'
  file_name: 161kenter16_diss_submission_print_16-08-26.pdf
  file_size: 5039555
  relation: main_file
  success: 1
file_date_updated: 2018-03-21T12:46:48Z
has_accepted_license: '1'
project:
- _id: '1'
  name: SFB 901
- _id: '14'
  name: SFB 901 - Subprojekt C2
- _id: '4'
  name: SFB 901 - Project Area C
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
title: Reconfigurable Accelerators in the World of General-Purpose Computing
type: dissertation
user_id: '3145'
year: '2016'
...
---
_id: '1794'
abstract:
- lang: eng
  text: Demands for computational power and energy efficiency of computing devices
    are steadily increasing. At the same time, following classic methods to increase
    speed and reduce energy consumption of these devices becomes increasingly difficult,
    bringing alternative methods into focus. One of these methods is approximate computing
    which utilizes the fact that small errors in computations are acceptable in many
    applications in order to allow acceleration of these computations or to increase
    energy efficiency. This thesis develops elements of a workflow that can be followed
    to apply approximate computing to existing applications. It proposes a novel heuristic
    approach to the localization of code paths that are suitable to approximate computing
    based on findings in recent research. Additionally, an approach to identification
    of approximable instructions within these code paths is proposed and used to implement
    simulation of approximation. The parts of the workflow are implemented with the
    goal to lay the foundation for a partly automated toolflow. Evaluation of the
    developed techniques shows that the proposed methods can help providing a convenient
    workflow, facilitating the first steps into the application of approximate computing.
author:
- first_name: Michael
  full_name: Lass, Michael
  id: '24135'
  last_name: Lass
  orcid: 0000-0002-5708-7632
citation:
  ama: 'Lass M. <i>Localization and Analysis of Code Paths Suitable for Acceleration
    Using Approximate Computing</i>. Paderborn: Paderborn University; 2015.'
  apa: 'Lass, M. (2015). <i>Localization and Analysis of Code Paths Suitable for Acceleration
    using Approximate Computing</i>. Paderborn: Paderborn University.'
  bibtex: '@book{Lass_2015, place={Paderborn}, title={Localization and Analysis of
    Code Paths Suitable for Acceleration using Approximate Computing}, publisher={Paderborn
    University}, author={Lass, Michael}, year={2015} }'
  chicago: 'Lass, Michael. <i>Localization and Analysis of Code Paths Suitable for
    Acceleration Using Approximate Computing</i>. Paderborn: Paderborn University,
    2015.'
  ieee: 'M. Lass, <i>Localization and Analysis of Code Paths Suitable for Acceleration
    using Approximate Computing</i>. Paderborn: Paderborn University, 2015.'
  mla: Lass, Michael. <i>Localization and Analysis of Code Paths Suitable for Acceleration
    Using Approximate Computing</i>. Paderborn University, 2015.
  short: M. Lass, Localization and Analysis of Code Paths Suitable for Acceleration
    Using Approximate Computing, Paderborn University, Paderborn, 2015.
date_created: 2018-03-26T15:24:10Z
date_updated: 2022-01-06T06:53:23Z
department:
- _id: '27'
- _id: '518'
place: Paderborn
publisher: Paderborn University
status: public
supervisor:
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
title: Localization and Analysis of Code Paths Suitable for Acceleration using Approximate
  Computing
type: mastersthesis
user_id: '24135'
year: '2015'
...
---
_id: '5413'
author:
- first_name: Lukas
  full_name: Funke, Lukas
  last_name: Funke
citation:
  ama: Funke L. <i>An LLVM Based Toolchain for Transparent Acceleration of Digital
    Image Processing Applications Using FPGA Overlay Architectures</i>. Universität
    Paderborn; 2015.
  apa: Funke, L. (2015). <i>An LLVM Based Toolchain for Transparent Acceleration of
    Digital Image Processing Applications using FPGA Overlay Architectures</i>. Universität
    Paderborn.
  bibtex: '@book{Funke_2015, title={An LLVM Based Toolchain for Transparent Acceleration
    of Digital Image Processing Applications using FPGA Overlay Architectures}, publisher={Universität
    Paderborn}, author={Funke, Lukas}, year={2015} }'
  chicago: Funke, Lukas. <i>An LLVM Based Toolchain for Transparent Acceleration of
    Digital Image Processing Applications Using FPGA Overlay Architectures</i>. Universität
    Paderborn, 2015.
  ieee: L. Funke, <i>An LLVM Based Toolchain for Transparent Acceleration of Digital
    Image Processing Applications using FPGA Overlay Architectures</i>. Universität
    Paderborn, 2015.
  mla: Funke, Lukas. <i>An LLVM Based Toolchain for Transparent Acceleration of Digital
    Image Processing Applications Using FPGA Overlay Architectures</i>. Universität
    Paderborn, 2015.
  short: L. Funke, An LLVM Based Toolchain for Transparent Acceleration of Digital
    Image Processing Applications Using FPGA Overlay Architectures, Universität Paderborn,
    2015.
date_created: 2018-11-07T15:10:35Z
date_updated: 2022-01-06T07:01:52Z
department:
- _id: '27'
- _id: '518'
language:
- iso: eng
project:
- _id: '1'
  name: SFB 901
- _id: '4'
  name: SFB 901 - Project Area C
- _id: '14'
  name: SFB 901 - Subproject C2
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
title: An LLVM Based Toolchain for Transparent Acceleration of Digital Image Processing
  Applications using FPGA Overlay Architectures
type: mastersthesis
user_id: '477'
year: '2015'
...
---
_id: '5416'
author:
- first_name: Thomas
  full_name: Löcke, Thomas
  last_name: Löcke
citation:
  ama: Löcke T. <i>Instance-Specific Computing in Hard- and Software for Faster Solving
    of Complex Problems</i>. Universität Paderborn; 2015.
  apa: Löcke, T. (2015). <i>Instance-Specific Computing in Hard- and Software for
    Faster Solving of Complex Problems</i>. Universität Paderborn.
  bibtex: '@book{Löcke_2015, title={Instance-Specific Computing in Hard- and Software
    for Faster Solving of Complex Problems}, publisher={Universität Paderborn}, author={Löcke,
    Thomas}, year={2015} }'
  chicago: Löcke, Thomas. <i>Instance-Specific Computing in Hard- and Software for
    Faster Solving of Complex Problems</i>. Universität Paderborn, 2015.
  ieee: T. Löcke, <i>Instance-Specific Computing in Hard- and Software for Faster
    Solving of Complex Problems</i>. Universität Paderborn, 2015.
  mla: Löcke, Thomas. <i>Instance-Specific Computing in Hard- and Software for Faster
    Solving of Complex Problems</i>. Universität Paderborn, 2015.
  short: T. Löcke, Instance-Specific Computing in Hard- and Software for Faster Solving
    of Complex Problems, Universität Paderborn, 2015.
date_created: 2018-11-07T16:06:53Z
date_updated: 2022-01-06T07:01:52Z
department:
- _id: '27'
- _id: '518'
language:
- iso: eng
project:
- _id: '1'
  name: SFB 901
- _id: '4'
  name: SFB 901 - Project Area C
- _id: '14'
  name: SFB 901 - Subproject C2
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
title: Instance-Specific Computing in Hard- and Software for Faster Solving of Complex
  Problems
type: mastersthesis
user_id: '477'
year: '2015'
...
---
_id: '5419'
author:
- first_name: Felix
  full_name: Wallaschek, Felix
  last_name: Wallaschek
citation:
  ama: Wallaschek F. <i>Accelerating Programmable Logic Controllers with the Use of
    FPGAs</i>. Universität Paderborn; 2015.
  apa: Wallaschek, F. (2015). <i>Accelerating Programmable Logic Controllers with
    the use of FPGAs</i>. Universität Paderborn.
  bibtex: '@book{Wallaschek_2015, title={Accelerating Programmable Logic Controllers
    with the use of FPGAs}, publisher={Universität Paderborn}, author={Wallaschek,
    Felix}, year={2015} }'
  chicago: Wallaschek, Felix. <i>Accelerating Programmable Logic Controllers with
    the Use of FPGAs</i>. Universität Paderborn, 2015.
  ieee: F. Wallaschek, <i>Accelerating Programmable Logic Controllers with the use
    of FPGAs</i>. Universität Paderborn, 2015.
  mla: Wallaschek, Felix. <i>Accelerating Programmable Logic Controllers with the
    Use of FPGAs</i>. Universität Paderborn, 2015.
  short: F. Wallaschek, Accelerating Programmable Logic Controllers with the Use of
    FPGAs, Universität Paderborn, 2015.
date_created: 2018-11-07T16:14:30Z
date_updated: 2022-01-06T07:01:52Z
department:
- _id: '27'
- _id: '518'
language:
- iso: eng
project:
- _id: '1'
  name: SFB 901
- _id: '4'
  name: SFB 901 - Project Area C
- _id: '14'
  name: SFB 901 - Subproject C2
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
title: Accelerating Programmable Logic Controllers with the use of FPGAs
type: mastersthesis
user_id: '477'
year: '2015'
...
---
_id: '10624'
abstract:
- lang: eng
  text: "The use of heterogeneous computing resources, such as graphics processing
    units or other specialized co-processors, has become widespread in recent years
    because of their performance and energy efficiency advantages. Operating system
    approaches that are limited to optimizing CPU usage are no longer sufficient for
    the efficient utilization of systems that comprise diverse resource types.\r\n\r\nEnabling
    task preemption on these architectures and migration of tasks between different
    resource types at run-time is not only key to improving the performance and energy
    consumption but also to enabling automatic scheduling methods for heterogeneous
    compute nodes.\r\n\r\nThis thesis proposes novel techniques for run-time management
    of heterogeneous resources and enabling tasks to migrate between diverse hardware.
    It provides fundamental work towards future operating systems by discussing implications,
    limitations, and chances of the heterogeneity and introducing solutions for energy-
    and performance-efficient run-time systems. Scheduling methods to utilize heterogeneous
    systems by the use of a centralized scheduler are presented that show benefits
    over existing approaches in varying case studies."
author:
- first_name: Tobias
  full_name: Beisel, Tobias
  last_name: Beisel
citation:
  ama: 'Beisel T. <i>Management and Scheduling of Accelerators for Heterogeneous High-Performance
    Computing</i>. Berlin: Logos Verlag Berlin GmbH; 2015.'
  apa: 'Beisel, T. (2015). <i>Management and Scheduling of Accelerators for Heterogeneous
    High-Performance Computing</i>. Berlin: Logos Verlag Berlin GmbH.'
  bibtex: '@book{Beisel_2015, place={Berlin}, title={Management and Scheduling of
    Accelerators for Heterogeneous High-Performance Computing}, publisher={Logos Verlag
    Berlin GmbH}, author={Beisel, Tobias}, year={2015} }'
  chicago: 'Beisel, Tobias. <i>Management and Scheduling of Accelerators for Heterogeneous
    High-Performance Computing</i>. Berlin: Logos Verlag Berlin GmbH, 2015.'
  ieee: 'T. Beisel, <i>Management and Scheduling of Accelerators for Heterogeneous
    High-Performance Computing</i>. Berlin: Logos Verlag Berlin GmbH, 2015.'
  mla: Beisel, Tobias. <i>Management and Scheduling of Accelerators for Heterogeneous
    High-Performance Computing</i>. Logos Verlag Berlin GmbH, 2015.
  short: T. Beisel, Management and Scheduling of Accelerators for Heterogeneous High-Performance
    Computing, Logos Verlag Berlin GmbH, Berlin, 2015.
date_created: 2019-07-10T09:36:58Z
date_updated: 2022-01-06T06:50:48Z
department:
- _id: '78'
- _id: '27'
- _id: '518'
language:
- iso: eng
page: '183'
place: Berlin
project:
- _id: '30'
  grant_number: 01|H11004
  name: Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling
    Models
publication_identifier:
  isbn:
  - 978-3-8325-4155-2
publisher: Logos Verlag Berlin GmbH
status: public
supervisor:
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
title: Management and Scheduling of Accelerators for Heterogeneous High-Performance
  Computing
type: dissertation
user_id: '3118'
year: '2015'
...