---
_id: '15920'
abstract:
- lang: eng
  text: "Secure hardware design is the most important aspect to be considered in addition
    to functional correctness. Achieving hardware security in today’s globalized Integrated
    Cir- cuit(IC) supply chain is a challenging task. One solution that is widely
    considered to help achieve secure hardware designs is Information Flow Tracking(IFT).
    It provides an ap- proach to verify that the systems adhere to security properties
    either by static verification during design phase or dynamic checking during runtime.\r\nProof-Carrying
    Hardware(PCH) is an approach to verify a functional design prior to using it in
    hardware. It is a two-party verification approach, where the target party, the
    consumer requests new functionalities with pre-defined properties to the producer.
    In response, the producer designs the IP (Intellectual Property) cores with the
    requested functionalities that adhere to the consumer-defined properties. The
    producer provides the IP cores and a proof certificate combined into a proof-carrying
    bitstream to the consumer to verify it. If the verification is successful, the
    consumer can use the IP cores in his hardware. In essence, the consumer can only
    run verified IP cores. Correctly applied, PCH techniques can help consumers to
    defend against many unintentional modifications and malicious alterations of the
    modules they receive. There are numerous published examples of how to use PCH
    to detect any change in the functionality of a circuit, i.e., pairing a PCH approach
    with functional equivalence checking for combinational or sequential circuits.
    For non-functional properties, since opening new covert channels to leak secret
    information from secure circuits is a viable attack vector for hardware trojans,
    i.e., intentionally added malicious circuitry, IFT technique is employed to make
    sure that secret/untrusted information never reaches any unclassified/trusted
    outputs.\r\nThis master thesis aims to explore the possibility of adapting Information
    Flow Tracking into a Proof-Carrying Hardware scenario. It aims to create a method
    that combines Infor- mation Flow Tracking(IFT) with a PCH approach at bitstream
    level enabling consumers to validate the trustworthiness of a module’s information
    flow without the computational costs of a complete flow analysis."
author:
- first_name: Monica
  full_name: Keerthipati, Monica
  last_name: Keerthipati
citation:
  ama: Keerthipati M. <i>A Bitstream-Level Proof-Carrying Hardware Technique for Information
    Flow Tracking</i>. Universität Paderborn; 2019.
  apa: Keerthipati, M. (2019). <i>A Bitstream-Level Proof-Carrying Hardware Technique
    for Information Flow Tracking</i>. Universität Paderborn.
  bibtex: '@book{Keerthipati_2019, title={A Bitstream-Level Proof-Carrying Hardware
    Technique for Information Flow Tracking}, publisher={Universität Paderborn}, author={Keerthipati,
    Monica}, year={2019} }'
  chicago: Keerthipati, Monica. <i>A Bitstream-Level Proof-Carrying Hardware Technique
    for Information Flow Tracking</i>. Universität Paderborn, 2019.
  ieee: M. Keerthipati, <i>A Bitstream-Level Proof-Carrying Hardware Technique for
    Information Flow Tracking</i>. Universität Paderborn, 2019.
  mla: Keerthipati, Monica. <i>A Bitstream-Level Proof-Carrying Hardware Technique
    for Information Flow Tracking</i>. Universität Paderborn, 2019.
  short: M. Keerthipati, A Bitstream-Level Proof-Carrying Hardware Technique for Information
    Flow Tracking, Universität Paderborn, 2019.
date_created: 2020-02-17T12:03:40Z
date_updated: 2022-01-06T06:52:41Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '12'
  name: SFB 901 - Subproject B4
- _id: '3'
  name: SFB 901 - Project Area B
- _id: '1'
  name: SFB 901
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Tobias
  full_name: Wiersema, Tobias
  id: '3118'
  last_name: Wiersema
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Sybille
  full_name: Hellebrand, Sybille
  id: '209'
  last_name: Hellebrand
  orcid: 0000-0002-3717-3939
title: A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking
type: mastersthesis
user_id: '477'
year: '2019'
...
---
_id: '14831'
author:
- first_name: Nithin S.
  full_name: Sabu, Nithin S.
  last_name: Sabu
citation:
  ama: Sabu NS. <i>FPGA Acceleration of String Search Techniques in Huge Data Sets</i>.
    Paderborn University; 2019.
  apa: Sabu, N. S. (2019). <i>FPGA Acceleration of String Search Techniques in Huge
    Data Sets</i>. Paderborn University.
  bibtex: '@book{Sabu_2019, title={FPGA Acceleration of String Search Techniques in
    Huge Data Sets}, publisher={Paderborn University}, author={Sabu, Nithin S.}, year={2019}
    }'
  chicago: Sabu, Nithin S. <i>FPGA Acceleration of String Search Techniques in Huge
    Data Sets</i>. Paderborn University, 2019.
  ieee: N. S. Sabu, <i>FPGA Acceleration of String Search Techniques in Huge Data
    Sets</i>. Paderborn University, 2019.
  mla: Sabu, Nithin S. <i>FPGA Acceleration of String Search Techniques in Huge Data
    Sets</i>. Paderborn University, 2019.
  short: N.S. Sabu, FPGA Acceleration of String Search Techniques in Huge Data Sets,
    Paderborn University, 2019.
date_created: 2019-11-06T12:06:09Z
date_updated: 2022-01-06T06:52:07Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Stefan
  full_name: Böttcher, Stefan
  last_name: Böttcher
- first_name: Tobias
  full_name: Wiersema, Tobias
  id: '3118'
  last_name: Wiersema
title: FPGA Acceleration of String Search Techniques in Huge Data Sets
type: mastersthesis
user_id: '3118'
year: '2019'
...
---
_id: '1097'
author:
- first_name: Felix Paul
  full_name: Jentzsch, Felix Paul
  last_name: Jentzsch
citation:
  ama: Jentzsch FP. <i>Enforcing IP Core Connection Properties with Verifiable Security
    Monitors</i>. Universität Paderborn; 2018.
  apa: Jentzsch, F. P. (2018). <i>Enforcing IP Core Connection Properties with Verifiable
    Security Monitors</i>. Universität Paderborn.
  bibtex: '@book{Jentzsch_2018, title={Enforcing IP Core Connection Properties with
    Verifiable Security Monitors}, publisher={Universität Paderborn}, author={Jentzsch,
    Felix Paul}, year={2018} }'
  chicago: Jentzsch, Felix Paul. <i>Enforcing IP Core Connection Properties with Verifiable
    Security Monitors</i>. Universität Paderborn, 2018.
  ieee: F. P. Jentzsch, <i>Enforcing IP Core Connection Properties with Verifiable
    Security Monitors</i>. Universität Paderborn, 2018.
  mla: Jentzsch, Felix Paul. <i>Enforcing IP Core Connection Properties with Verifiable
    Security Monitors</i>. Universität Paderborn, 2018.
  short: F.P. Jentzsch, Enforcing IP Core Connection Properties with Verifiable Security
    Monitors, Universität Paderborn, 2018.
date_created: 2018-01-15T16:48:05Z
date_updated: 2022-01-06T06:50:54Z
department:
- _id: '78'
keyword:
- Approximate Computing
- Proof-Carrying Hardware
- Formal Verification
language:
- iso: eng
project:
- _id: '12'
  name: SFB 901 - Subproject B4
- _id: '1'
  name: SFB 901
- _id: '3'
  name: SFB 901 - Project Area B
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Tobias
  full_name: Wiersema, Tobias
  id: '3118'
  last_name: Wiersema
title: Enforcing IP Core Connection Properties with Verifiable Security Monitors
type: bachelorsthesis
user_id: '477'
year: '2018'
...
---
_id: '1157'
author:
- first_name: Linus Matthias
  full_name: Witschen, Linus Matthias
  id: '49051'
  last_name: Witschen
citation:
  ama: Witschen LM. <i>A Framework for the Synthesis of Approximate Circuits</i>.
    Universität Paderborn; 2017.
  apa: Witschen, L. M. (2017). <i>A Framework for the Synthesis of Approximate Circuits</i>.
    Universität Paderborn.
  bibtex: '@book{Witschen_2017, title={A Framework for the Synthesis of Approximate
    Circuits}, publisher={Universität Paderborn}, author={Witschen, Linus Matthias},
    year={2017} }'
  chicago: Witschen, Linus Matthias. <i>A Framework for the Synthesis of Approximate
    Circuits</i>. Universität Paderborn, 2017.
  ieee: L. M. Witschen, <i>A Framework for the Synthesis of Approximate Circuits</i>.
    Universität Paderborn, 2017.
  mla: Witschen, Linus Matthias. <i>A Framework for the Synthesis of Approximate Circuits</i>.
    Universität Paderborn, 2017.
  short: L.M. Witschen, A Framework for the Synthesis of Approximate Circuits, Universität
    Paderborn, 2017.
date_created: 2018-02-01T14:21:19Z
date_updated: 2022-01-06T06:51:03Z
department:
- _id: '78'
- _id: '7'
language:
- iso: eng
project:
- _id: '1'
  name: SFB 901
- _id: '3'
  name: SFB 901 - Project Area B
- _id: '12'
  name: SFB 901 - Subproject B4
- _id: '52'
  name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Tobias
  full_name: Wiersema, Tobias
  id: '3118'
  last_name: Wiersema
title: A Framework for the Synthesis of Approximate Circuits
type: mastersthesis
user_id: '477'
year: '2017'
...
---
_id: '10714'
author:
- first_name: Roland
  full_name: Meißner, Roland
  last_name: Meißner
citation:
  ama: Meißner R. <i>Konzept Und Implementation Einer Benutzeroberfläche Zur Generierung
    Virtueller FPGAs</i>. Universität Paderborn; 2015.
  apa: Meißner, R. (2015). <i>Konzept und Implementation einer Benutzeroberfläche
    zur Generierung virtueller FPGAs</i>. Universität Paderborn.
  bibtex: '@book{Meißner_2015, title={Konzept und Implementation einer Benutzeroberfläche
    zur Generierung virtueller FPGAs}, publisher={Universität Paderborn}, author={Meißner,
    Roland}, year={2015} }'
  chicago: Meißner, Roland. <i>Konzept Und Implementation Einer Benutzeroberfläche
    Zur Generierung Virtueller FPGAs</i>. Universität Paderborn, 2015.
  ieee: R. Meißner, <i>Konzept und Implementation einer Benutzeroberfläche zur Generierung
    virtueller FPGAs</i>. Universität Paderborn, 2015.
  mla: Meißner, Roland. <i>Konzept Und Implementation Einer Benutzeroberfläche Zur
    Generierung Virtueller FPGAs</i>. Universität Paderborn, 2015.
  short: R. Meißner, Konzept Und Implementation Einer Benutzeroberfläche Zur Generierung
    Virtueller FPGAs, Universität Paderborn, 2015.
date_created: 2019-07-10T11:48:25Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '12'
  name: SFB 901 - Subproject B4
- _id: '1'
  name: SFB 901
- _id: '3'
  name: SFB 901 - Project Area B
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Tobias
  full_name: Wiersema, Tobias
  id: '3118'
  last_name: Wiersema
title: Konzept und Implementation einer Benutzeroberfläche zur Generierung virtueller
  FPGAs
type: bachelorsthesis
user_id: '477'
year: '2015'
...