@misc{15874, author = {{Lienen, Christian}}, publisher = {{Universität Paderborn}}, title = {{{Implementing a Real-time System on a Platform FPGA operated with ReconOS}}}, year = {{2019}}, } @misc{3365, author = {{Schnuer, Jan-Philip}}, publisher = {{Universität Paderborn}}, title = {{{Static Scheduling Algorithms for Heterogeneous Compute Nodes}}}, year = {{2018}}, } @misc{3366, author = {{Croce, Marcel}}, publisher = {{Universität Paderborn}}, title = {{{Evaluation of OpenCL-based Compilation for FPGAs}}}, year = {{2018}}, } @phdthesis{3720, abstract = {{Traditional cache design uses a consolidated block of memory address bits to index a cache set, equivalent to the use of modulo functions. While this module-based mapping scheme is widely used in contemporary cache structures due to the simplicity of its hardware design and its good performance for sequences of consecutive addresses, its use may not be satisfactory for a variety of application domains having different characteristics.This thesis presents a new type of cache mapping scheme, motivated by programmable capabilities combined with Nature-inspired optimization of reconfigurable hardware. This research has focussed on an FPGA-based evolvable cache structure of the first level cache in a multi-core processor architecture, able to dynamically change cache indexing. To solve the challenge of reconfigurable cache mappings, a programmable Boolean circuit based on a combination of Look-up Table (LUT) memory elements is proposed. Focusing on optimization aspects at the system level, a Performance Measurement Infrastructure is introduced that is able to monitor the underlying microarchitectural metrics, and an adaptive evaluation strategy is presented that leverages on Evolutionary Algorithms, that is not only capable of evolving application-specific address-to-cache-index mappings for level one split caches but also of reducing optimization times. Putting this all together and prototyping in an FPGA for a LEON3/Linux-based multi-core processor, the creation of a system architecture reduces cache misses and improves performance over the use of conventional caches.}}, author = {{Ho, Nam}}, pages = {{139}}, publisher = {{Universität Paderborn}}, title = {{{FPGA-based Reconfigurable Cache Mapping Schemes: Design and Optimization}}}, doi = {{10.17619/UNIPB/1-376}}, year = {{2018}}, } @misc{3580, author = {{Hansmeier, Tim}}, publisher = {{Universität Paderborn}}, title = {{{An FPGA Accelerator for Checking Resolution Proofs}}}, year = {{2017}}, } @misc{1157, author = {{Witschen, Linus Matthias}}, publisher = {{Universität Paderborn}}, title = {{{A Framework for the Synthesis of Approximate Circuits}}}, year = {{2017}}, } @misc{74, author = {{Knorr, Christoph}}, publisher = {{Universität Paderborn}}, title = {{{OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten}}}, year = {{2017}}, } @misc{3364, author = {{Knorr, Christoph}}, publisher = {{Universität Paderborn}}, title = {{{Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten}}}, year = {{2015}}, } @misc{10701, author = {{Koch, Benjamin}}, publisher = {{Paderborn University}}, title = {{{Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA}}}, year = {{2014}}, } @phdthesis{10733, abstract = {{Monte-Carlo Tree Search (MCTS) is a class of simulation-based search algorithms. It brought about great success in the past few years regarding the evaluation of deterministic two-player games such as the Asian board game Go. In this thesis, we present a parallelization of the most popular MCTS variant for large HPC compute clusters that efficiently shares a single game tree representation in a distributed memory environment and scales up to 128 compute nodes and 2048 cores. It is hereby one of the most powerful MCTS parallelizations to date. In order to measure the impact of our parallelization on the search quality and remain comparable to the most advanced MCTS implementations to date, we implemented it in a state-of-the-art Go engine Gomorra, making it competitive with the strongest Go programs in the world. We further present an empirical comparison of different Bayesian ranking systems when being used for predicting expert moves for the game of Go and introduce a novel technique for automated detection and analysis of evaluation uncertainties that show up during MCTS searches.}}, author = {{Schäfers, Lars}}, isbn = {{978-3-8325-3748-7}}, pages = {{133}}, publisher = {{Logos Verlag Berlin GmbH}}, title = {{{Parallel Monte-Carlo Tree Search for HPC Systems and its Application to Computer Go}}}, year = {{2014}}, }