[{"year":"2014","place":"Berlin","citation":{"short":"L. Schäfers, Parallel Monte-Carlo Tree Search for HPC Systems and Its Application to Computer Go, Logos Verlag Berlin GmbH, Berlin, 2014.","mla":"Schäfers, Lars. <i>Parallel Monte-Carlo Tree Search for HPC Systems and Its Application to Computer Go</i>. Logos Verlag Berlin GmbH, 2014.","bibtex":"@book{Schäfers_2014, place={Berlin}, title={Parallel Monte-Carlo Tree Search for HPC Systems and its Application to Computer Go}, publisher={Logos Verlag Berlin GmbH}, author={Schäfers, Lars}, year={2014} }","apa":"Schäfers, L. (2014). <i>Parallel Monte-Carlo Tree Search for HPC Systems and its Application to Computer Go</i>. Berlin: Logos Verlag Berlin GmbH.","chicago":"Schäfers, Lars. <i>Parallel Monte-Carlo Tree Search for HPC Systems and Its Application to Computer Go</i>. Berlin: Logos Verlag Berlin GmbH, 2014.","ieee":"L. Schäfers, <i>Parallel Monte-Carlo Tree Search for HPC Systems and its Application to Computer Go</i>. Berlin: Logos Verlag Berlin GmbH, 2014.","ama":"Schäfers L. <i>Parallel Monte-Carlo Tree Search for HPC Systems and Its Application to Computer Go</i>. Berlin: Logos Verlag Berlin GmbH; 2014."},"page":"133","publication_status":"published","publication_identifier":{"isbn":["978-3-8325-3748-7"]},"title":"Parallel Monte-Carlo Tree Search for HPC Systems and its Application to Computer Go","publisher":"Logos Verlag Berlin GmbH","date_updated":"2022-01-06T06:50:50Z","supervisor":[{"last_name":"Platzner","full_name":"Platzner, Marco","id":"398","first_name":"Marco"}],"date_created":"2019-07-10T11:58:06Z","author":[{"last_name":"Schäfers","full_name":"Schäfers, Lars","first_name":"Lars"}],"abstract":[{"lang":"eng","text":"Monte-Carlo Tree Search (MCTS) is a class of simulation-based search algorithms. It brought about great success in the past few years regarding the evaluation of deterministic two-player games such as the Asian board game Go.\r\n\r\nIn this thesis, we present a parallelization of the most popular MCTS variant for large HPC compute clusters that efficiently shares a single game tree representation in a distributed memory environment and scales up to 128 compute nodes and 2048 cores. It is hereby one of the most powerful MCTS parallelizations to date.\r\n\r\nIn order to measure the impact of our parallelization on the search quality and remain comparable to the most advanced MCTS implementations to date, we implemented it in a state-of-the-art Go engine Gomorra, making it competitive with the strongest Go programs in the world.\r\n\r\nWe further present an empirical comparison of different Bayesian ranking systems when being used for predicting expert moves for the game of Go and introduce a novel technique for automated detection and analysis of evaluation uncertainties that show up during MCTS searches."}],"status":"public","type":"dissertation","language":[{"iso":"eng"}],"_id":"10733","user_id":"3118","department":[{"_id":"78"}]},{"type":"mastersthesis","status":"public","department":[{"_id":"78"}],"user_id":"3118","_id":"10744","language":[{"iso":"eng"}],"citation":{"ama":"Surmund S. <i>Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA</i>. Paderborn University; 2014.","ieee":"S. Surmund, <i>Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA</i>. Paderborn University, 2014.","chicago":"Surmund, Sebastian. <i>Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA</i>. Paderborn University, 2014.","bibtex":"@book{Surmund_2014, title={Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA}, publisher={Paderborn University}, author={Surmund, Sebastian}, year={2014} }","mla":"Surmund, Sebastian. <i>Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA</i>. Paderborn University, 2014.","short":"S. Surmund, Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA, Paderborn University, 2014.","apa":"Surmund, S. (2014). <i>Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA</i>. Paderborn University."},"year":"2014","author":[{"last_name":"Surmund","full_name":"Surmund, Sebastian","first_name":"Sebastian"}],"date_created":"2019-07-10T12:00:45Z","supervisor":[{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}],"publisher":"Paderborn University","date_updated":"2022-01-06T06:50:50Z","title":"Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA"},{"abstract":[{"text":"Reconfigurable circuit devices have opened up a fundamentally new way of creating adaptable systems. Combined with artificial evolution, reconfigurable circuits allow an elegant adaptation approach to compensating for changes in the distribution of input data, computational resource errors, and variations in resource requirements. Referred to as ``Evolvable Hardware'' (EHW), this paradigm has yielded astonishing results for traditional engineering challenges and has discovered intriguing design principles, which have not yet been seen in conventional engineering.\r\n\r\nIn this thesis, we present new and fundamental work on Evolvable Hardware motivated by the insight that Evolvable Hardware needs to compensate for events with different change rates. To solve the challenge of different adaptation speeds, we propose a unified adaptation approach based on multi-objective evolution, evolving and propagating candidate solutions that are diverse in objectives that may experience radical changes.\r\n\r\nFocusing on algorithmic aspects, we enable Cartesian Genetic Programming (CGP) model, which we are using to encode Boolean circuits, for multi-objective optimization by introducing a meaningful recombination operator. We improve the scalability of CGP by objectives scaling, periodization of local- and global-search algorithms, and the automatic acquisition and reuse of subfunctions using age- and cone-based techniques. We validate our methods on the applications of adaptation of hardware classifiers to resource changes, recognition of muscular signals for prosthesis control and optimization of processor caches.","lang":"eng"}],"status":"public","type":"dissertation","language":[{"iso":"eng"}],"_id":"11619","user_id":"3118","department":[{"_id":"78"}],"place":"Berlin","year":"2013","citation":{"ieee":"P. Kaufmann, <i>Adapting Hardware Systems by Means of Multi-Objective Evolution</i>. Berlin: Logos Verlag Berlin GmbH, 2013.","chicago":"Kaufmann, Paul. <i>Adapting Hardware Systems by Means of Multi-Objective Evolution</i>. Berlin: Logos Verlag Berlin GmbH, 2013.","ama":"Kaufmann P. <i>Adapting Hardware Systems by Means of Multi-Objective Evolution</i>. Berlin: Logos Verlag Berlin GmbH; 2013.","bibtex":"@book{Kaufmann_2013, place={Berlin}, title={Adapting Hardware Systems by Means of Multi-Objective Evolution}, publisher={Logos Verlag Berlin GmbH}, author={Kaufmann, Paul}, year={2013} }","short":"P. Kaufmann, Adapting Hardware Systems by Means of Multi-Objective Evolution, Logos Verlag Berlin GmbH, Berlin, 2013.","mla":"Kaufmann, Paul. <i>Adapting Hardware Systems by Means of Multi-Objective Evolution</i>. Logos Verlag Berlin GmbH, 2013.","apa":"Kaufmann, P. (2013). <i>Adapting Hardware Systems by Means of Multi-Objective Evolution</i>. Berlin: Logos Verlag Berlin GmbH."},"page":"249","publication_status":"published","publication_identifier":{"isbn":["978-3-8325-3530-8"]},"title":"Adapting Hardware Systems by Means of Multi-Objective Evolution","publisher":"Logos Verlag Berlin GmbH","date_updated":"2022-01-06T06:51:04Z","author":[{"first_name":"Paul","full_name":"Kaufmann, Paul","last_name":"Kaufmann"}],"date_created":"2019-07-11T11:51:51Z","supervisor":[{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}]},{"related_material":{"link":[{"url":"https://www.logos-verlag.de/cgi-bin/engbuchmid?isbn=3425&lng=deu&id=","relation":"confirmation"}]},"publication_status":"published","publication_identifier":{"isbn":["978-3-8325-3425-7"]},"citation":{"ama":"Happe M. <i>Performance and Thermal Management on Self-Adaptive Hybrid Multi-Cores</i>. Berlin: Logos Verlag Berlin GmbH; 2013.","ieee":"M. Happe, <i>Performance and thermal management on self-adaptive hybrid multi-cores</i>. Berlin: Logos Verlag Berlin GmbH, 2013.","chicago":"Happe, Markus. <i>Performance and Thermal Management on Self-Adaptive Hybrid Multi-Cores</i>. Berlin: Logos Verlag Berlin GmbH, 2013.","short":"M. Happe, Performance and Thermal Management on Self-Adaptive Hybrid Multi-Cores, Logos Verlag Berlin GmbH, Berlin, 2013.","bibtex":"@book{Happe_2013, place={Berlin}, title={Performance and thermal management on self-adaptive hybrid multi-cores}, publisher={Logos Verlag Berlin GmbH}, author={Happe, Markus}, year={2013} }","mla":"Happe, Markus. <i>Performance and Thermal Management on Self-Adaptive Hybrid Multi-Cores</i>. Logos Verlag Berlin GmbH, 2013.","apa":"Happe, M. (2013). <i>Performance and thermal management on self-adaptive hybrid multi-cores</i>. Berlin: Logos Verlag Berlin GmbH."},"page":"220","year":"2013","place":"Berlin","author":[{"full_name":"Happe, Markus","last_name":"Happe","first_name":"Markus"}],"supervisor":[{"last_name":"Platzner","full_name":"Platzner, Marco","id":"398","first_name":"Marco"}],"date_created":"2017-10-17T12:42:30Z","publisher":"Logos Verlag Berlin GmbH","date_updated":"2022-01-06T07:01:34Z","title":"Performance and thermal management on self-adaptive hybrid multi-cores","type":"dissertation","status":"public","abstract":[{"text":"Handling run-time dynamics on embedded system-on-chip architectures has become more challenging over the years. On the one hand, the impact of workload and physical dynamics on the system behavior has dramatically increased. On the other hand, embedded architectures have become more complex as they have evolved from single-processor systems over multi-processor systems to hybrid multi-core platforms.Static design-time techniques no longer provide suitable solutions to deal with the run-time dynamics of today's embedded systems. Therefore, system designers have to apply run-time solutions, which have hardly been investigated for hybrid multi-core platforms.In this thesis, we present fundamental work in the new area of run-time management on hybrid multi-core platforms. We propose a novel architecture, a self-adaptive hybrid multi-core system, that combines heterogeneous processors, reconfigurable hardware cores, and monitoring cores on a single chip. Using self-adaptation on thread-level, our hybrid multi-core systems can effectively perform performance and thermal management autonomously at run-time. ","lang":"eng"}],"user_id":"477","department":[{"_id":"78"}],"project":[{"_id":"14","name":"SFB 901 - Subprojekt C2"},{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Project Area C","_id":"4"}],"_id":"501","language":[{"iso":"eng"}]},{"ddc":["040"],"language":[{"iso":"eng"}],"abstract":[{"lang":"eng","text":"FPGAs, systems on chip and embedded systems are nowadays irreplaceable. They combine the computational power of application specific hardware with software-like flexibility. At runtime, they can adjust their functionality by downloading new hardware modules and integrating their functionality. Due to their growing capabilities, the demands made to reconfigurable hardware grow. Their deployment in increasingly security critical scenarios requires new ways of enforcing security since a failure in security has severe consequences. Aside from financial losses, a loss of human life and risks to national security are possible. With this work I present the novel and groundbreaking concept of proof-carrying hardware. It is a method for the verification of properties of hardware modules to guarantee security for a target platform at runtime. The producer of a hardware module delivers based on the consumer's safety policy a safety proof in combination with the reconfiguration bitstream. The extensive computation of a proof is a contrast to the comparatively undemanding checking of the proof. I present a prototype based on open-source tools and an abstract FPGA architecture and bitstream format. The proof of the usability of proof-carrying hardware provides the evaluation of the prototype with the exemplary application of securing combinational and bounded sequential equivalence of reference monitor modules for memory safety."},{"lang":"ger","text":"FPGAs, System on Chips und eingebettete Systeme sind heutzutage kaum mehr wegzudenken. Sie kombinieren die Rechenleistung von spezialisierter Hardware mit einer Software-ähnlichen Flexibilität. Zur Laufzeit können sie ihre Funktionalität anpassen, indem sie online neue Hardware Module beziehen und deren Funktionalität integrieren. Mit der Leistung wachsen auch die Anforderungen an rekonfigurierbare Hardware. Ihr Einsatz in immer sicherheitskritischeren Szenarien erfordert neue Wege um Sicherheit zu gewährleisten, da ein Versagen der Sicherheit gravierende Folgen mit sich bringt. Neben finanziellen Verlusten sind auch der Verlust von Menschenleben oder Einbußen in der nationalen Sicherheit denkbar. In dieser Arbeit stelle ich das neue und wegweisende Konzept der beweistragenden Hardware vor. Es ist eine Methode zur Verifizierung von Eigenschaften von Hardware Modulen um die Sicherheit der Zielplatformen zur Laufzeit zu garantieren. Der Produzent eines Hardware Moduls liefert, basierend auf den Sicherheitsbestimmungen des Konsumenten, einen Beweis der Sicherheit mit dem Rekonfigurierungsbitstrom. Die aufwendige Berechnung des Beweises steht im Kontrast zu der vergleichsweise unaufwendigen Überprüfung durch den Konsumenten. Ich präsentiere einen Prototypen basierend auf Open Source Werkzeugen und einer eigenen abstrakten FPGA Architektur samt Bitstromformat. Den Nachweis über die Nutzbarkeit von beweistragender Hardware erbringt die Evaluierung des Prototypen zur beispielhaften Anwendung der Sicherung von kombinatorischer und begrenzt sequenzieller Äquivalenz von Referenzmonitor-Modulen zur Speichersicherheit."}],"file":[{"access_level":"closed","file_name":"586-Drzevitzky-PhD_01.pdf","file_id":"1261","file_size":1438436,"date_created":"2018-03-15T08:38:19Z","creator":"florida","date_updated":"2018-03-15T08:38:19Z","relation":"main_file","success":1,"content_type":"application/pdf"}],"publisher":"Universität Paderborn","date_created":"2017-10-17T12:42:46Z","title":"Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security","year":"2012","project":[{"name":"SFB 901 - Subprojekt B4","_id":"12"},{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Project Area B","_id":"3"}],"_id":"586","user_id":"477","department":[{"_id":"78"}],"file_date_updated":"2018-03-15T08:38:19Z","type":"dissertation","status":"public","date_updated":"2022-01-06T07:02:44Z","oa":"1","supervisor":[{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}],"author":[{"first_name":"Stephanie","full_name":"Drzevitzky, Stephanie","last_name":"Drzevitzky"}],"main_file_link":[{"url":"https://nbn-resolving.de/urn:nbn:de:hbz:466:2-10423","open_access":"1"}],"publication_status":"published","has_accepted_license":"1","citation":{"apa":"Drzevitzky, S. (2012). <i>Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security</i>. Universität Paderborn.","bibtex":"@book{Drzevitzky_2012, title={Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security}, publisher={Universität Paderborn}, author={Drzevitzky, Stephanie}, year={2012} }","mla":"Drzevitzky, Stephanie. <i>Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security</i>. Universität Paderborn, 2012.","short":"S. Drzevitzky, Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security, Universität Paderborn, 2012.","chicago":"Drzevitzky, Stephanie. <i>Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security</i>. Universität Paderborn, 2012.","ieee":"S. Drzevitzky, <i>Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security</i>. Universität Paderborn, 2012.","ama":"Drzevitzky S. <i>Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security</i>. Universität Paderborn; 2012."},"page":"114"},{"supervisor":[{"last_name":"Platzner","id":"398","full_name":"Platzner, Marco","first_name":"Marco"}],"date_created":"2019-07-10T11:13:12Z","author":[{"first_name":"Heiner","full_name":"Giefers, Heiner","last_name":"Giefers"}],"date_updated":"2022-01-06T06:50:49Z","publisher":"Logos Verlag Berlin GmbH","title":"Design and Programming of Reconfigurable Mesh based Many-Cores","publication_status":"published","publication_identifier":{"isbn":["978-3-8325-3165-2"]},"citation":{"apa":"Giefers, H. (2012). <i>Design and Programming of Reconfigurable Mesh based Many-Cores</i>. Berlin: Logos Verlag Berlin GmbH.","bibtex":"@book{Giefers_2012, place={Berlin}, title={Design and Programming of Reconfigurable Mesh based Many-Cores}, publisher={Logos Verlag Berlin GmbH}, author={Giefers, Heiner}, year={2012} }","mla":"Giefers, Heiner. <i>Design and Programming of Reconfigurable Mesh Based Many-Cores</i>. Logos Verlag Berlin GmbH, 2012.","short":"H. Giefers, Design and Programming of Reconfigurable Mesh Based Many-Cores, Logos Verlag Berlin GmbH, Berlin, 2012.","chicago":"Giefers, Heiner. <i>Design and Programming of Reconfigurable Mesh Based Many-Cores</i>. Berlin: Logos Verlag Berlin GmbH, 2012.","ieee":"H. Giefers, <i>Design and Programming of Reconfigurable Mesh based Many-Cores</i>. Berlin: Logos Verlag Berlin GmbH, 2012.","ama":"Giefers H. <i>Design and Programming of Reconfigurable Mesh Based Many-Cores</i>. Berlin: Logos Verlag Berlin GmbH; 2012."},"page":"159","place":"Berlin","year":"2012","user_id":"3118","department":[{"_id":"78"}],"_id":"10652","language":[{"iso":"eng"}],"type":"dissertation","status":"public","abstract":[{"lang":"eng","text":"The paradigm shift towards many-core parallelism is accompanied by two fundamental questions: how should the many processors on a single die communicate to each other and what are suitable programming models for these novel architectures? In this thesis, the author tackles both questions by reviewing the reconfigurable mesh model of massively parallel computation for many-cores.\r\n\r\nThe book presents the design, implementation and evaluation of a many-core architecture that is based on the execution principles and communication infrastructure of the reconfigurable mesh. This work fundamentally rests on FPGA implementations and shows that reconfigurable mesh processors with hundreds of autonomous cores are feasible. Several case studies demonstrate the effectiveness of programming and illustrate why the reconfigurable mesh is a promising model for many-cores."}]}]