---
_id: '45762'
author:
- first_name: Florian
full_name: Simon-Mertens, Florian
last_name: Simon-Mertens
citation:
ama: Simon-Mertens F. Effizienzanalyse Leichtgewichtiger Neuronaler Netze Für
FPGA-Basierte Modulationsklassifikation.; 2023.
apa: Simon-Mertens, F. (2023). Effizienzanalyse leichtgewichtiger Neuronaler
Netze für FPGA-basierte Modulationsklassifikation.
bibtex: '@book{Simon-Mertens_2023, title={Effizienzanalyse leichtgewichtiger Neuronaler
Netze für FPGA-basierte Modulationsklassifikation}, author={Simon-Mertens, Florian},
year={2023} }'
chicago: Simon-Mertens, Florian. Effizienzanalyse Leichtgewichtiger Neuronaler
Netze Für FPGA-Basierte Modulationsklassifikation, 2023.
ieee: F. Simon-Mertens, Effizienzanalyse leichtgewichtiger Neuronaler Netze für
FPGA-basierte Modulationsklassifikation. 2023.
mla: Simon-Mertens, Florian. Effizienzanalyse Leichtgewichtiger Neuronaler Netze
Für FPGA-Basierte Modulationsklassifikation. 2023.
short: F. Simon-Mertens, Effizienzanalyse Leichtgewichtiger Neuronaler Netze Für
FPGA-Basierte Modulationsklassifikation, 2023.
date_created: 2023-06-23T10:41:54Z
date_updated: 2023-06-23T10:42:08Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '52'
name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing'
status: public
supervisor:
- first_name: Felix
full_name: Jentzsch, Felix
id: '55631'
last_name: Jentzsch
orcid: 0000-0003-4987-5708
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
title: Effizienzanalyse leichtgewichtiger Neuronaler Netze für FPGA-basierte Modulationsklassifikation
type: bachelorsthesis
user_id: '55631'
year: '2023'
...
---
_id: '46482'
abstract:
- lang: eng
text: "Ever increasing demands on the performance of microchips are leading to ever
more complex semiconductor technologies with ever shrinking feature sizes. Complex
applications with high demands on safety and reliability, such as autonomous driving,
are simultaneously driving the requirements for test and diagnosis of VLSI circuits.
Throughout the life cycle of a microchip, uncertainties occur that affect its
timing behavior. For example, weak circuit structures, aging effects, or process
variations can lead to a change in the timing behavior of the circuit. While these
uncertainties do not necessarily lead to a change of the functional behavior,
they can lead to a reliability problem.\r\nWith modular and hybrid compaction
two test instruments are presented in this work that can be used for X-tolerant
test response compaction in the built-in Faster-than-At-Speed Test (FAST) which
is used to detect uncertainties in VLSI circuits. One challenge for test response
compaction during FAST is the high and varying X-rate at the outputs of the circuit
under test. By dividing the circuit outputs into test groups and separately compacting
these test groups using stochastic compactors, the modular compaction is able
to handle these high and varying X-rates.\r\nTo deal with uncertainties on logic
interconnects, a method for distinguishing crosstalk and process variation is
presented. In current semiconductor technologies, the number of parasitic coupling
capacitances between logic interconnects is growing. These coupling capacitances
can lead to crosstalk, which causes increased current flow in the logic interconnects,
which in turn can lead to increased electromigration. In the presented method,
delay maps describing the timing behavior of the circuit outputs at different
operating points are used to train artificial neural networks which classify the
tested circuits into fault-free and faulty."
- lang: ger
text: "Immer größere Anforderungen an die Leistungsfähigkeit von Mikrochips führen
zu Halbleitertechnologien mit immer kleiner werdenden Strukturgrößen. Anwendungen
mit hohen Ansprüchen an Sicherheit und Zuverlässigkeit, wie z.B. das autonome
Fahren, treiben gleichzeitig die Anforderungen an den Test hochintegrierter Schaltungen
an. Während des gesamten Lebenszyklus eines Mikrochips kommt es zu Unsicherheiten
im Zeitverhalten. So können z.B. schwache Schaltungsstrukturen, Alterungseffekte
oder Prozessvariationen zu einer Veränderung des Zeitverhaltens führen. Während
diese Unsicherheiten nicht zu einer Veränderung des funktionalen Verhaltens führen
müssen, können sie jedoch zu einem Zuverlässigkeitsproblem führen.\r\nMit der
modularen und der hybriden Kompaktierung werden in dieser Arbeit zwei Testinstrumente
vorgestellt, die für die X-tolerante Testantwortkompaktierung im eingebauten Hochgeschwindigkeitstest
verwendet werden können. Eine Herausforderung für die Testantwortkompaktierung
während des Hochgeschwindigkeitstests ist die hohe und variierende X-Rate an den
Ausgängen der zu testenden Schaltung. Durch die Einteilung der Schaltungsausgänge
in Prüfgruppen und die separierte Kompaktierung der Prüfgruppen mithilfe von stochastischen
Kompaktierern, können die vorgestellten Verfahren diese hohen und variierenden
X-Raten verarbeiten.\r\nFür den Umgang mit Unsicherheiten auf Verbindungsleitungen
der Logik-Schaltung wird ein Verfahren zur Unterscheidung von Übersprechen und
Prozessvariation vorgestellt. In aktuellen Halbleitertechnologien kommt es vermehrt
zu parasitären Koppelkapazitäten zwischen den Verbindungsleitungen. In dem vorgestellten
Verfahren werden künstliche neuronale Netze trainiert, um die Schaltungen in fehlerfrei
und fehlerhaft zu klassifizieren."
author:
- first_name: Alexander
full_name: Sprenger, Alexander
id: '22707'
last_name: Sprenger
orcid: 0000-0002-0775-7677
citation:
ama: Sprenger A. Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten
in Logikblöcken hochintegrierter Schaltungen. Universität Paderborn; 2023.
doi:10.17619/UNIPB/1-1787
apa: Sprenger, A. (2023). Testinstrumente und Testdatenanalyse zur Verarbeitung
von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen. Universität
Paderborn. https://doi.org/10.17619/UNIPB/1-1787
bibtex: '@book{Sprenger_2023, place={Paderborn}, title={Testinstrumente und Testdatenanalyse
zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen},
DOI={10.17619/UNIPB/1-1787},
publisher={Universität Paderborn}, author={Sprenger, Alexander}, year={2023} }'
chicago: 'Sprenger, Alexander. Testinstrumente und Testdatenanalyse zur Verarbeitung
von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen. Paderborn:
Universität Paderborn, 2023. https://doi.org/10.17619/UNIPB/1-1787.'
ieee: 'A. Sprenger, Testinstrumente und Testdatenanalyse zur Verarbeitung von
Unsicherheiten in Logikblöcken hochintegrierter Schaltungen. Paderborn: Universität
Paderborn, 2023.'
mla: Sprenger, Alexander. Testinstrumente und Testdatenanalyse zur Verarbeitung
von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen. Universität
Paderborn, 2023, doi:10.17619/UNIPB/1-1787.
short: A. Sprenger, Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten
in Logikblöcken hochintegrierter Schaltungen, Universität Paderborn, Paderborn,
2023.
date_created: 2023-08-12T09:10:38Z
date_updated: 2023-08-12T09:13:18Z
department:
- _id: '48'
doi: 10.17619/UNIPB/1-1787
extern: '1'
keyword:
- Testantwortkompaktierung
- Prozessvariation
- Silicon Lifecycle Management
language:
- iso: ger
main_file_link:
- open_access: '1'
url: https://nbn-resolving.org/urn:nbn:de:hbz:466:2-45493
oa: '1'
page: xi, 160
place: Paderborn
publication_status: published
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in
Logikblöcken hochintegrierter Schaltungen
type: dissertation
user_id: '22707'
year: '2023'
...
---
_id: '47837'
author:
- first_name: Tim
full_name: Hansmeier, Tim
last_name: Hansmeier
citation:
ama: Hansmeier T. XCS for Self-Awareness in Autonomous Computing Systems.;
2023.
apa: Hansmeier, T. (2023). XCS for Self-awareness in Autonomous Computing Systems.
bibtex: '@book{Hansmeier_2023, title={XCS for Self-awareness in Autonomous Computing
Systems}, author={Hansmeier, Tim}, year={2023} }'
chicago: Hansmeier, Tim. XCS for Self-Awareness in Autonomous Computing Systems,
2023.
ieee: T. Hansmeier, XCS for Self-awareness in Autonomous Computing Systems.
2023.
mla: Hansmeier, Tim. XCS for Self-Awareness in Autonomous Computing Systems.
2023.
short: T. Hansmeier, XCS for Self-Awareness in Autonomous Computing Systems, 2023.
date_created: 2023-10-06T12:45:58Z
date_updated: 2023-10-06T12:46:08Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '1'
grant_number: '160364472'
name: 'SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen
in dynamischen Märkten '
- _id: '4'
name: 'SFB 901 - C: SFB 901 - Project Area C'
- _id: '14'
grant_number: '160364472'
name: 'SFB 901 - C2: SFB 901 - On-The-Fly Compute Centers I: Heterogene Ausführungsumgebungen
(Subproject C2)'
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: XCS for Self-awareness in Autonomous Computing Systems
type: dissertation
user_id: '15504'
year: '2023'
...
---
_id: '29769'
abstract:
- lang: eng
text: 'Wettstreit zwischen der Entwicklung neuer Hardwaretrojaner und entsprechender
Gegenmaßnahmen beschreiten Widersacher immer raffiniertere Wege um Schaltungsentwürfe
zu infizieren und dabei selbst fortgeschrittene Test- und Verifikationsmethoden
zu überlisten. Abgesehen von den konventionellen Methoden um einen Trojaner in
eine Schaltung für ein Field-programmable Gate Array (FPGA) einzuschleusen, können
auch die Entwurfswerkzeuge heimlich kompromittiert werden um einen Angreifer dabei
zu unterstützen einen erfolgreichen Angriff durchzuführen, der zum Beispiel Fehlfunktionen
oder ungewollte Informationsabflüsse bewirken kann. Diese Dissertation beschäftigt
sich hauptsächlich mit den beiden Blickwinkeln auf Hardwaretrojaner in rekonfigurierbaren
Systemen, einerseits der Perspektive des Verteidigers mit einer Methode zur Erkennung
von Trojanern auf der Bitstromebene, und andererseits derjenigen des Angreifers
mit einer neuartigen Angriffsmethode für FPGA Trojaner. Für die Verteidigung gegen
den Trojaner ``Heimtückische LUT'''' stellen wir die allererste erfolgreiche Gegenmaßnahme
vor, die durch Verifikation mittels Proof-carrying Hardware (PCH) auf der Bitstromebene
direkt vor der Konfiguration der Hardware angewendet werden kann, und präsentieren
ein vollständiges Schema für den Entwurf und die Verifikation von Schaltungen
für iCE40 FPGAs. Für die Gegenseite führen wir einen neuen Angriff ein, welcher
bösartiges Routing im eingefügten Trojaner ausnutzt um selbst im fertigen Bitstrom
in einem inaktiven Zustand zu verbleiben: Hierdurch kann dieser neuartige Angriff
zur Zeit weder von herkömmlichen Test- und Verifikationsmethoden, noch von unserer
vorher vorgestellten Verifikation auf der Bitstromebene entdeckt werden.'
- lang: eng
text: The battle of developing hardware Trojans and corresponding countermeasures
has taken adversaries towards ingenious ways of compromising hardware designs
by circumventing even advanced testing and verification methods. Besides conventional
methods of inserting Trojans into a design by a malicious entity, the design flow
for field-programmable gate arrays (FPGAs) can also be surreptitiously compromised
to assist the attacker to perform a successful malfunctioning or information leakage
attack. This thesis mainly focuses on the two aspects of hardware Trojans in reconfigurable
systems, the defenders perspective which corresponds to the bitstream-level Trojan
detection technique, and the attackers perspective which corresponds to a novel
FPGA Trojan attack. From the defender's perspective, we introduce a first-ever
successful pre-configuration countermeasure against the ``Malicious LUT''-hardware
Trojan, by employing bitstream-level Proof-Carrying Hardware (PCH) and present
the complete design-and-verification flow for iCE40 FPGAs. Likewise, from an attackers
perspective, we present a novel attack that leverages malicious routing of the
inserted Trojan circuit to acquire a dormant state even in the generated and transmitted
bitstream. Since the Trojan is injected in a post-synthesis step and remains unconnected
in the bitstream, the presented attack can currently neither be prevented by conventional
testing and verification methods nor by bitstream-level verification techniques.
author:
- first_name: Qazi Arbab
full_name: Ahmed, Qazi Arbab
id: '72764'
last_name: Ahmed
orcid: 0000-0002-1837-2254
citation:
ama: Ahmed QA. Hardware Trojans in Reconfigurable Computing. Paderborn University,
Paderborn, Germany; 2022. doi:10.17619/UNIPB/1-1271
apa: Ahmed, Q. A. (2022). Hardware Trojans in Reconfigurable Computing. Paderborn
University, Paderborn, Germany. https://doi.org/10.17619/UNIPB/1-1271
bibtex: '@book{Ahmed_2022, place={Paderborn}, title={Hardware Trojans in Reconfigurable
Computing}, DOI={10.17619/UNIPB/1-1271},
publisher={ Paderborn University, Paderborn, Germany}, author={Ahmed, Qazi Arbab},
year={2022} }'
chicago: 'Ahmed, Qazi Arbab. Hardware Trojans in Reconfigurable Computing.
Paderborn: Paderborn University, Paderborn, Germany, 2022. https://doi.org/10.17619/UNIPB/1-1271.'
ieee: 'Q. A. Ahmed, Hardware Trojans in Reconfigurable Computing. Paderborn: Paderborn
University, Paderborn, Germany, 2022.'
mla: Ahmed, Qazi Arbab. Hardware Trojans in Reconfigurable Computing. Paderborn
University, Paderborn, Germany, 2022, doi:10.17619/UNIPB/1-1271.
short: Q.A. Ahmed, Hardware Trojans in Reconfigurable Computing, Paderborn University,
Paderborn, Germany, Paderborn, 2022.
date_created: 2022-02-07T14:02:36Z
date_updated: 2022-11-30T13:39:01Z
ddc:
- '004'
department:
- _id: '78'
doi: 10.17619/UNIPB/1-1271
has_accepted_license: '1'
keyword:
- FPGA Security
- Hardware Trojans
- Bitstream-level Trojans
- Bitstream Verification
language:
- iso: eng
main_file_link:
- open_access: '1'
url: "\turn:nbn:de:hbz:466:2-40303"
oa: '1'
place: Paderborn
project:
- _id: '1'
name: 'SFB 901: SFB 901'
- _id: '4'
name: 'SFB 901 - C: SFB 901 - Project Area C'
- _id: '14'
name: 'SFB 901 - C2: SFB 901 - Subproject C2'
publication_status: published
publisher: ' Paderborn University, Paderborn, Germany'
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Hardware Trojans in Reconfigurable Computing
type: dissertation
user_id: '477'
year: '2022'
...
---
_id: '34041'
author:
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
citation:
ama: Witschen LM. Frameworks and Methodologies for Search-Based Approximate Logic
Synthesis.; 2022. doi:10.17619/UNIPB/1-1649
apa: Witschen, L. M. (2022). Frameworks and Methodologies for Search-based Approximate
Logic Synthesis. https://doi.org/10.17619/UNIPB/1-1649
bibtex: '@book{Witschen_2022, title={Frameworks and Methodologies for Search-based
Approximate Logic Synthesis}, DOI={10.17619/UNIPB/1-1649},
author={Witschen, Linus Matthias}, year={2022} }'
chicago: Witschen, Linus Matthias. Frameworks and Methodologies for Search-Based
Approximate Logic Synthesis, 2022. https://doi.org/10.17619/UNIPB/1-1649.
ieee: L. M. Witschen, Frameworks and Methodologies for Search-based Approximate
Logic Synthesis. 2022.
mla: Witschen, Linus Matthias. Frameworks and Methodologies for Search-Based
Approximate Logic Synthesis. 2022, doi:10.17619/UNIPB/1-1649.
short: L.M. Witschen, Frameworks and Methodologies for Search-Based Approximate
Logic Synthesis, 2022.
date_created: 2022-11-09T06:26:22Z
date_updated: 2023-01-19T06:41:22Z
department:
- _id: '78'
doi: 10.17619/UNIPB/1-1649
language:
- iso: eng
project:
- _id: '1'
name: 'SFB 901: SFB 901'
- _id: '3'
name: 'SFB 901 - B: SFB 901 - Project Area B'
- _id: '12'
name: 'SFB 901 - B4: SFB 901 - Subproject B4'
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Frameworks and Methodologies for Search-based Approximate Logic Synthesis
type: dissertation
user_id: '15504'
year: '2022'
...
---
_id: '42839'
author:
- first_name: Florian
full_name: Mehlich, Florian
last_name: Mehlich
citation:
ama: Mehlich F. An Evaluation of XCS on the OpenAI Gym. Paderborn University;
2022.
apa: Mehlich, F. (2022). An Evaluation of XCS on the OpenAI Gym. Paderborn
University.
bibtex: '@book{Mehlich_2022, place={Paderborn}, title={An Evaluation of XCS on the
OpenAI Gym}, publisher={Paderborn University}, author={Mehlich, Florian}, year={2022}
}'
chicago: 'Mehlich, Florian. An Evaluation of XCS on the OpenAI Gym. Paderborn:
Paderborn University, 2022.'
ieee: 'F. Mehlich, An Evaluation of XCS on the OpenAI Gym. Paderborn: Paderborn
University, 2022.'
mla: Mehlich, Florian. An Evaluation of XCS on the OpenAI Gym. Paderborn
University, 2022.
short: F. Mehlich, An Evaluation of XCS on the OpenAI Gym, Paderborn University,
Paderborn, 2022.
date_created: 2023-03-07T12:22:57Z
date_updated: 2023-03-07T12:23:52Z
department:
- _id: '78'
extern: '1'
language:
- iso: eng
place: Paderborn
project:
- _id: '14'
name: 'SFB 901 - C2: SFB 901 - Subproject C2'
- _id: '4'
name: 'SFB 901 - C: SFB 901 - Project Area C'
- _id: '1'
name: 'SFB 901: SFB 901'
publisher: Paderborn University
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Tim
full_name: Hansmeier, Tim
id: '49992'
last_name: Hansmeier
orcid: 0000-0003-1377-3339
title: An Evaluation of XCS on the OpenAI Gym
type: bachelorsthesis
user_id: '49992'
year: '2022'
...
---
_id: '45715'
author:
- first_name: Vanessa Ingrid
full_name: Tcheussi Ngayap, Vanessa Ingrid
last_name: Tcheussi Ngayap
citation:
ama: Tcheussi Ngayap VI. FreeRTOS on a MicroBlaze Soft-Core Processor with Hardware
Accelerators.; 2022.
apa: Tcheussi Ngayap, V. I. (2022). FreeRTOS on a MicroBlaze Soft-Core Processor
with Hardware Accelerators.
bibtex: '@book{Tcheussi Ngayap_2022, title={FreeRTOS on a MicroBlaze Soft-Core Processor
with Hardware Accelerators}, author={Tcheussi Ngayap, Vanessa Ingrid}, year={2022}
}'
chicago: Tcheussi Ngayap, Vanessa Ingrid. FreeRTOS on a MicroBlaze Soft-Core
Processor with Hardware Accelerators, 2022.
ieee: V. I. Tcheussi Ngayap, FreeRTOS on a MicroBlaze Soft-Core Processor with
Hardware Accelerators. 2022.
mla: Tcheussi Ngayap, Vanessa Ingrid. FreeRTOS on a MicroBlaze Soft-Core Processor
with Hardware Accelerators. 2022.
short: V.I. Tcheussi Ngayap, FreeRTOS on a MicroBlaze Soft-Core Processor with Hardware
Accelerators, 2022.
date_created: 2023-06-22T12:04:57Z
date_updated: 2023-06-22T12:07:53Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '83'
name: 'SFB 901 - T1: SFB 901 -Subproject T1'
- _id: '82'
name: 'SFB 901 - T: SFB 901 - Project Area T'
- _id: '1'
grant_number: '160364472'
name: 'SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen
in dynamischen Märkten '
status: public
supervisor:
- first_name: Lennart
full_name: Clausing, Lennart
id: '74287'
last_name: Clausing
orcid: 0000-0003-3789-6034
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
title: FreeRTOS on a MicroBlaze Soft-Core Processor with Hardware Accelerators
type: mastersthesis
user_id: '74287'
year: '2022'
...
---
_id: '26746'
abstract:
- lang: eng
text: "Previous research in proof-carrying hardware has established the feasibility
and utility of the approach, and provided a concrete solution for employing it
for the certification of functional equivalence checking against a specification,
but fell short in connecting it to state-of-the-art formal verification insights,
methods and tools. Due to the immense complexity of modern circuits, and verification
challenges such as the state explosion problem for sequential circuits, this restriction
of readily-available verification solutions severely limited the applicability
of the approach in wider contexts.\r\n\r\nThis thesis closes the gap between the
PCH approach and current advances in formal hardware verification, provides methods
and tools to express and certify a wide range of circuit properties, both functional
and non-functional, and presents for the first time prototypes in which circuits
that are implemented on actual reconfigurable hardware are verified with PCH methods.
Using these results, designers can now apply PCH to establish trust in more complex
circuits, by using more diverse properties which they can express using modern,
efficient property specification techniques."
- lang: ger
text: "Die bisherige Forschung zu Proof-Carrying Hardware (PCH) hat dessen Machbarkeit
und Nützlichkeit gezeigt und einen Ansatz zur Zertifizierung der funktionalen
Äquivalenz zu einer Spezifikation geliefert, jedoch ohne PCH mit aktuellen Erkenntnissen,
Methoden oder Werkzeugen formaler Hardwareverifikation zu verknüpfen. Aufgrund
der Komplexität moderner Schaltungen und Verifikationsherausforderungen wie der
Zustandsexplosion bei sequentiellen Schaltungen, limitiert diese Einschränkung
sofort verfügbarer Verifikationslösungen die Anwendbarkeit des Ansatzes in einem
größeren Kontext signifikant.\r\n\r\nDiese Dissertation schließt die Lücke zwischen
PCH und modernen Entwicklungen in der Schaltungsverifikation und stellt Methoden
und Werkzeuge zur Verfügung, welche die Zertifizierung einer großen Bandbreite
von Schaltungseigenschaften ermöglicht; sowohl funktionale, als auch nicht-funktionale.
Überdies werden erstmals Prototypen vorgestellt in welchen Schaltungen mittels
PCH verifiziert werden, die auf tatsächlicher rekonfigurierbarer Hardware realisiert
sind. Dank dieser Ergebnisse können Entwickler PCH zur Herstellung von Vertrauen
in weit komplexere Schaltungen verwenden, unter Zuhilfenahme einer größeren Vielfalt
von Eigenschaften, welche durch moderne, effiziente Spezifikationstechniken ausgedrückt
werden können."
author:
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
citation:
ama: Wiersema T. Guaranteeing Properties of Reconfigurable Hardware Circuits
with Proof-Carrying Hardware. Paderborn University; 2021.
apa: Wiersema, T. (2021). Guaranteeing Properties of Reconfigurable Hardware
Circuits with Proof-Carrying Hardware. Paderborn University.
bibtex: '@book{Wiersema_2021, place={Paderborn}, title={Guaranteeing Properties
of Reconfigurable Hardware Circuits with Proof-Carrying Hardware}, publisher={Paderborn
University}, author={Wiersema, Tobias}, year={2021} }'
chicago: 'Wiersema, Tobias. Guaranteeing Properties of Reconfigurable Hardware
Circuits with Proof-Carrying Hardware. Paderborn: Paderborn University, 2021.'
ieee: 'T. Wiersema, Guaranteeing Properties of Reconfigurable Hardware Circuits
with Proof-Carrying Hardware. Paderborn: Paderborn University, 2021.'
mla: Wiersema, Tobias. Guaranteeing Properties of Reconfigurable Hardware Circuits
with Proof-Carrying Hardware. Paderborn University, 2021.
short: T. Wiersema, Guaranteeing Properties of Reconfigurable Hardware Circuits
with Proof-Carrying Hardware, Paderborn University, Paderborn, 2021.
date_created: 2021-10-25T06:35:41Z
date_updated: 2022-01-06T06:57:26Z
ddc:
- '006'
department:
- _id: '78'
keyword:
- Proof-Carrying Hardware
- Formal Verification
- Sequential Circuits
- Non-Functional Properties
- Functional Properties
language:
- iso: eng
main_file_link:
- open_access: '1'
url: https://nbn-resolving.de/urn:nbn:de:hbz:466:2-39800
oa: '1'
page: '293'
place: Paderborn
project:
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
- _id: '12'
name: SFB 901 - Subproject B4
publication_status: published
publisher: Paderborn University
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying
Hardware
type: dissertation
user_id: '3118'
year: '2021'
...
---
_id: '29151'
abstract:
- lang: eng
text: Automation becomes a vital part in the High-Performance computing system in
situational dynamics to take the decisions on the fly. Heterogeneous compute nodes
consist of computing resources such as CPU, GPU and FPGA and are the important
components of the high-performance computing system that can adapt the automation
to achieve the given goal. While implanting automation in the computing resources,
management of the resources is one of the essential aspects that need to be taken
care of. Tasks are continuously executed on the resources using its unique characteristics.
Effective scheduling is essential to make the best use of the characteristics
provided by each resource. Scheduling enables the execution of each task by allocating
resources so that they take advantage of all the characteristics of the compute
resources. Various scheduling heuristics can be used to create effective scheduling,
which might require the execution time to schedule the task efficiently. Providing
actual execution time is not possible in many cases; hence we can provide the
estimations for the actual execution time . The purpose of this master's thesis
is to design a predictive model or system that estimates the execution time required
to execute tasks using historical execution time data on the heterogeneous compute
nodes. In this thesis, regression techniques(SGD Regressor, Passive-Aggressive
Regressor, MLP Regressor, and XCSF Regressor) are compared in terms of their prediction
accuracy in order to determine which technique produces reliable predictions for
the execution time. These estimations must be generated in an online learning
environment in which data points arrive in any sequence, one by one, and the regression
model must learn from them. After evaluating the regression algorithms, it is
seen that the XCSF regressor provides the highest overall prediction accuracy
for the supplied data sets. The regression technique's parameters also play a
significant role in achieving an acceptable prediction accuracy. As a remark,
when using online learning in regression analysis, the accuracy depends upon both
the order of sequential data points that are coming to train the model and the
parameter configuration for each regression technique.
author:
- first_name: Chinmay
full_name: Kashikar, Chinmay
last_name: Kashikar
citation:
ama: Kashikar C. A Comparison of Machine Learning Techniques for the On-Line
Characterization of Tasks Executed on Heterogeneous Compute Nodes. Paderborn
University; 2021.
apa: Kashikar, C. (2021). A Comparison of Machine Learning Techniques for the
On-line Characterization of Tasks Executed on Heterogeneous Compute Nodes.
Paderborn University.
bibtex: '@book{Kashikar_2021, place={Paderborn}, title={A Comparison of Machine
Learning Techniques for the On-line Characterization of Tasks Executed on Heterogeneous
Compute Nodes}, publisher={Paderborn University}, author={Kashikar, Chinmay},
year={2021} }'
chicago: 'Kashikar, Chinmay. A Comparison of Machine Learning Techniques for
the On-Line Characterization of Tasks Executed on Heterogeneous Compute Nodes.
Paderborn: Paderborn University, 2021.'
ieee: 'C. Kashikar, A Comparison of Machine Learning Techniques for the On-line
Characterization of Tasks Executed on Heterogeneous Compute Nodes. Paderborn:
Paderborn University, 2021.'
mla: Kashikar, Chinmay. A Comparison of Machine Learning Techniques for the On-Line
Characterization of Tasks Executed on Heterogeneous Compute Nodes. Paderborn
University, 2021.
short: C. Kashikar, A Comparison of Machine Learning Techniques for the On-Line
Characterization of Tasks Executed on Heterogeneous Compute Nodes, Paderborn University,
Paderborn, 2021.
date_created: 2022-01-04T09:24:52Z
date_updated: 2022-01-06T06:58:46Z
department:
- _id: '78'
language:
- iso: eng
place: Paderborn
project:
- _id: '14'
name: SFB 901 - Subproject C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '1'
name: SFB 901
publisher: Paderborn University
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Tim
full_name: Hansmeier, Tim
id: '49992'
last_name: Hansmeier
orcid: 0000-0003-1377-3339
title: A Comparison of Machine Learning Techniques for the On-line Characterization
of Tasks Executed on Heterogeneous Compute Nodes
type: mastersthesis
user_id: '49992'
year: '2021'
...
---
_id: '22216'
author:
- first_name: Jakob Werner
full_name: Rehnen, Jakob Werner
last_name: Rehnen
citation:
ama: Rehnen JW. Decomposition of Arithmetic Components for the Approximate Circuit
Synthesis with EvoApproxLib.; 2021.
apa: Rehnen, J. W. (2021). Decomposition of Arithmetic Components for the Approximate
Circuit Synthesis with EvoApproxLib.
bibtex: '@book{Rehnen_2021, title={Decomposition of Arithmetic Components for the
Approximate Circuit Synthesis with EvoApproxLib}, author={Rehnen, Jakob Werner},
year={2021} }'
chicago: Rehnen, Jakob Werner. Decomposition of Arithmetic Components for the
Approximate Circuit Synthesis with EvoApproxLib, 2021.
ieee: J. W. Rehnen, Decomposition of Arithmetic Components for the Approximate
Circuit Synthesis with EvoApproxLib. 2021.
mla: Rehnen, Jakob Werner. Decomposition of Arithmetic Components for the Approximate
Circuit Synthesis with EvoApproxLib. 2021.
short: J.W. Rehnen, Decomposition of Arithmetic Components for the Approximate Circuit
Synthesis with EvoApproxLib, 2021.
date_created: 2021-05-19T16:56:11Z
date_updated: 2022-01-06T06:55:29Z
department:
- _id: '78'
- _id: '7'
language:
- iso: eng
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
title: Decomposition of Arithmetic Components for the Approximate Circuit Synthesis
with EvoApproxLib
type: bachelorsthesis
user_id: '49051'
year: '2021'
...
---
_id: '22483'
abstract:
- lang: eng
text: This bachelor thesis presents a C/C++ implementation of the XCS algorithm
for an embedded system and profiling results concerning the execution time of
the functions. These are then analyzed in relation to the input characteristics
of the examined learning environments and compared with related work. Three main
conclusions can be drawn from the measured results. First, the maximum size of
the population of the classifiers influences the runtime of the genetic algorithm;
second, the size of the input space has a direct effect on the execution time
of the matching function; and last, a larger action space results in a longer
runtime generating the prediction for the possible actions. The dependencies identified
here can serve to optimize the computational efficiency and make XCS more suitable
for embedded systems.
author:
- first_name: Mathis
full_name: Brede, Mathis
last_name: Brede
citation:
ama: 'Brede M. Implementation and Profiling of XCS in the Context of Embedded
Systems. Paderborn: Paderborn University; 2021.'
apa: 'Brede, M. (2021). Implementation and Profiling of XCS in the Context of
Embedded Systems. Paderborn: Paderborn University.'
bibtex: '@book{Brede_2021, place={Paderborn}, title={Implementation and Profiling
of XCS in the Context of Embedded Systems}, publisher={Paderborn University},
author={Brede, Mathis}, year={2021} }'
chicago: 'Brede, Mathis. Implementation and Profiling of XCS in the Context of
Embedded Systems. Paderborn: Paderborn University, 2021.'
ieee: 'M. Brede, Implementation and Profiling of XCS in the Context of Embedded
Systems. Paderborn: Paderborn University, 2021.'
mla: Brede, Mathis. Implementation and Profiling of XCS in the Context of Embedded
Systems. Paderborn University, 2021.
short: M. Brede, Implementation and Profiling of XCS in the Context of Embedded
Systems, Paderborn University, Paderborn, 2021.
date_created: 2021-06-21T09:35:03Z
date_updated: 2022-01-06T06:55:33Z
department:
- _id: '78'
extern: '1'
language:
- iso: eng
place: Paderborn
project:
- _id: '14'
name: SFB 901 - Subproject C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '1'
name: SFB 901
publisher: Paderborn University
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Tim
full_name: Hansmeier, Tim
id: '49992'
last_name: Hansmeier
orcid: 0000-0003-1377-3339
title: Implementation and Profiling of XCS in the Context of Embedded Systems
type: bachelorsthesis
user_id: '477'
year: '2021'
...
---
_id: '29540'
abstract:
- lang: eng
text: "Autonomous mobile robots are becoming increasingly more capable and widespread.
Reliable Obstacle avoidance is an integral part of autonomous navigation. This
involves real time interpretation and processing of a complex environment. Strict
time and energy constraints of a mobile autonomous system make efficient computation
extremely desirable. The benefits of employing Hardware/Software co-designed applications
are obvious and significant. Hardware accelerators are used for efficient processing
of the algorithms by exploiting parallelism. FPGAs are a class of hardware accelerators,
which\r\ncan contain hundreds of small execution units, and can be used for Hardware/Software
co-designed application. However, there is a reluctance when it comes to adoption
of these devices in well established application domains, such as Robotics, due
to a steep learning curve needed for FPGA application design. ReconROS has successfully
bridged the gap between robotic and FPGA application development, by providing
an intuitive, common development platform for robotic application development
for FPGA. It does so by integrating Robotics Operating System(ROS) which is an
industry and academia standard for robotics application development, with ReconOS,
an operating system for re-configurable hardware. In this thesis an obstacle avoidance
system is designed and implemented for an autonomous vehicle using ReconROS. The
objectives of the thesis is to demonstrate and explore ReconROS integration within
the ROS ecosystem and explore the design process within ReconROS framework, and
to demonstrate the effectiveness of Hardware Acceleration in Robotics, by analysing
the resulting architectures for Latency and Power Consumption."
author:
- first_name: Muhammad Aamir
full_name: Sheikh, Muhammad Aamir
last_name: Sheikh
citation:
ama: Sheikh MA. Design and Implementation of a ReconROS-Based Obstacle Avoidance
System. Paderborn University; 2021.
apa: Sheikh, M. A. (2021). Design and Implementation of a ReconROS-based Obstacle
Avoidance System. Paderborn University.
bibtex: '@book{Sheikh_2021, title={Design and Implementation of a ReconROS-based
Obstacle Avoidance System}, publisher={Paderborn University}, author={Sheikh,
Muhammad Aamir}, year={2021} }'
chicago: Sheikh, Muhammad Aamir. Design and Implementation of a ReconROS-Based
Obstacle Avoidance System. Paderborn University, 2021.
ieee: M. A. Sheikh, Design and Implementation of a ReconROS-based Obstacle Avoidance
System. Paderborn University, 2021.
mla: Sheikh, Muhammad Aamir. Design and Implementation of a ReconROS-Based Obstacle
Avoidance System. Paderborn University, 2021.
short: M.A. Sheikh, Design and Implementation of a ReconROS-Based Obstacle Avoidance
System, Paderborn University, 2021.
date_created: 2022-01-26T08:50:52Z
date_updated: 2022-01-28T08:30:46Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Lienen, Christian
id: '60323'
last_name: Lienen
title: Design and Implementation of a ReconROS-based Obstacle Avoidance System
type: mastersthesis
user_id: '60323'
year: '2021'
...
---
_id: '21324'
author:
- first_name: Khushboo
full_name: Chandrakar, Khushboo
last_name: Chandrakar
citation:
ama: Chandrakar K. Comparison of Feature Selection Techniques to Improve Approximate
Circuit Synthesis.; 2020.
apa: Chandrakar, K. (2020). Comparison of Feature Selection Techniques to Improve
Approximate Circuit Synthesis.
bibtex: '@book{Chandrakar_2020, title={Comparison of Feature Selection Techniques
to Improve Approximate Circuit Synthesis}, author={Chandrakar, Khushboo}, year={2020}
}'
chicago: Chandrakar, Khushboo. Comparison of Feature Selection Techniques to
Improve Approximate Circuit Synthesis, 2020.
ieee: K. Chandrakar, Comparison of Feature Selection Techniques to Improve Approximate
Circuit Synthesis. 2020.
mla: Chandrakar, Khushboo. Comparison of Feature Selection Techniques to Improve
Approximate Circuit Synthesis. 2020.
short: K. Chandrakar, Comparison of Feature Selection Techniques to Improve Approximate
Circuit Synthesis, 2020.
date_created: 2021-03-01T09:19:29Z
date_updated: 2022-01-06T06:54:54Z
department:
- _id: '78'
- _id: '7'
language:
- iso: eng
project:
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
title: Comparison of Feature Selection Techniques to Improve Approximate Circuit Synthesis
type: mastersthesis
user_id: '49051'
year: '2020'
...
---
_id: '21432'
abstract:
- lang: eng
text: "Robots are becoming increasingly autonomous and more capable. Because of
a limited portable energy budget by e.g. batteries, and more demanding algorithms,
an efficient computation is of interest. Field Programmable Gate Arrays (FPGAs)
for example can provide fast and efficient processing and the Robot Operating
System (ROS) is a popular\r\nmiddleware used for robotic applications. The novel
ReconROS combines version 2 of the Robot Operating System with ReconOS, a framework
for integrating reconfigurable hardware. It provides a unified interface between
software and hardware. ReconROS is evaluated in this thesis by implementing a
Sobel filter as the video processing application, running on a Zynq-7000 series
System on Chip. Timing measurements were taken of execution and transfer times
and were compared to theoretical values. Designing the hardware implementation
is done by C code using High Level Synthesis and with the interface and functionality
provided by ReconROS. An important aspect is the publish/subscribe mechanism of
ROS. The Operating System interface functions for publishing and subscribing are
reasonably fast at below 10 ms for a 1 MB color VGA image. The main memory interface
performs well at higher data sizes, crossing 100 MB/s at 20 kB and increasing
to a maximum of around 150 MB/s. Furthermore, the hardware implementation introduces
consistency to the execution times and performs twice as fast as the software
implementation."
author:
- first_name: Luca-Sebastian
full_name: Henke, Luca-Sebastian
last_name: Henke
citation:
ama: Henke L-S. Evaluation of a ReconOS-ROS Combination Based on a Video Processing
Application.; 2020.
apa: Henke, L.-S. (2020). Evaluation of a ReconOS-ROS Combination based on a
Video Processing Application.
bibtex: '@book{Henke_2020, title={Evaluation of a ReconOS-ROS Combination based
on a Video Processing Application}, author={Henke, Luca-Sebastian}, year={2020}
}'
chicago: Henke, Luca-Sebastian. Evaluation of a ReconOS-ROS Combination Based
on a Video Processing Application, 2020.
ieee: L.-S. Henke, Evaluation of a ReconOS-ROS Combination based on a Video Processing
Application. 2020.
mla: Henke, Luca-Sebastian. Evaluation of a ReconOS-ROS Combination Based on
a Video Processing Application. 2020.
short: L.-S. Henke, Evaluation of a ReconOS-ROS Combination Based on a Video Processing
Application, 2020.
date_created: 2021-03-10T07:07:01Z
date_updated: 2022-01-06T06:54:59Z
department:
- _id: '78'
language:
- iso: eng
status: public
supervisor:
- first_name: Christian
full_name: Lienen, Christian
id: '60323'
last_name: Lienen
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Evaluation of a ReconOS-ROS Combination based on a Video Processing Application
type: bachelorsthesis
user_id: '60323'
year: '2020'
...
---
_id: '20820'
author:
- first_name: Simon
full_name: Thiele, Simon
last_name: Thiele
citation:
ama: Thiele S. Implementing Machine Learning Functions as PYNQ FPGA Overlays.;
2020.
apa: Thiele, S. (2020). Implementing Machine Learning Functions as PYNQ FPGA
Overlays.
bibtex: '@book{Thiele_2020, title={Implementing Machine Learning Functions as PYNQ
FPGA Overlays}, author={Thiele, Simon}, year={2020} }'
chicago: Thiele, Simon. Implementing Machine Learning Functions as PYNQ FPGA
Overlays, 2020.
ieee: S. Thiele, Implementing Machine Learning Functions as PYNQ FPGA Overlays.
2020.
mla: Thiele, Simon. Implementing Machine Learning Functions as PYNQ FPGA Overlays.
2020.
short: S. Thiele, Implementing Machine Learning Functions as PYNQ FPGA Overlays,
2020.
date_created: 2020-12-21T13:59:55Z
date_updated: 2022-01-06T06:54:40Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '1'
name: SFB 901
- _id: '82'
name: SFB 901 - Project Area T
- _id: '83'
name: SFB 901 -Subproject T1
status: public
supervisor:
- first_name: Lennart
full_name: Clausing, Lennart
id: '74287'
last_name: Clausing
orcid: 0000-0003-3789-6034
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
title: Implementing Machine Learning Functions as PYNQ FPGA Overlays
type: bachelorsthesis
user_id: '74287'
year: '2020'
...
---
_id: '20821'
author:
- first_name: Vivek
full_name: Jaganath, Vivek
last_name: Jaganath
citation:
ama: Jaganath V. Extension and Evaluation of Python-Based High-Level Synthesis
Tool Flows.; 2020.
apa: Jaganath, V. (2020). Extension and Evaluation of Python-based High-Level
Synthesis Tool Flows.
bibtex: '@book{Jaganath_2020, title={Extension and Evaluation of Python-based High-Level
Synthesis Tool Flows}, author={Jaganath, Vivek}, year={2020} }'
chicago: Jaganath, Vivek. Extension and Evaluation of Python-Based High-Level
Synthesis Tool Flows, 2020.
ieee: V. Jaganath, Extension and Evaluation of Python-based High-Level Synthesis
Tool Flows. 2020.
mla: Jaganath, Vivek. Extension and Evaluation of Python-Based High-Level Synthesis
Tool Flows. 2020.
short: V. Jaganath, Extension and Evaluation of Python-Based High-Level Synthesis
Tool Flows, 2020.
date_created: 2020-12-21T14:02:42Z
date_updated: 2022-01-06T06:54:40Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '1'
name: SFB 901
- _id: '82'
name: SFB 901 - Project Area T
- _id: '83'
name: SFB 901 -Subproject T1
status: public
supervisor:
- first_name: Lennart
full_name: Clausing, Lennart
id: '74287'
last_name: Clausing
orcid: 0000-0003-3789-6034
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
title: Extension and Evaluation of Python-based High-Level Synthesis Tool Flows
type: mastersthesis
user_id: '74287'
year: '2020'
...
---
_id: '21433'
abstract:
- lang: eng
text: "Modern machine learning (ML) techniques continue to move into the embedded
system space because traditional centralized compute resources do not suit certain
application domains, for example in mobile or real-time environments. Google’s
TensorFlow Lite (TFLite) framework supports this shift from cloud to edge computing
and makes ML inference accessible on resource-constrained devices. While it offers
the possibility to partially delegate computation to hardware accelerators, there
is no such “delegate” available to utilize the promising characteristics of reconfigurable
hardware.\r\nThis thesis incorporates modern platform FPGAs into TFLite by implementing
a modular delegate framework, which allows accelerators within the programmable
logic to take over the execution of neural network layers. To facilitate the necessary
hardware/software codesign, the FPGA delegate is based on the operating system
for reconfigurable\r\ncomputing (ReconOS), whose partial reconfiguration support
enables the instantiation of model-tailored accelerator architectures. In the
hardware back-end, a streaming-based prototype accelerator for the MobileNet model
family showcases the working order of the platform, but falls short of the desired
performance. Thus, it indicates the need for further exploration of alternative
accelerator designs, which the delegate could automatically synthesize to meet
a model’s demands."
author:
- first_name: Felix P.
full_name: Jentzsch, Felix P.
last_name: Jentzsch
citation:
ama: Jentzsch FP. Design and Implementation of a ReconOS-Based TensorFlow Lite
Delegate Architecture.; 2020.
apa: Jentzsch, F. P. (2020). Design and Implementation of a ReconOS-based TensorFlow
Lite Delegate Architecture.
bibtex: '@book{Jentzsch_2020, title={Design and Implementation of a ReconOS-based
TensorFlow Lite Delegate Architecture}, author={Jentzsch, Felix P.}, year={2020}
}'
chicago: Jentzsch, Felix P. Design and Implementation of a ReconOS-Based TensorFlow
Lite Delegate Architecture, 2020.
ieee: F. P. Jentzsch, Design and Implementation of a ReconOS-based TensorFlow
Lite Delegate Architecture. 2020.
mla: Jentzsch, Felix P. Design and Implementation of a ReconOS-Based TensorFlow
Lite Delegate Architecture. 2020.
short: F.P. Jentzsch, Design and Implementation of a ReconOS-Based TensorFlow Lite
Delegate Architecture, 2020.
date_created: 2021-03-10T07:09:14Z
date_updated: 2023-07-09T17:12:52Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '1'
grant_number: '160364472'
name: 'SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen
in dynamischen Märkten '
- _id: '82'
name: 'SFB 901 - T: SFB 901 - Project Area T'
- _id: '83'
name: 'SFB 901 - T1: SFB 901 -Subproject T1'
status: public
supervisor:
- first_name: Christian
full_name: Lienen, Christian
id: '60323'
last_name: Lienen
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
title: Design and Implementation of a ReconOS-based TensorFlow Lite Delegate Architecture
type: mastersthesis
user_id: '398'
year: '2020'
...
---
_id: '15920'
abstract:
- lang: eng
text: "Secure hardware design is the most important aspect to be considered in addition
to functional correctness. Achieving hardware security in today’s globalized Integrated
Cir- cuit(IC) supply chain is a challenging task. One solution that is widely
considered to help achieve secure hardware designs is Information Flow Tracking(IFT).
It provides an ap- proach to verify that the systems adhere to security properties
either by static verification during design phase or dynamic checking during runtime.\r\nProof-Carrying
Hardware(PCH) is an approach to verify a functional design prior to using it in
hardware. It is a two-party verification approach, where the target party, the
consumer requests new functionalities with pre-defined properties to the producer.
In response, the producer designs the IP (Intellectual Property) cores with the
requested functionalities that adhere to the consumer-defined properties. The
producer provides the IP cores and a proof certificate combined into a proof-carrying
bitstream to the consumer to verify it. If the verification is successful, the
consumer can use the IP cores in his hardware. In essence, the consumer can only
run verified IP cores. Correctly applied, PCH techniques can help consumers to
defend against many unintentional modifications and malicious alterations of the
modules they receive. There are numerous published examples of how to use PCH
to detect any change in the functionality of a circuit, i.e., pairing a PCH approach
with functional equivalence checking for combinational or sequential circuits.
For non-functional properties, since opening new covert channels to leak secret
information from secure circuits is a viable attack vector for hardware trojans,
i.e., intentionally added malicious circuitry, IFT technique is employed to make
sure that secret/untrusted information never reaches any unclassified/trusted
outputs.\r\nThis master thesis aims to explore the possibility of adapting Information
Flow Tracking into a Proof-Carrying Hardware scenario. It aims to create a method
that combines Infor- mation Flow Tracking(IFT) with a PCH approach at bitstream
level enabling consumers to validate the trustworthiness of a module’s information
flow without the computational costs of a complete flow analysis."
author:
- first_name: Monica
full_name: Keerthipati, Monica
last_name: Keerthipati
citation:
ama: Keerthipati M. A Bitstream-Level Proof-Carrying Hardware Technique for Information
Flow Tracking. Universität Paderborn; 2019.
apa: Keerthipati, M. (2019). A Bitstream-Level Proof-Carrying Hardware Technique
for Information Flow Tracking. Universität Paderborn.
bibtex: '@book{Keerthipati_2019, title={A Bitstream-Level Proof-Carrying Hardware
Technique for Information Flow Tracking}, publisher={Universität Paderborn}, author={Keerthipati,
Monica}, year={2019} }'
chicago: Keerthipati, Monica. A Bitstream-Level Proof-Carrying Hardware Technique
for Information Flow Tracking. Universität Paderborn, 2019.
ieee: M. Keerthipati, A Bitstream-Level Proof-Carrying Hardware Technique for
Information Flow Tracking. Universität Paderborn, 2019.
mla: Keerthipati, Monica. A Bitstream-Level Proof-Carrying Hardware Technique
for Information Flow Tracking. Universität Paderborn, 2019.
short: M. Keerthipati, A Bitstream-Level Proof-Carrying Hardware Technique for Information
Flow Tracking, Universität Paderborn, 2019.
date_created: 2020-02-17T12:03:40Z
date_updated: 2022-01-06T06:52:41Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '3'
name: SFB 901 - Project Area B
- _id: '1'
name: SFB 901
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
title: A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking
type: mastersthesis
user_id: '477'
year: '2019'
...
---
_id: '14831'
author:
- first_name: Nithin S.
full_name: Sabu, Nithin S.
last_name: Sabu
citation:
ama: Sabu NS. FPGA Acceleration of String Search Techniques in Huge Data Sets.
Paderborn University; 2019.
apa: Sabu, N. S. (2019). FPGA Acceleration of String Search Techniques in Huge
Data Sets. Paderborn University.
bibtex: '@book{Sabu_2019, title={FPGA Acceleration of String Search Techniques in
Huge Data Sets}, publisher={Paderborn University}, author={Sabu, Nithin S.}, year={2019}
}'
chicago: Sabu, Nithin S. FPGA Acceleration of String Search Techniques in Huge
Data Sets. Paderborn University, 2019.
ieee: N. S. Sabu, FPGA Acceleration of String Search Techniques in Huge Data
Sets. Paderborn University, 2019.
mla: Sabu, Nithin S. FPGA Acceleration of String Search Techniques in Huge Data
Sets. Paderborn University, 2019.
short: N.S. Sabu, FPGA Acceleration of String Search Techniques in Huge Data Sets,
Paderborn University, 2019.
date_created: 2019-11-06T12:06:09Z
date_updated: 2022-01-06T06:52:07Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Stefan
full_name: Böttcher, Stefan
last_name: Böttcher
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
title: FPGA Acceleration of String Search Techniques in Huge Data Sets
type: mastersthesis
user_id: '3118'
year: '2019'
...
---
_id: '14546'
author:
- first_name: Tim
full_name: Hansmeier, Tim
id: '49992'
last_name: Hansmeier
orcid: 0000-0003-1377-3339
citation:
ama: Hansmeier T. Autonomous Operation of High-Performance Compute Nodes through
Self-Awareness and Learning Classifiers. Universität Paderborn; 2019.
apa: Hansmeier, T. (2019). Autonomous Operation of High-Performance Compute Nodes
through Self-Awareness and Learning Classifiers. Universität Paderborn.
bibtex: '@book{Hansmeier_2019, title={Autonomous Operation of High-Performance Compute
Nodes through Self-Awareness and Learning Classifiers}, publisher={Universität
Paderborn}, author={Hansmeier, Tim}, year={2019} }'
chicago: Hansmeier, Tim. Autonomous Operation of High-Performance Compute Nodes
through Self-Awareness and Learning Classifiers. Universität Paderborn, 2019.
ieee: T. Hansmeier, Autonomous Operation of High-Performance Compute Nodes through
Self-Awareness and Learning Classifiers. Universität Paderborn, 2019.
mla: Hansmeier, Tim. Autonomous Operation of High-Performance Compute Nodes through
Self-Awareness and Learning Classifiers. Universität Paderborn, 2019.
short: T. Hansmeier, Autonomous Operation of High-Performance Compute Nodes through
Self-Awareness and Learning Classifiers, Universität Paderborn, 2019.
date_created: 2019-11-05T14:32:46Z
date_updated: 2022-01-06T06:52:02Z
department:
- _id: '78'
- _id: '34'
- _id: '7'
language:
- iso: eng
project:
- _id: '14'
name: SFB 901 - Subproject C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '1'
name: SFB 901
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Autonomous Operation of High-Performance Compute Nodes through Self-Awareness
and Learning Classifiers
type: mastersthesis
user_id: '477'
year: '2019'
...
---
_id: '15874'
author:
- first_name: Christian
full_name: Lienen, Christian
id: '60323'
last_name: Lienen
citation:
ama: Lienen C. Implementing a Real-Time System on a Platform FPGA Operated with
ReconOS. Universität Paderborn
apa: Lienen, C. (n.d.). Implementing a Real-time System on a Platform FPGA operated
with ReconOS. Universität Paderborn.
bibtex: '@book{Lienen, title={Implementing a Real-time System on a Platform FPGA
operated with ReconOS}, publisher={Universität Paderborn}, author={Lienen, Christian}
}'
chicago: Lienen, Christian. Implementing a Real-Time System on a Platform FPGA
Operated with ReconOS. Universität Paderborn, n.d.
ieee: C. Lienen, Implementing a Real-time System on a Platform FPGA operated
with ReconOS. Universität Paderborn.
mla: Lienen, Christian. Implementing a Real-Time System on a Platform FPGA Operated
with ReconOS. Universität Paderborn.
short: C. Lienen, Implementing a Real-Time System on a Platform FPGA Operated with
ReconOS, Universität Paderborn, n.d.
date_created: 2020-02-11T10:22:06Z
date_updated: 2023-07-31T11:58:50Z
ddc:
- '004'
department:
- _id: '78'
file:
- access_level: open_access
content_type: application/pdf
creator: clienen
date_created: 2020-07-01T11:46:49Z
date_updated: 2021-02-13T16:46:58Z
file_id: '17351'
file_name: thesis_main.pdf
file_size: 5920668
relation: main_file
file_date_updated: 2021-02-13T16:46:58Z
has_accepted_license: '1'
language:
- iso: eng
oa: '1'
project:
- _id: '83'
name: 'SFB 901 - T1: SFB 901 -Subproject T1'
- _id: '82'
name: 'SFB 901 - T: SFB 901 - Project Area T'
- _id: '1'
grant_number: '160364472'
name: 'SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen
in dynamischen Märkten '
publication_status: submitted
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Lennart
full_name: Clausing, Lennart
id: '74287'
last_name: Clausing
orcid: 0000-0003-3789-6034
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
title: Implementing a Real-time System on a Platform FPGA operated with ReconOS
type: mastersthesis
user_id: '60323'
year: '2019'
...
---
_id: '3365'
author:
- first_name: Jan-Philip
full_name: Schnuer, Jan-Philip
last_name: Schnuer
citation:
ama: Schnuer J-P. Static Scheduling Algorithms for Heterogeneous Compute Nodes.
Universität Paderborn; 2018.
apa: Schnuer, J.-P. (2018). Static Scheduling Algorithms for Heterogeneous Compute
Nodes. Universität Paderborn.
bibtex: '@book{Schnuer_2018, title={Static Scheduling Algorithms for Heterogeneous
Compute Nodes}, publisher={Universität Paderborn}, author={Schnuer, Jan-Philip},
year={2018} }'
chicago: Schnuer, Jan-Philip. Static Scheduling Algorithms for Heterogeneous
Compute Nodes. Universität Paderborn, 2018.
ieee: J.-P. Schnuer, Static Scheduling Algorithms for Heterogeneous Compute Nodes.
Universität Paderborn, 2018.
mla: Schnuer, Jan-Philip. Static Scheduling Algorithms for Heterogeneous Compute
Nodes. Universität Paderborn, 2018.
short: J.-P. Schnuer, Static Scheduling Algorithms for Heterogeneous Compute Nodes,
Universität Paderborn, 2018.
date_created: 2018-06-26T14:10:18Z
date_updated: 2022-01-06T06:59:13Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '14'
name: SFB 901 - Subproject C2
- _id: '1'
name: SFB 901
- _id: '4'
name: SFB 901 - Project Area C
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Achim
full_name: Lösch, Achim
id: '43646'
last_name: Lösch
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Static Scheduling Algorithms for Heterogeneous Compute Nodes
type: bachelorsthesis
user_id: '477'
year: '2018'
...
---
_id: '3366'
author:
- first_name: Marcel
full_name: Croce, Marcel
last_name: Croce
citation:
ama: Croce M. Evaluation of OpenCL-Based Compilation for FPGAs. Universität
Paderborn; 2018.
apa: Croce, M. (2018). Evaluation of OpenCL-based Compilation for FPGAs.
Universität Paderborn.
bibtex: '@book{Croce_2018, title={Evaluation of OpenCL-based Compilation for FPGAs},
publisher={Universität Paderborn}, author={Croce, Marcel}, year={2018} }'
chicago: Croce, Marcel. Evaluation of OpenCL-Based Compilation for FPGAs.
Universität Paderborn, 2018.
ieee: M. Croce, Evaluation of OpenCL-based Compilation for FPGAs. Universität
Paderborn, 2018.
mla: Croce, Marcel. Evaluation of OpenCL-Based Compilation for FPGAs. Universität
Paderborn, 2018.
short: M. Croce, Evaluation of OpenCL-Based Compilation for FPGAs, Universität Paderborn,
2018.
date_created: 2018-06-26T14:12:00Z
date_updated: 2022-01-06T06:59:13Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '14'
name: SFB 901 - Subproject C2
- _id: '1'
name: SFB 901
- _id: '4'
name: SFB 901 - Project Area C
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Achim
full_name: Lösch, Achim
id: '43646'
last_name: Lösch
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Evaluation of OpenCL-based Compilation for FPGAs
type: bachelorsthesis
user_id: '477'
year: '2018'
...
---
_id: '3720'
abstract:
- lang: eng
text: Traditional cache design uses a consolidated block of memory address bits
to index a cache set, equivalent to the use of modulo functions. While this module-based
mapping scheme is widely used in contemporary cache structures due to the simplicity
of its hardware design and its good performance for sequences of consecutive addresses,
its use may not be satisfactory for a variety of application domains having different
characteristics.This thesis presents a new type of cache mapping scheme, motivated
by programmable capabilities combined with Nature-inspired optimization of reconfigurable
hardware. This research has focussed on an FPGA-based evolvable cache structure
of the first level cache in a multi-core processor architecture, able to dynamically
change cache indexing. To solve the challenge of reconfigurable cache mappings,
a programmable Boolean circuit based on a combination of Look-up Table (LUT) memory
elements is proposed. Focusing on optimization aspects at the system level, a
Performance Measurement Infrastructure is introduced that is able to monitor the
underlying microarchitectural metrics, and an adaptive evaluation strategy is
presented that leverages on Evolutionary Algorithms, that is not only capable
of evolving application-specific address-to-cache-index mappings for level one
split caches but also of reducing optimization times. Putting this all together
and prototyping in an FPGA for a LEON3/Linux-based multi-core processor, the creation
of a system architecture reduces cache misses and improves performance over the
use of conventional caches.
- lang: ger
text: Traditionelle Cachedesigns verwenden konsolidierte Blöcke von Speicheradressbits
um einen Cachesatz zu indizieren, vergleichbar mit der Anwendung einer Modulofunktion.
Obwohl dieses modulobasierte Abbildungsschema in heutigen Cachestrukturen weit
verbreitet ist, vor allem wegen seiner einfachen Anforderungen an das Hardwaredesign
und seiner Effizienz für die Indizierung eufeinanderfolgender Speicheradressen,
kann seine Verwendung für eine Vielzahl von Anwendungsdomänen mit unterschiedlichen
Charakteristiken zu suboptimalen Ergebnissen führen. Diese Dissertation präsentiert
einen neuen Typ von Cacheabbildungsschema, motiviert durch die Kombination programmierbarer
Ressourcen mit der naturinspirierten Optimierung rekonfigurierbarer Hardware.
Im Fokus dieser Forschung steht eine FPGA-basierte Cachestruktur für den first
level Cache einer Mehrkernprozessorarchitektur, welche die Cacheindizierung dynamisch
ändern kann. Um die Herausforderung rekonfigurierbarer Cacheabbildungen zu lösen,
wird eine reprogrammierbare Boolesche Schaltung eingeführt, die auf Look-up Table
(LUT) Speicherelementen basiert. Weiterhin wird eine Infrastruktur zur Effizienzmessung
eingeführt, welche die zugrundeliege Mikroarchitektur überwachen kann, sowie eine
adaptive Evaluationsstrategie präsentiert, die evolutionäre Algorithmen wirksam
einsetzt, und die nicht nur anwendungsspezifische Abbildungen von Speicheradressen
zu Cacheindizes für level one Caches evolvieren sondern dabei auch die Optimierungszeiten
reduzieren kann. All diese Aspekte zusammen in einer prototypischen Implementierung
auf einem FPGA für einen LEON3/Linux-basierten Mehrkernprozessor zeigen, dass
evolvierbare Cacheabbildungsfunktionen Cache Misses reduzieren, sowie die Effizienz
im Vergleich zu konventionellen Caches erhöhen können.
author:
- first_name: Nam
full_name: Ho, Nam
last_name: Ho
citation:
ama: 'Ho N. FPGA-Based Reconfigurable Cache Mapping Schemes: Design and Optimization.
Universität Paderborn; 2018. doi:10.17619/UNIPB/1-376'
apa: 'Ho, N. (2018). FPGA-based Reconfigurable Cache Mapping Schemes: Design
and Optimization. Universität Paderborn. https://doi.org/10.17619/UNIPB/1-376'
bibtex: '@book{Ho_2018, title={FPGA-based Reconfigurable Cache Mapping Schemes:
Design and Optimization}, DOI={10.17619/UNIPB/1-376},
publisher={Universität Paderborn}, author={Ho, Nam}, year={2018} }'
chicago: 'Ho, Nam. FPGA-Based Reconfigurable Cache Mapping Schemes: Design and
Optimization. Universität Paderborn, 2018. https://doi.org/10.17619/UNIPB/1-376.'
ieee: 'N. Ho, FPGA-based Reconfigurable Cache Mapping Schemes: Design and Optimization.
Universität Paderborn, 2018.'
mla: 'Ho, Nam. FPGA-Based Reconfigurable Cache Mapping Schemes: Design and Optimization.
Universität Paderborn, 2018, doi:10.17619/UNIPB/1-376.'
short: 'N. Ho, FPGA-Based Reconfigurable Cache Mapping Schemes: Design and Optimization,
Universität Paderborn, 2018.'
date_created: 2018-07-27T06:41:13Z
date_updated: 2022-01-06T06:59:31Z
department:
- _id: '78'
doi: 10.17619/UNIPB/1-376
language:
- iso: eng
page: '139'
project:
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
publication_status: published
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: 'FPGA-based Reconfigurable Cache Mapping Schemes: Design and Optimization'
type: dissertation
user_id: '477'
year: '2018'
...
---
_id: '3580'
author:
- first_name: Tim
full_name: Hansmeier, Tim
id: '49992'
last_name: Hansmeier
orcid: 0000-0003-1377-3339
citation:
ama: Hansmeier T. An FPGA Accelerator for Checking Resolution Proofs. Universität
Paderborn; 2017.
apa: Hansmeier, T. (2017). An FPGA Accelerator for Checking Resolution Proofs.
Universität Paderborn.
bibtex: '@book{Hansmeier_2017, title={An FPGA Accelerator for Checking Resolution
Proofs}, publisher={Universität Paderborn}, author={Hansmeier, Tim}, year={2017}
}'
chicago: Hansmeier, Tim. An FPGA Accelerator for Checking Resolution Proofs.
Universität Paderborn, 2017.
ieee: T. Hansmeier, An FPGA Accelerator for Checking Resolution Proofs. Universität
Paderborn, 2017.
mla: Hansmeier, Tim. An FPGA Accelerator for Checking Resolution Proofs.
Universität Paderborn, 2017.
short: T. Hansmeier, An FPGA Accelerator for Checking Resolution Proofs, Universität
Paderborn, 2017.
date_created: 2018-07-20T13:44:34Z
date_updated: 2022-01-06T06:59:25Z
department:
- _id: '78'
- _id: '34'
- _id: '7'
language:
- iso: eng
project:
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
- _id: '12'
name: SFB 901 - Subproject B4
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: An FPGA Accelerator for Checking Resolution Proofs
type: bachelorsthesis
user_id: '3118'
year: '2017'
...
---
_id: '1157'
author:
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
citation:
ama: Witschen LM. A Framework for the Synthesis of Approximate Circuits.
Universität Paderborn; 2017.
apa: Witschen, L. M. (2017). A Framework for the Synthesis of Approximate Circuits.
Universität Paderborn.
bibtex: '@book{Witschen_2017, title={A Framework for the Synthesis of Approximate
Circuits}, publisher={Universität Paderborn}, author={Witschen, Linus Matthias},
year={2017} }'
chicago: Witschen, Linus Matthias. A Framework for the Synthesis of Approximate
Circuits. Universität Paderborn, 2017.
ieee: L. M. Witschen, A Framework for the Synthesis of Approximate Circuits.
Universität Paderborn, 2017.
mla: Witschen, Linus Matthias. A Framework for the Synthesis of Approximate Circuits.
Universität Paderborn, 2017.
short: L.M. Witschen, A Framework for the Synthesis of Approximate Circuits, Universität
Paderborn, 2017.
date_created: 2018-02-01T14:21:19Z
date_updated: 2022-01-06T06:51:03Z
department:
- _id: '78'
- _id: '7'
language:
- iso: eng
project:
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
title: A Framework for the Synthesis of Approximate Circuits
type: mastersthesis
user_id: '477'
year: '2017'
...
---
_id: '74'
author:
- first_name: Christoph
full_name: Knorr, Christoph
last_name: Knorr
citation:
ama: Knorr C. OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten.
Universität Paderborn; 2017.
apa: Knorr, C. (2017). OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten.
Universität Paderborn.
bibtex: '@book{Knorr_2017, title={OpenCL-basierte Videoverarbeitung auf heterogenen
Rechenknoten}, publisher={Universität Paderborn}, author={Knorr, Christoph}, year={2017}
}'
chicago: Knorr, Christoph. OpenCL-basierte Videoverarbeitung auf heterogenen
Rechenknoten. Universität Paderborn, 2017.
ieee: C. Knorr, OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten.
Universität Paderborn, 2017.
mla: Knorr, Christoph. OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten.
Universität Paderborn, 2017.
short: C. Knorr, OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten,
Universität Paderborn, 2017.
date_created: 2017-10-17T12:41:05Z
date_updated: 2022-01-06T07:03:36Z
department:
- _id: '78'
language:
- iso: ger
project:
- _id: '1'
name: SFB 901
- _id: '14'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Achim
full_name: Lösch, Achim
id: '43646'
last_name: Lösch
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten
type: mastersthesis
user_id: '477'
year: '2017'
...
---
_id: '3364'
author:
- first_name: Christoph
full_name: Knorr, Christoph
last_name: Knorr
citation:
ama: Knorr C. Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten.
Universität Paderborn; 2015.
apa: Knorr, C. (2015). Evaluation von Bildverarbeitungsalgorithmen in heterogenen
Rechenknoten. Universität Paderborn.
bibtex: '@book{Knorr_2015, title={Evaluation von Bildverarbeitungsalgorithmen in
heterogenen Rechenknoten}, publisher={Universität Paderborn}, author={Knorr, Christoph},
year={2015} }'
chicago: Knorr, Christoph. Evaluation von Bildverarbeitungsalgorithmen in heterogenen
Rechenknoten. Universität Paderborn, 2015.
ieee: C. Knorr, Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten.
Universität Paderborn, 2015.
mla: Knorr, Christoph. Evaluation von Bildverarbeitungsalgorithmen in heterogenen
Rechenknoten. Universität Paderborn, 2015.
short: C. Knorr, Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten,
Universität Paderborn, 2015.
date_created: 2018-06-26T14:06:07Z
date_updated: 2022-01-06T06:59:13Z
department:
- _id: '78'
language:
- iso: ger
project:
- _id: '14'
name: SFB 901 - Subproject C2
- _id: '1'
name: SFB 901
- _id: '4'
name: SFB 901 - Project Area C
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Achim
full_name: Lösch, Achim
id: '43646'
last_name: Lösch
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten
type: bachelorsthesis
user_id: '477'
year: '2015'
...
---
_id: '10701'
author:
- first_name: Benjamin
full_name: Koch, Benjamin
last_name: Koch
citation:
ama: Koch B. Hardware Acceleration of Mechatronic Controllers on a Zynq Platform
FPGA. Paderborn University; 2014.
apa: Koch, B. (2014). Hardware Acceleration of Mechatronic Controllers on a Zynq
Platform FPGA. Paderborn University.
bibtex: '@book{Koch_2014, title={Hardware Acceleration of Mechatronic Controllers
on a Zynq Platform FPGA}, publisher={Paderborn University}, author={Koch, Benjamin},
year={2014} }'
chicago: Koch, Benjamin. Hardware Acceleration of Mechatronic Controllers on
a Zynq Platform FPGA. Paderborn University, 2014.
ieee: B. Koch, Hardware Acceleration of Mechatronic Controllers on a Zynq Platform
FPGA. Paderborn University, 2014.
mla: Koch, Benjamin. Hardware Acceleration of Mechatronic Controllers on a Zynq
Platform FPGA. Paderborn University, 2014.
short: B. Koch, Hardware Acceleration of Mechatronic Controllers on a Zynq Platform
FPGA, Paderborn University, 2014.
date_created: 2019-07-10T11:38:27Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA
type: mastersthesis
user_id: '3118'
year: '2014'
...
---
_id: '10733'
abstract:
- lang: eng
text: "Monte-Carlo Tree Search (MCTS) is a class of simulation-based search algorithms.
It brought about great success in the past few years regarding the evaluation
of deterministic two-player games such as the Asian board game Go.\r\n\r\nIn this
thesis, we present a parallelization of the most popular MCTS variant for large
HPC compute clusters that efficiently shares a single game tree representation
in a distributed memory environment and scales up to 128 compute nodes and 2048
cores. It is hereby one of the most powerful MCTS parallelizations to date.\r\n\r\nIn
order to measure the impact of our parallelization on the search quality and remain
comparable to the most advanced MCTS implementations to date, we implemented it
in a state-of-the-art Go engine Gomorra, making it competitive with the strongest
Go programs in the world.\r\n\r\nWe further present an empirical comparison of
different Bayesian ranking systems when being used for predicting expert moves
for the game of Go and introduce a novel technique for automated detection and
analysis of evaluation uncertainties that show up during MCTS searches."
author:
- first_name: Lars
full_name: Schäfers, Lars
last_name: Schäfers
citation:
ama: 'Schäfers L. Parallel Monte-Carlo Tree Search for HPC Systems and Its Application
to Computer Go. Berlin: Logos Verlag Berlin GmbH; 2014.'
apa: 'Schäfers, L. (2014). Parallel Monte-Carlo Tree Search for HPC Systems and
its Application to Computer Go. Berlin: Logos Verlag Berlin GmbH.'
bibtex: '@book{Schäfers_2014, place={Berlin}, title={Parallel Monte-Carlo Tree Search
for HPC Systems and its Application to Computer Go}, publisher={Logos Verlag Berlin
GmbH}, author={Schäfers, Lars}, year={2014} }'
chicago: 'Schäfers, Lars. Parallel Monte-Carlo Tree Search for HPC Systems and
Its Application to Computer Go. Berlin: Logos Verlag Berlin GmbH, 2014.'
ieee: 'L. Schäfers, Parallel Monte-Carlo Tree Search for HPC Systems and its
Application to Computer Go. Berlin: Logos Verlag Berlin GmbH, 2014.'
mla: Schäfers, Lars. Parallel Monte-Carlo Tree Search for HPC Systems and Its
Application to Computer Go. Logos Verlag Berlin GmbH, 2014.
short: L. Schäfers, Parallel Monte-Carlo Tree Search for HPC Systems and Its Application
to Computer Go, Logos Verlag Berlin GmbH, Berlin, 2014.
date_created: 2019-07-10T11:58:06Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
page: '133'
place: Berlin
publication_identifier:
isbn:
- 978-3-8325-3748-7
publication_status: published
publisher: Logos Verlag Berlin GmbH
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Parallel Monte-Carlo Tree Search for HPC Systems and its Application to Computer
Go
type: dissertation
user_id: '3118'
year: '2014'
...
---
_id: '10744'
author:
- first_name: Sebastian
full_name: Surmund, Sebastian
last_name: Surmund
citation:
ama: Surmund S. Multithreaded Parallelization of Mechatronic Controllers on a
Zynq Platform FPGA. Paderborn University; 2014.
apa: Surmund, S. (2014). Multithreaded Parallelization of Mechatronic Controllers
on a Zynq Platform FPGA. Paderborn University.
bibtex: '@book{Surmund_2014, title={Multithreaded Parallelization of Mechatronic
Controllers on a Zynq Platform FPGA}, publisher={Paderborn University}, author={Surmund,
Sebastian}, year={2014} }'
chicago: Surmund, Sebastian. Multithreaded Parallelization of Mechatronic Controllers
on a Zynq Platform FPGA. Paderborn University, 2014.
ieee: S. Surmund, Multithreaded Parallelization of Mechatronic Controllers on
a Zynq Platform FPGA. Paderborn University, 2014.
mla: Surmund, Sebastian. Multithreaded Parallelization of Mechatronic Controllers
on a Zynq Platform FPGA. Paderborn University, 2014.
short: S. Surmund, Multithreaded Parallelization of Mechatronic Controllers on a
Zynq Platform FPGA, Paderborn University, 2014.
date_created: 2019-07-10T12:00:45Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform
FPGA
type: mastersthesis
user_id: '3118'
year: '2014'
...
---
_id: '11619'
abstract:
- lang: eng
text: "Reconfigurable circuit devices have opened up a fundamentally new way of
creating adaptable systems. Combined with artificial evolution, reconfigurable
circuits allow an elegant adaptation approach to compensating for changes in the
distribution of input data, computational resource errors, and variations in resource
requirements. Referred to as ``Evolvable Hardware'' (EHW), this paradigm has yielded
astonishing results for traditional engineering challenges and has discovered
intriguing design principles, which have not yet been seen in conventional engineering.\r\n\r\nIn
this thesis, we present new and fundamental work on Evolvable Hardware motivated
by the insight that Evolvable Hardware needs to compensate for events with different
change rates. To solve the challenge of different adaptation speeds, we propose
a unified adaptation approach based on multi-objective evolution, evolving and
propagating candidate solutions that are diverse in objectives that may experience
radical changes.\r\n\r\nFocusing on algorithmic aspects, we enable Cartesian Genetic
Programming (CGP) model, which we are using to encode Boolean circuits, for multi-objective
optimization by introducing a meaningful recombination operator. We improve the
scalability of CGP by objectives scaling, periodization of local- and global-search
algorithms, and the automatic acquisition and reuse of subfunctions using age-
and cone-based techniques. We validate our methods on the applications of adaptation
of hardware classifiers to resource changes, recognition of muscular signals for
prosthesis control and optimization of processor caches."
author:
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
citation:
ama: 'Kaufmann P. Adapting Hardware Systems by Means of Multi-Objective Evolution.
Berlin: Logos Verlag Berlin GmbH; 2013.'
apa: 'Kaufmann, P. (2013). Adapting Hardware Systems by Means of Multi-Objective
Evolution. Berlin: Logos Verlag Berlin GmbH.'
bibtex: '@book{Kaufmann_2013, place={Berlin}, title={Adapting Hardware Systems by
Means of Multi-Objective Evolution}, publisher={Logos Verlag Berlin GmbH}, author={Kaufmann,
Paul}, year={2013} }'
chicago: 'Kaufmann, Paul. Adapting Hardware Systems by Means of Multi-Objective
Evolution. Berlin: Logos Verlag Berlin GmbH, 2013.'
ieee: 'P. Kaufmann, Adapting Hardware Systems by Means of Multi-Objective Evolution.
Berlin: Logos Verlag Berlin GmbH, 2013.'
mla: Kaufmann, Paul. Adapting Hardware Systems by Means of Multi-Objective Evolution.
Logos Verlag Berlin GmbH, 2013.
short: P. Kaufmann, Adapting Hardware Systems by Means of Multi-Objective Evolution,
Logos Verlag Berlin GmbH, Berlin, 2013.
date_created: 2019-07-11T11:51:51Z
date_updated: 2022-01-06T06:51:04Z
department:
- _id: '78'
language:
- iso: eng
page: '249'
place: Berlin
publication_identifier:
isbn:
- 978-3-8325-3530-8
publication_status: published
publisher: Logos Verlag Berlin GmbH
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Adapting Hardware Systems by Means of Multi-Objective Evolution
type: dissertation
user_id: '3118'
year: '2013'
...
---
_id: '501'
abstract:
- lang: eng
text: 'Handling run-time dynamics on embedded system-on-chip architectures has become
more challenging over the years. On the one hand, the impact of workload and physical
dynamics on the system behavior has dramatically increased. On the other hand,
embedded architectures have become more complex as they have evolved from single-processor
systems over multi-processor systems to hybrid multi-core platforms.Static design-time
techniques no longer provide suitable solutions to deal with the run-time dynamics
of today''s embedded systems. Therefore, system designers have to apply run-time
solutions, which have hardly been investigated for hybrid multi-core platforms.In
this thesis, we present fundamental work in the new area of run-time management
on hybrid multi-core platforms. We propose a novel architecture, a self-adaptive
hybrid multi-core system, that combines heterogeneous processors, reconfigurable
hardware cores, and monitoring cores on a single chip. Using self-adaptation on
thread-level, our hybrid multi-core systems can effectively perform performance
and thermal management autonomously at run-time. '
author:
- first_name: Markus
full_name: Happe, Markus
last_name: Happe
citation:
ama: 'Happe M. Performance and Thermal Management on Self-Adaptive Hybrid Multi-Cores.
Berlin: Logos Verlag Berlin GmbH; 2013.'
apa: 'Happe, M. (2013). Performance and thermal management on self-adaptive hybrid
multi-cores. Berlin: Logos Verlag Berlin GmbH.'
bibtex: '@book{Happe_2013, place={Berlin}, title={Performance and thermal management
on self-adaptive hybrid multi-cores}, publisher={Logos Verlag Berlin GmbH}, author={Happe,
Markus}, year={2013} }'
chicago: 'Happe, Markus. Performance and Thermal Management on Self-Adaptive
Hybrid Multi-Cores. Berlin: Logos Verlag Berlin GmbH, 2013.'
ieee: 'M. Happe, Performance and thermal management on self-adaptive hybrid multi-cores.
Berlin: Logos Verlag Berlin GmbH, 2013.'
mla: Happe, Markus. Performance and Thermal Management on Self-Adaptive Hybrid
Multi-Cores. Logos Verlag Berlin GmbH, 2013.
short: M. Happe, Performance and Thermal Management on Self-Adaptive Hybrid Multi-Cores,
Logos Verlag Berlin GmbH, Berlin, 2013.
date_created: 2017-10-17T12:42:30Z
date_updated: 2022-01-06T07:01:34Z
department:
- _id: '78'
language:
- iso: eng
page: '220'
place: Berlin
project:
- _id: '14'
name: SFB 901 - Subprojekt C2
- _id: '1'
name: SFB 901
- _id: '4'
name: SFB 901 - Project Area C
publication_identifier:
isbn:
- 978-3-8325-3425-7
publication_status: published
publisher: Logos Verlag Berlin GmbH
related_material:
link:
- relation: confirmation
url: https://www.logos-verlag.de/cgi-bin/engbuchmid?isbn=3425&lng=deu&id=
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Performance and thermal management on self-adaptive hybrid multi-cores
type: dissertation
user_id: '477'
year: '2013'
...
---
_id: '586'
abstract:
- lang: eng
text: FPGAs, systems on chip and embedded systems are nowadays irreplaceable. They
combine the computational power of application specific hardware with software-like
flexibility. At runtime, they can adjust their functionality by downloading new
hardware modules and integrating their functionality. Due to their growing capabilities,
the demands made to reconfigurable hardware grow. Their deployment in increasingly
security critical scenarios requires new ways of enforcing security since a failure
in security has severe consequences. Aside from financial losses, a loss of human
life and risks to national security are possible. With this work I present the
novel and groundbreaking concept of proof-carrying hardware. It is a method for
the verification of properties of hardware modules to guarantee security for a
target platform at runtime. The producer of a hardware module delivers based on
the consumer's safety policy a safety proof in combination with the reconfiguration
bitstream. The extensive computation of a proof is a contrast to the comparatively
undemanding checking of the proof. I present a prototype based on open-source
tools and an abstract FPGA architecture and bitstream format. The proof of the
usability of proof-carrying hardware provides the evaluation of the prototype
with the exemplary application of securing combinational and bounded sequential
equivalence of reference monitor modules for memory safety.
- lang: ger
text: FPGAs, System on Chips und eingebettete Systeme sind heutzutage kaum mehr
wegzudenken. Sie kombinieren die Rechenleistung von spezialisierter Hardware mit
einer Software-ähnlichen Flexibilität. Zur Laufzeit können sie ihre Funktionalität
anpassen, indem sie online neue Hardware Module beziehen und deren Funktionalität
integrieren. Mit der Leistung wachsen auch die Anforderungen an rekonfigurierbare
Hardware. Ihr Einsatz in immer sicherheitskritischeren Szenarien erfordert neue
Wege um Sicherheit zu gewährleisten, da ein Versagen der Sicherheit gravierende
Folgen mit sich bringt. Neben finanziellen Verlusten sind auch der Verlust von
Menschenleben oder Einbußen in der nationalen Sicherheit denkbar. In dieser Arbeit
stelle ich das neue und wegweisende Konzept der beweistragenden Hardware vor.
Es ist eine Methode zur Verifizierung von Eigenschaften von Hardware Modulen um
die Sicherheit der Zielplatformen zur Laufzeit zu garantieren. Der Produzent eines
Hardware Moduls liefert, basierend auf den Sicherheitsbestimmungen des Konsumenten,
einen Beweis der Sicherheit mit dem Rekonfigurierungsbitstrom. Die aufwendige
Berechnung des Beweises steht im Kontrast zu der vergleichsweise unaufwendigen
Überprüfung durch den Konsumenten. Ich präsentiere einen Prototypen basierend
auf Open Source Werkzeugen und einer eigenen abstrakten FPGA Architektur samt
Bitstromformat. Den Nachweis über die Nutzbarkeit von beweistragender Hardware
erbringt die Evaluierung des Prototypen zur beispielhaften Anwendung der Sicherung
von kombinatorischer und begrenzt sequenzieller Äquivalenz von Referenzmonitor-Modulen
zur Speichersicherheit.
author:
- first_name: Stephanie
full_name: Drzevitzky, Stephanie
last_name: Drzevitzky
citation:
ama: 'Drzevitzky S. Proof-Carrying Hardware: A Novel Approach to Reconfigurable
Hardware Security. Universität Paderborn; 2012.'
apa: 'Drzevitzky, S. (2012). Proof-Carrying Hardware: A Novel Approach to Reconfigurable
Hardware Security. Universität Paderborn.'
bibtex: '@book{Drzevitzky_2012, title={Proof-Carrying Hardware: A Novel Approach
to Reconfigurable Hardware Security}, publisher={Universität Paderborn}, author={Drzevitzky,
Stephanie}, year={2012} }'
chicago: 'Drzevitzky, Stephanie. Proof-Carrying Hardware: A Novel Approach to
Reconfigurable Hardware Security. Universität Paderborn, 2012.'
ieee: 'S. Drzevitzky, Proof-Carrying Hardware: A Novel Approach to Reconfigurable
Hardware Security. Universität Paderborn, 2012.'
mla: 'Drzevitzky, Stephanie. Proof-Carrying Hardware: A Novel Approach to Reconfigurable
Hardware Security. Universität Paderborn, 2012.'
short: 'S. Drzevitzky, Proof-Carrying Hardware: A Novel Approach to Reconfigurable
Hardware Security, Universität Paderborn, 2012.'
date_created: 2017-10-17T12:42:46Z
date_updated: 2022-01-06T07:02:44Z
ddc:
- '040'
department:
- _id: '78'
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-15T08:38:19Z
date_updated: 2018-03-15T08:38:19Z
file_id: '1261'
file_name: 586-Drzevitzky-PhD_01.pdf
file_size: 1438436
relation: main_file
success: 1
file_date_updated: 2018-03-15T08:38:19Z
has_accepted_license: '1'
language:
- iso: eng
main_file_link:
- open_access: '1'
url: https://nbn-resolving.de/urn:nbn:de:hbz:466:2-10423
oa: '1'
page: '114'
project:
- _id: '12'
name: SFB 901 - Subprojekt B4
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
publication_status: published
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: 'Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security'
type: dissertation
user_id: '477'
year: '2012'
...
---
_id: '10652'
abstract:
- lang: eng
text: "The paradigm shift towards many-core parallelism is accompanied by two fundamental
questions: how should the many processors on a single die communicate to each
other and what are suitable programming models for these novel architectures?
In this thesis, the author tackles both questions by reviewing the reconfigurable
mesh model of massively parallel computation for many-cores.\r\n\r\nThe book presents
the design, implementation and evaluation of a many-core architecture that is
based on the execution principles and communication infrastructure of the reconfigurable
mesh. This work fundamentally rests on FPGA implementations and shows that reconfigurable
mesh processors with hundreds of autonomous cores are feasible. Several case studies
demonstrate the effectiveness of programming and illustrate why the reconfigurable
mesh is a promising model for many-cores."
author:
- first_name: Heiner
full_name: Giefers, Heiner
last_name: Giefers
citation:
ama: 'Giefers H. Design and Programming of Reconfigurable Mesh Based Many-Cores.
Berlin: Logos Verlag Berlin GmbH; 2012.'
apa: 'Giefers, H. (2012). Design and Programming of Reconfigurable Mesh based
Many-Cores. Berlin: Logos Verlag Berlin GmbH.'
bibtex: '@book{Giefers_2012, place={Berlin}, title={Design and Programming of Reconfigurable
Mesh based Many-Cores}, publisher={Logos Verlag Berlin GmbH}, author={Giefers,
Heiner}, year={2012} }'
chicago: 'Giefers, Heiner. Design and Programming of Reconfigurable Mesh Based
Many-Cores. Berlin: Logos Verlag Berlin GmbH, 2012.'
ieee: 'H. Giefers, Design and Programming of Reconfigurable Mesh based Many-Cores.
Berlin: Logos Verlag Berlin GmbH, 2012.'
mla: Giefers, Heiner. Design and Programming of Reconfigurable Mesh Based Many-Cores.
Logos Verlag Berlin GmbH, 2012.
short: H. Giefers, Design and Programming of Reconfigurable Mesh Based Many-Cores,
Logos Verlag Berlin GmbH, Berlin, 2012.
date_created: 2019-07-10T11:13:12Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
page: '159'
place: Berlin
publication_identifier:
isbn:
- 978-3-8325-3165-2
publication_status: published
publisher: Logos Verlag Berlin GmbH
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Design and Programming of Reconfigurable Mesh based Many-Cores
type: dissertation
user_id: '3118'
year: '2012'
...