---
_id: '59232'
abstract:
- lang: eng
  text: Heterogeneous computing devices comprising multiple processing systems combined
    with a programmable logic like an FPGA have become increasingly popular. Developing
    and runtime managing these heterogeneous platform devices, however, still poses
    multiple challenges. The programming paradigms for hardware and software applications
    fundamentally differ, while the runtime management requires additional attention.
    The first steps towards unifying design flows have been taken by creating high-level
    synthesis tools. However, these toolsfocus on the design process and lack runtime
    management features. FPGA operating systems aim to close this gap by providing
    runtime management features and build tools. ReconOS, as an example of an FPGA
    operating system, allows bridging the hardware-software gap by integrating hardware-located
    computation units as threads into a host operating system, allowing for familiar
    inter-thread programming paradigms to be extended to FPGAs. This thesis presents
    ReconOS64, a successor and fork of ReconOS, aiming at modern 64-bit platform systems-on-chip.
    Besides establishing support for this platform and incorporating new system generation
    processes, ReconOS64 provides additional features for both development and runtime
    management. By providing a flexible grouping mechanism for hardware-located threads,
    partial reconfiguration for exchanging individual threads at runtime is simplified.
    Further runtime flexibility was achieved by implementing a multi-clock architecture,
    allowing individual groups of threads to be executed at different frequencies,
    which can be adapted during runtime with a low reconfiguration overhead. In addition,
    this thesis provides an overview of further development approaches on various
    systems based on ReconOS64 and ReconOS.
- lang: ger
  text: Heterogene Architekturen, welche aus mehreren Recheneinheiten im Verbund mit
    einer programmierbaren Logik bestehen, gewinnen zunehmend an Verbreitung. Die
    Entwicklungsprozesse sowie die Steuerung solcher heterogenen Umgebungen stellen
    jedoch nach wie vor eine Herausforderung dar. Die Programmiertechniken für Hardware-
    und Software-Anwendungen unterscheiden sich bereits grundlegend; zudem benötigt
    die Steuerung zusätzliche Aufmerksamkeit. Die Verwendung von Hochsprachen-Synthesewerkzeugen
    (High-Level Synthesis) für das Hardwaredesign stellen einen ersten Schritt hin
    zu einem einheitlichen Entwurfsprozess dar. Allerdings beschränkt sich deren Einsatz
    auf den Designprozess, während das Management zur Laufzeit keine Berücksichtigung
    findet.FPGA-Betriebssysteme versuchen diese Lücke durch die Bereitstellung von
    Management- und Entwurfswerkzeugen zu schließen. Ein Beispiel für ein solches
    System ist ReconOS, welches die Hardware-Software-Interaktion durch Anbindung
    von hardwareseitigen Recheneinheiten als Threads in einem Host-Betriebssystem
    ermöglicht. Dadurch werden die aus der Softwareentwicklung bekannten Methoden
    zur Kommunikation zwischen mehreren Threads auf FPGA-Systeme ausgeweitet.Diese
    Arbeit stellt ReconOS64 vor, welches als Ableger von ReconOS auf aktuellen 64-bit
    Systemen verwendet werden kann. Neben der Unterstützung aktueller Plattformen
    sowie der Einrichtung eines neuen Designprozesses werden durch ReconOS64 zusätzliche
    Möglichkeiten sowohl zur Entwicklung wie auch zum Laufzeitmanagement geschaffen.
    Durch flexible Gruppierungen von Hardware-basierten Threads wird die Verwendung
    partieller Rekonfiguration zum Austausch einzelner Threads zur Laufzeit vereinfacht.
    Zudem erhöht die Entwicklung einer Multi-Taktsignal-Architektur die Flexibilität
    zur Laufzeit, da hierdurch einzelne Gruppen von Threads mit unterschiedlichen
    Taktsignalen versorgt werden können, welche zudem zurLaufzeit mit geringer Unterbrechungszeit
    verändert werden können.Zusätzlich werden im Rahmen dieser Arbeit weitere Entwicklungsprojekte
    auf verschiedenen Systemen für ReconOS64 und ReconOS vorgestellt.
author:
- first_name: Lennart
  full_name: Clausing, Lennart
  id: '74287'
  last_name: Clausing
  orcid: 0000-0003-3789-6034
citation:
  ama: Clausing L. <i>ReconOS64 - Hardware-Software Multithreading for Heterogeneous
    Platform FPGAs</i>.; 2025. doi:<a href="https://doi.org/10.17619/UNIPB/1-2216">10.17619/UNIPB/1-2216</a>
  apa: Clausing, L. (2025). <i>ReconOS64 - Hardware-Software Multithreading for Heterogeneous
    Platform FPGAs</i>. <a href="https://doi.org/10.17619/UNIPB/1-2216">https://doi.org/10.17619/UNIPB/1-2216</a>
  bibtex: '@book{Clausing_2025, place={Paderborn}, title={ReconOS64 - Hardware-Software
    Multithreading for Heterogeneous Platform FPGAs}, DOI={<a href="https://doi.org/10.17619/UNIPB/1-2216">10.17619/UNIPB/1-2216</a>},
    author={Clausing, Lennart}, year={2025} }'
  chicago: Clausing, Lennart. <i>ReconOS64 - Hardware-Software Multithreading for
    Heterogeneous Platform FPGAs</i>. Paderborn, 2025. <a href="https://doi.org/10.17619/UNIPB/1-2216">https://doi.org/10.17619/UNIPB/1-2216</a>.
  ieee: L. Clausing, <i>ReconOS64 - Hardware-Software Multithreading for Heterogeneous
    Platform FPGAs</i>. Paderborn, 2025.
  mla: Clausing, Lennart. <i>ReconOS64 - Hardware-Software Multithreading for Heterogeneous
    Platform FPGAs</i>. 2025, doi:<a href="https://doi.org/10.17619/UNIPB/1-2216">10.17619/UNIPB/1-2216</a>.
  short: L. Clausing, ReconOS64 - Hardware-Software Multithreading for Heterogeneous
    Platform FPGAs, Paderborn, 2025.
date_created: 2025-04-01T17:00:31Z
date_updated: 2025-04-01T17:24:18Z
doi: 10.17619/UNIPB/1-2216
language:
- iso: eng
main_file_link:
- open_access: '1'
  url: https://nbn-resolving.org/urn:nbn:de:hbz:466:2-54271
oa: '1'
place: Paderborn
publication_status: published
status: public
supervisor:
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
title: ReconOS64 - Hardware-Software Multithreading for Heterogeneous Platform FPGAs
type: dissertation
user_id: '74287'
year: '2025'
...
---
_id: '62268'
author:
- first_name: Prajwal
  full_name: Bengaluru Amarnath, Prajwal
  last_name: Bengaluru Amarnath
citation:
  ama: Bengaluru Amarnath P. <i>Design and Integration of Intra-Process Communication
    for ROS 2 into ReconROS</i>. Paderborn University; 2025.
  apa: Bengaluru Amarnath, P. (2025). <i>Design and Integration of Intra-Process Communication
    for ROS 2 into ReconROS</i>. Paderborn University.
  bibtex: '@book{Bengaluru Amarnath_2025, title={Design and Integration of Intra-Process
    Communication for ROS 2 into ReconROS}, publisher={Paderborn University}, author={Bengaluru
    Amarnath, Prajwal}, year={2025} }'
  chicago: Bengaluru Amarnath, Prajwal. <i>Design and Integration of Intra-Process
    Communication for ROS 2 into ReconROS</i>. Paderborn University, 2025.
  ieee: P. Bengaluru Amarnath, <i>Design and Integration of Intra-Process Communication
    for ROS 2 into ReconROS</i>. Paderborn University, 2025.
  mla: Bengaluru Amarnath, Prajwal. <i>Design and Integration of Intra-Process Communication
    for ROS 2 into ReconROS</i>. Paderborn University, 2025.
  short: P. Bengaluru Amarnath, Design and Integration of Intra-Process Communication
    for ROS 2 into ReconROS, Paderborn University, 2025.
date_created: 2025-11-20T10:15:20Z
date_updated: 2025-11-20T10:17:09Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Alexander Philipp
  full_name: Nowosad, Alexander Philipp
  id: '68801'
  last_name: Nowosad
  orcid: 0009-0009-3783-3843
title: Design and Integration of Intra-Process Communication for ROS 2 into ReconROS
type: mastersthesis
user_id: '68801'
year: '2025'
...
---
_id: '54245'
author:
- first_name: Luca-Sebastian
  full_name: Henke, Luca-Sebastian
  last_name: Henke
citation:
  ama: Henke L-S. <i>Exploring Custom FPGA Accelerators for DNN-Based RF Fingerprinting</i>.;
    2024.
  apa: Henke, L.-S. (2024). <i>Exploring Custom FPGA Accelerators for DNN-based RF
    Fingerprinting</i>.
  bibtex: '@book{Henke_2024, title={Exploring Custom FPGA Accelerators for DNN-based
    RF Fingerprinting}, author={Henke, Luca-Sebastian}, year={2024} }'
  chicago: Henke, Luca-Sebastian. <i>Exploring Custom FPGA Accelerators for DNN-Based
    RF Fingerprinting</i>, 2024.
  ieee: L.-S. Henke, <i>Exploring Custom FPGA Accelerators for DNN-based RF Fingerprinting</i>.
    2024.
  mla: Henke, Luca-Sebastian. <i>Exploring Custom FPGA Accelerators for DNN-Based
    RF Fingerprinting</i>. 2024.
  short: L.-S. Henke, Exploring Custom FPGA Accelerators for DNN-Based RF Fingerprinting,
    2024.
date_created: 2024-05-13T14:00:01Z
date_updated: 2024-05-13T14:01:23Z
department:
- _id: '78'
language:
- iso: eng
status: public
supervisor:
- first_name: Felix
  full_name: Jentzsch, Felix
  id: '55631'
  last_name: Jentzsch
  orcid: 0000-0003-4987-5708
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
title: Exploring Custom FPGA Accelerators for DNN-based RF Fingerprinting
type: mastersthesis
user_id: '55631'
year: '2024'
...
---
_id: '59621'
author:
- first_name: Tobias
  full_name: Erhart, Tobias
  last_name: Erhart
citation:
  ama: Erhart T. <i>Efficient Automatic Speech Recognition on FPGAs for Datacenters</i>.;
    2024.
  apa: Erhart, T. (2024). <i>Efficient Automatic Speech Recognition on FPGAs for Datacenters</i>.
  bibtex: '@book{Erhart_2024, title={Efficient Automatic Speech Recognition on FPGAs
    for Datacenters}, author={Erhart, Tobias}, year={2024} }'
  chicago: Erhart, Tobias. <i>Efficient Automatic Speech Recognition on FPGAs for
    Datacenters</i>, 2024.
  ieee: T. Erhart, <i>Efficient Automatic Speech Recognition on FPGAs for Datacenters</i>.
    2024.
  mla: Erhart, Tobias. <i>Efficient Automatic Speech Recognition on FPGAs for Datacenters</i>.
    2024.
  short: T. Erhart, Efficient Automatic Speech Recognition on FPGAs for Datacenters,
    2024.
date_created: 2025-04-22T07:37:25Z
date_updated: 2025-04-22T07:37:44Z
extern: '1'
language:
- iso: eng
status: public
supervisor:
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Christoph
  full_name: Berganski, Christoph
  id: '98854'
  last_name: Berganski
title: Efficient Automatic Speech Recognition on FPGAs for Datacenters
type: bachelorsthesis
user_id: '98854'
year: '2024'
...
---
_id: '58132'
author:
- first_name: Maximilian
  full_name: Hartinger, Maximilian
  last_name: Hartinger
citation:
  ama: Hartinger M. <i>Controlling I/O Devices from Hardware-Mapped ReconROS Nodes</i>.
    Paderborn University; 2024.
  apa: Hartinger, M. (2024). <i>Controlling I/O Devices from Hardware-Mapped ReconROS
    Nodes</i>. Paderborn University.
  bibtex: '@book{Hartinger_2024, title={Controlling I/O Devices from Hardware-Mapped
    ReconROS Nodes}, publisher={Paderborn University}, author={Hartinger, Maximilian},
    year={2024} }'
  chicago: Hartinger, Maximilian. <i>Controlling I/O Devices from Hardware-Mapped
    ReconROS Nodes</i>. Paderborn University, 2024.
  ieee: M. Hartinger, <i>Controlling I/O Devices from Hardware-Mapped ReconROS Nodes</i>.
    Paderborn University, 2024.
  mla: Hartinger, Maximilian. <i>Controlling I/O Devices from Hardware-Mapped ReconROS
    Nodes</i>. Paderborn University, 2024.
  short: M. Hartinger, Controlling I/O Devices from Hardware-Mapped ReconROS Nodes,
    Paderborn University, 2024.
date_created: 2025-01-09T15:29:16Z
date_updated: 2025-01-09T15:32:54Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Alexander Philipp
  full_name: Nowosad, Alexander Philipp
  id: '68801'
  last_name: Nowosad
  orcid: 0009-0009-3783-3843
title: Controlling I/O Devices from Hardware-Mapped ReconROS Nodes
type: bachelorsthesis
user_id: '68801'
year: '2024'
...
---
_id: '47837'
author:
- first_name: Tim
  full_name: Hansmeier, Tim
  last_name: Hansmeier
citation:
  ama: Hansmeier T. <i>XCS for Self-Awareness in Autonomous Computing Systems</i>.;
    2023.
  apa: Hansmeier, T. (2023). <i>XCS for Self-awareness in Autonomous Computing Systems</i>.
  bibtex: '@book{Hansmeier_2023, title={XCS for Self-awareness in Autonomous Computing
    Systems}, author={Hansmeier, Tim}, year={2023} }'
  chicago: Hansmeier, Tim. <i>XCS for Self-Awareness in Autonomous Computing Systems</i>,
    2023.
  ieee: T. Hansmeier, <i>XCS for Self-awareness in Autonomous Computing Systems</i>.
    2023.
  mla: Hansmeier, Tim. <i>XCS for Self-Awareness in Autonomous Computing Systems</i>.
    2023.
  short: T. Hansmeier, XCS for Self-Awareness in Autonomous Computing Systems, 2023.
date_created: 2023-10-06T12:45:58Z
date_updated: 2023-10-06T12:46:08Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '1'
  grant_number: '160364472'
  name: 'SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen
    in dynamischen Märkten '
- _id: '4'
  name: 'SFB 901 - C: SFB 901 - Project Area C'
- _id: '14'
  grant_number: '160364472'
  name: 'SFB 901 - C2: SFB 901 - On-The-Fly Compute Centers I: Heterogene Ausführungsumgebungen
    (Subproject C2)'
status: public
supervisor:
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
title: XCS for Self-awareness in Autonomous Computing Systems
type: dissertation
user_id: '15504'
year: '2023'
...
---
_id: '54127'
author:
- first_name: Deepak Bhardwaj
  full_name: Anantha Rao, Deepak Bhardwaj
  last_name: Anantha Rao
citation:
  ama: Anantha Rao DB. <i>Efficient Neural Network Inference for Velocity Estimation
    in Athletic Relay Races on a Microcontroller</i>. Paderborn University; 2023.
  apa: Anantha Rao, D. B. (2023). <i>Efficient Neural Network Inference for Velocity
    Estimation in Athletic Relay Races on a Microcontroller</i>. Paderborn University.
  bibtex: '@book{Anantha Rao_2023, title={Efficient Neural Network Inference for Velocity
    Estimation in Athletic Relay Races on a Microcontroller}, publisher={Paderborn
    University}, author={Anantha Rao, Deepak Bhardwaj}, year={2023} }'
  chicago: Anantha Rao, Deepak Bhardwaj. <i>Efficient Neural Network Inference for
    Velocity Estimation in Athletic Relay Races on a Microcontroller</i>. Paderborn
    University, 2023.
  ieee: D. B. Anantha Rao, <i>Efficient Neural Network Inference for Velocity Estimation
    in Athletic Relay Races on a Microcontroller</i>. Paderborn University, 2023.
  mla: Anantha Rao, Deepak Bhardwaj. <i>Efficient Neural Network Inference for Velocity
    Estimation in Athletic Relay Races on a Microcontroller</i>. Paderborn University,
    2023.
  short: D.B. Anantha Rao, Efficient Neural Network Inference for Velocity Estimation
    in Athletic Relay Races on a Microcontroller, Paderborn University, 2023.
date_created: 2024-05-08T15:40:17Z
date_updated: 2024-05-08T15:51:52Z
department:
- _id: '78'
extern: '1'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Christoph
  full_name: Berganski, Christoph
  id: '98854'
  last_name: Berganski
- first_name: Andre
  full_name: Diekwisch, Andre
  id: '9451'
  last_name: Diekwisch
title: Efficient Neural Network Inference for Velocity Estimation in Athletic Relay
  Races on a Microcontroller
type: mastersthesis
user_id: '98854'
year: '2023'
...
---
_id: '42839'
author:
- first_name: Florian
  full_name: Mehlich, Florian
  last_name: Mehlich
citation:
  ama: Mehlich F. <i>An Evaluation of XCS on the OpenAI Gym</i>. Paderborn University;
    2023.
  apa: Mehlich, F. (2023). <i>An Evaluation of XCS on the OpenAI Gym</i>. Paderborn
    University.
  bibtex: '@book{Mehlich_2023, place={Paderborn}, title={An Evaluation of XCS on the
    OpenAI Gym}, publisher={Paderborn University}, author={Mehlich, Florian}, year={2023}
    }'
  chicago: 'Mehlich, Florian. <i>An Evaluation of XCS on the OpenAI Gym</i>. Paderborn:
    Paderborn University, 2023.'
  ieee: 'F. Mehlich, <i>An Evaluation of XCS on the OpenAI Gym</i>. Paderborn: Paderborn
    University, 2023.'
  mla: Mehlich, Florian. <i>An Evaluation of XCS on the OpenAI Gym</i>. Paderborn
    University, 2023.
  short: F. Mehlich, An Evaluation of XCS on the OpenAI Gym, Paderborn University,
    Paderborn, 2023.
date_created: 2023-03-07T12:22:57Z
date_updated: 2024-05-15T13:14:54Z
department:
- _id: '78'
extern: '1'
language:
- iso: eng
place: Paderborn
project:
- _id: '14'
  grant_number: '160364472'
  name: 'SFB 901 - C2: SFB 901 - Subproject C2'
- _id: '4'
  name: 'SFB 901 - C: SFB 901 - Project Area C'
- _id: '1'
  grant_number: '160364472'
  name: 'SFB 901: SFB 901'
publisher: Paderborn University
status: public
supervisor:
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Tim
  full_name: Hansmeier, Tim
  id: '49992'
  last_name: Hansmeier
  orcid: 0000-0003-1377-3339
title: An Evaluation of XCS on the OpenAI Gym
type: bachelorsthesis
user_id: '398'
year: '2023'
...
---
_id: '45762'
author:
- first_name: Florian
  full_name: Simon-Mertens, Florian
  last_name: Simon-Mertens
citation:
  ama: Simon-Mertens F. <i>Effizienzanalyse leichtgewichtiger Neuronaler Netze für
    FPGA-basierte Modulationsklassifikation</i>. Paderborn University; 2023.
  apa: Simon-Mertens, F. (2023). <i>Effizienzanalyse leichtgewichtiger Neuronaler
    Netze für FPGA-basierte Modulationsklassifikation</i>. Paderborn University.
  bibtex: '@book{Simon-Mertens_2023, title={Effizienzanalyse leichtgewichtiger Neuronaler
    Netze für FPGA-basierte Modulationsklassifikation}, publisher={Paderborn University},
    author={Simon-Mertens, Florian}, year={2023} }'
  chicago: Simon-Mertens, Florian. <i>Effizienzanalyse leichtgewichtiger Neuronaler
    Netze für FPGA-basierte Modulationsklassifikation</i>. Paderborn University, 2023.
  ieee: F. Simon-Mertens, <i>Effizienzanalyse leichtgewichtiger Neuronaler Netze für
    FPGA-basierte Modulationsklassifikation</i>. Paderborn University, 2023.
  mla: Simon-Mertens, Florian. <i>Effizienzanalyse leichtgewichtiger Neuronaler Netze
    für FPGA-basierte Modulationsklassifikation</i>. Paderborn University, 2023.
  short: F. Simon-Mertens, Effizienzanalyse leichtgewichtiger Neuronaler Netze für
    FPGA-basierte Modulationsklassifikation, Paderborn University, 2023.
date_created: 2023-06-23T10:41:54Z
date_updated: 2024-05-15T13:29:13Z
department:
- _id: '78'
language:
- iso: ger
project:
- _id: '52'
  name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing'
publisher: Paderborn University
status: public
supervisor:
- first_name: Felix
  full_name: Jentzsch, Felix
  id: '55631'
  last_name: Jentzsch
  orcid: 0000-0003-4987-5708
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Tobias
  full_name: Kenter, Tobias
  id: '3145'
  last_name: Kenter
title: Effizienzanalyse leichtgewichtiger Neuronaler Netze für FPGA-basierte Modulationsklassifikation
type: bachelorsthesis
user_id: '398'
year: '2023'
...
---
_id: '54243'
author:
- first_name: Marvin Osaretin
  full_name: Oviasogie, Marvin Osaretin
  last_name: Oviasogie
citation:
  ama: Oviasogie MO. <i>Demonstrator for Dataflow-Based DNN Acceleration for Vision
    Applications on Platform FPGAs</i>. Paderborn University; 2023.
  apa: Oviasogie, M. O. (2023). <i>Demonstrator for Dataflow-based DNN Acceleration
    for Vision Applications on Platform FPGAs</i>. Paderborn University.
  bibtex: '@book{Oviasogie_2023, title={Demonstrator for Dataflow-based DNN Acceleration
    for Vision Applications on Platform FPGAs}, publisher={Paderborn University},
    author={Oviasogie, Marvin Osaretin}, year={2023} }'
  chicago: Oviasogie, Marvin Osaretin. <i>Demonstrator for Dataflow-Based DNN Acceleration
    for Vision Applications on Platform FPGAs</i>. Paderborn University, 2023.
  ieee: M. O. Oviasogie, <i>Demonstrator for Dataflow-based DNN Acceleration for Vision
    Applications on Platform FPGAs</i>. Paderborn University, 2023.
  mla: Oviasogie, Marvin Osaretin. <i>Demonstrator for Dataflow-Based DNN Acceleration
    for Vision Applications on Platform FPGAs</i>. Paderborn University, 2023.
  short: M.O. Oviasogie, Demonstrator for Dataflow-Based DNN Acceleration for Vision
    Applications on Platform FPGAs, Paderborn University, 2023.
date_created: 2024-05-13T13:58:31Z
date_updated: 2024-05-15T13:30:41Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Felix
  full_name: Jentzsch, Felix
  id: '55631'
  last_name: Jentzsch
  orcid: 0000-0003-4987-5708
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
title: Demonstrator for Dataflow-based DNN Acceleration for Vision Applications on
  Platform FPGAs
type: bachelorsthesis
user_id: '398'
year: '2023'
...
---
_id: '54241'
author:
- first_name: Lucas David
  full_name: Reuter, Lucas David
  last_name: Reuter
citation:
  ama: Reuter LD. <i>Development of a Power Analysis Framework for Embedded FPGA Accelerators</i>.
    Paderborn University; 2023.
  apa: Reuter, L. D. (2023). <i>Development of a Power Analysis Framework for Embedded
    FPGA Accelerators</i>. Paderborn University.
  bibtex: '@book{Reuter_2023, title={Development of a Power Analysis Framework for
    Embedded FPGA Accelerators}, publisher={Paderborn University}, author={Reuter,
    Lucas David}, year={2023} }'
  chicago: Reuter, Lucas David. <i>Development of a Power Analysis Framework for Embedded
    FPGA Accelerators</i>. Paderborn University, 2023.
  ieee: L. D. Reuter, <i>Development of a Power Analysis Framework for Embedded FPGA
    Accelerators</i>. Paderborn University, 2023.
  mla: Reuter, Lucas David. <i>Development of a Power Analysis Framework for Embedded
    FPGA Accelerators</i>. Paderborn University, 2023.
  short: L.D. Reuter, Development of a Power Analysis Framework for Embedded FPGA
    Accelerators, Paderborn University, 2023.
date_created: 2024-05-13T13:56:45Z
date_updated: 2024-05-15T13:30:54Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Felix
  full_name: Jentzsch, Felix
  id: '55631'
  last_name: Jentzsch
  orcid: 0000-0003-4987-5708
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
title: Development of a Power Analysis Framework for Embedded FPGA Accelerators
type: bachelorsthesis
user_id: '398'
year: '2023'
...
---
_id: '54246'
author:
- first_name: Robin
  full_name: Hamm, Robin
  last_name: Hamm
citation:
  ama: Hamm R. <i>Verarbeitung von Sensordaten auf eingebetteten heterogenen FPGA-Systemen</i>.
    Paderborn University; 2023.
  apa: Hamm, R. (2023). <i>Verarbeitung von Sensordaten auf eingebetteten heterogenen
    FPGA-Systemen</i>. Paderborn University.
  bibtex: '@book{Hamm_2023, title={Verarbeitung von Sensordaten auf eingebetteten
    heterogenen FPGA-Systemen}, publisher={Paderborn University}, author={Hamm, Robin},
    year={2023} }'
  chicago: Hamm, Robin. <i>Verarbeitung von Sensordaten auf eingebetteten heterogenen
    FPGA-Systemen</i>. Paderborn University, 2023.
  ieee: R. Hamm, <i>Verarbeitung von Sensordaten auf eingebetteten heterogenen FPGA-Systemen</i>.
    Paderborn University, 2023.
  mla: Hamm, Robin. <i>Verarbeitung von Sensordaten auf eingebetteten heterogenen
    FPGA-Systemen</i>. Paderborn University, 2023.
  short: R. Hamm, Verarbeitung von Sensordaten auf eingebetteten heterogenen FPGA-Systemen,
    Paderborn University, 2023.
date_created: 2024-05-13T14:01:01Z
date_updated: 2024-05-15T13:29:49Z
department:
- _id: '78'
language:
- iso: ger
publisher: Paderborn University
status: public
supervisor:
- first_name: Lennart
  full_name: Clausing, Lennart
  id: '74287'
  last_name: Clausing
  orcid: 0000-0003-3789-6034
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
title: Verarbeitung von Sensordaten auf eingebetteten heterogenen FPGA-Systemen
type: bachelorsthesis
user_id: '398'
year: '2023'
...
---
_id: '54244'
author:
- first_name: Salem
  full_name: AlAidroos, Salem
  last_name: AlAidroos
citation:
  ama: AlAidroos S. <i>Design and Implementation of a RadioML Demonstrator Based on
    an RFSoC Platform</i>. Paderborn University; 2023.
  apa: AlAidroos, S. (2023). <i>Design and Implementation of a RadioML Demonstrator
    based on an RFSoC Platform</i>. Paderborn University.
  bibtex: '@book{AlAidroos_2023, title={Design and Implementation of a RadioML Demonstrator
    based on an RFSoC Platform}, publisher={Paderborn University}, author={AlAidroos,
    Salem}, year={2023} }'
  chicago: AlAidroos, Salem. <i>Design and Implementation of a RadioML Demonstrator
    Based on an RFSoC Platform</i>. Paderborn University, 2023.
  ieee: S. AlAidroos, <i>Design and Implementation of a RadioML Demonstrator based
    on an RFSoC Platform</i>. Paderborn University, 2023.
  mla: AlAidroos, Salem. <i>Design and Implementation of a RadioML Demonstrator Based
    on an RFSoC Platform</i>. Paderborn University, 2023.
  short: S. AlAidroos, Design and Implementation of a RadioML Demonstrator Based on
    an RFSoC Platform, Paderborn University, 2023.
date_created: 2024-05-13T13:59:16Z
date_updated: 2024-05-15T13:31:46Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Felix
  full_name: Jentzsch, Felix
  id: '55631'
  last_name: Jentzsch
  orcid: 0000-0003-4987-5708
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
title: Design and Implementation of a RadioML Demonstrator based on an RFSoC Platform
type: mastersthesis
user_id: '398'
year: '2023'
...
---
_id: '54242'
author:
- first_name: Gerrit
  full_name: Evers, Gerrit
  last_name: Evers
citation:
  ama: Evers G. <i>Bewertung der Xilinx Runtime Library zur Hardware/Software-Kommunikation</i>.
    Paderborn University; 2023.
  apa: Evers, G. (2023). <i>Bewertung der Xilinx Runtime Library zur Hardware/Software-Kommunikation</i>.
    Paderborn University.
  bibtex: '@book{Evers_2023, title={Bewertung der Xilinx Runtime Library zur Hardware/Software-Kommunikation},
    publisher={Paderborn University}, author={Evers, Gerrit}, year={2023} }'
  chicago: Evers, Gerrit. <i>Bewertung der Xilinx Runtime Library zur Hardware/Software-Kommunikation</i>.
    Paderborn University, 2023.
  ieee: G. Evers, <i>Bewertung der Xilinx Runtime Library zur Hardware/Software-Kommunikation</i>.
    Paderborn University, 2023.
  mla: Evers, Gerrit. <i>Bewertung der Xilinx Runtime Library zur Hardware/Software-Kommunikation</i>.
    Paderborn University, 2023.
  short: G. Evers, Bewertung der Xilinx Runtime Library zur Hardware/Software-Kommunikation,
    Paderborn University, 2023.
date_created: 2024-05-13T13:59:09Z
date_updated: 2024-05-15T13:31:08Z
department:
- _id: '78'
language:
- iso: ger
publisher: Paderborn University
status: public
supervisor:
- first_name: Lennart
  full_name: Clausing, Lennart
  id: '74287'
  last_name: Clausing
  orcid: 0000-0003-3789-6034
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
title: Bewertung der Xilinx Runtime Library zur Hardware/Software-Kommunikation
type: bachelorsthesis
user_id: '398'
year: '2023'
...
---
_id: '46482'
abstract:
- lang: eng
  text: "Ever increasing demands on the performance of microchips are leading to ever
    more complex semiconductor technologies with ever shrinking feature sizes. Complex
    applications with high demands on safety and reliability, such as autonomous driving,
    are simultaneously driving the requirements for test and diagnosis of VLSI circuits.
    Throughout the life cycle of a microchip, uncertainties occur that affect its
    timing behavior. For example, weak circuit structures, aging effects, or process
    variations can lead to a change in the timing behavior of the circuit. While these
    uncertainties do not necessarily lead to a change of the functional behavior,
    they can lead to a reliability problem.\r\nWith modular and hybrid compaction
    two test instruments are presented in this work that can be used for X-tolerant
    test response compaction in the built-in Faster-than-At-Speed Test (FAST) which
    is used to detect uncertainties in VLSI circuits. One challenge for test response
    compaction during FAST is the high and varying X-rate at the outputs of the circuit
    under test. By dividing the circuit outputs into test groups and separately compacting
    these test groups using stochastic compactors, the modular compaction is able
    to handle these high and varying X-rates.\r\nTo deal with uncertainties on logic
    interconnects, a method for distinguishing crosstalk and process variation is
    presented. In current semiconductor technologies, the number of parasitic coupling
    capacitances between logic interconnects is growing. These coupling capacitances
    can lead to crosstalk, which causes increased current flow in the logic interconnects,
    which in turn can lead to increased electromigration. In the presented method,
    delay maps describing the timing behavior of the circuit outputs at different
    operating points are used to train artificial neural networks which classify the
    tested circuits into fault-free and faulty."
- lang: ger
  text: "Immer größere Anforderungen an die Leistungsfähigkeit von Mikrochips führen
    zu Halbleitertechnologien mit immer kleiner werdenden Strukturgrößen. Anwendungen
    mit hohen Ansprüchen an Sicherheit und Zuverlässigkeit, wie z.B. das autonome
    Fahren, treiben gleichzeitig die Anforderungen an den Test hochintegrierter Schaltungen
    an. Während des gesamten Lebenszyklus eines Mikrochips kommt es zu Unsicherheiten
    im Zeitverhalten. So können z.B. schwache Schaltungsstrukturen, Alterungseffekte
    oder Prozessvariationen zu einer Veränderung des Zeitverhaltens führen. Während
    diese Unsicherheiten nicht zu einer Veränderung des funktionalen Verhaltens führen
    müssen, können sie jedoch zu einem Zuverlässigkeitsproblem führen.\r\nMit der
    modularen und der hybriden Kompaktierung werden in dieser Arbeit zwei Testinstrumente
    vorgestellt, die für die X-tolerante Testantwortkompaktierung im eingebauten Hochgeschwindigkeitstest
    verwendet werden können. Eine Herausforderung für die Testantwortkompaktierung
    während des Hochgeschwindigkeitstests ist die hohe und variierende X-Rate an den
    Ausgängen der zu testenden Schaltung. Durch die Einteilung der Schaltungsausgänge
    in Prüfgruppen und die separierte Kompaktierung der Prüfgruppen mithilfe von stochastischen
    Kompaktierern, können die vorgestellten Verfahren diese hohen und variierenden
    X-Raten verarbeiten.\r\nFür den Umgang mit Unsicherheiten auf Verbindungsleitungen
    der Logik-Schaltung wird ein Verfahren zur Unterscheidung von Übersprechen und
    Prozessvariation vorgestellt. In aktuellen Halbleitertechnologien kommt es vermehrt
    zu parasitären Koppelkapazitäten zwischen den Verbindungsleitungen. In dem vorgestellten
    Verfahren werden künstliche neuronale Netze trainiert, um die Schaltungen in fehlerfrei
    und fehlerhaft zu klassifizieren."
author:
- first_name: Alexander
  full_name: Sprenger, Alexander
  id: '22707'
  last_name: Sprenger
  orcid: 0000-0002-0775-7677
citation:
  ama: Sprenger A. <i>Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten
    in Logikblöcken hochintegrierter Schaltungen</i>. Universität Paderborn; 2023.
    doi:<a href="https://doi.org/10.17619/UNIPB/1-1787">10.17619/UNIPB/1-1787</a>
  apa: Sprenger, A. (2023). <i>Testinstrumente und Testdatenanalyse zur Verarbeitung
    von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen</i>. Universität
    Paderborn. <a href="https://doi.org/10.17619/UNIPB/1-1787">https://doi.org/10.17619/UNIPB/1-1787</a>
  bibtex: '@book{Sprenger_2023, place={Paderborn}, title={Testinstrumente und Testdatenanalyse
    zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen},
    DOI={<a href="https://doi.org/10.17619/UNIPB/1-1787">10.17619/UNIPB/1-1787</a>},
    publisher={Universität Paderborn}, author={Sprenger, Alexander}, year={2023} }'
  chicago: 'Sprenger, Alexander. <i>Testinstrumente und Testdatenanalyse zur Verarbeitung
    von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen</i>. Paderborn:
    Universität Paderborn, 2023. <a href="https://doi.org/10.17619/UNIPB/1-1787">https://doi.org/10.17619/UNIPB/1-1787</a>.'
  ieee: 'A. Sprenger, <i>Testinstrumente und Testdatenanalyse zur Verarbeitung von
    Unsicherheiten in Logikblöcken hochintegrierter Schaltungen</i>. Paderborn: Universität
    Paderborn, 2023.'
  mla: Sprenger, Alexander. <i>Testinstrumente und Testdatenanalyse zur Verarbeitung
    von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen</i>. Universität
    Paderborn, 2023, doi:<a href="https://doi.org/10.17619/UNIPB/1-1787">10.17619/UNIPB/1-1787</a>.
  short: A. Sprenger, Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten
    in Logikblöcken hochintegrierter Schaltungen, Universität Paderborn, Paderborn,
    2023.
date_created: 2023-08-12T09:10:38Z
date_updated: 2023-08-12T09:13:18Z
department:
- _id: '48'
doi: 10.17619/UNIPB/1-1787
extern: '1'
keyword:
- Testantwortkompaktierung
- Prozessvariation
- Silicon Lifecycle Management
language:
- iso: ger
main_file_link:
- open_access: '1'
  url: https://nbn-resolving.org/urn:nbn:de:hbz:466:2-45493
oa: '1'
page: xi, 160
place: Paderborn
publication_status: published
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Sybille
  full_name: Hellebrand, Sybille
  id: '209'
  last_name: Hellebrand
  orcid: 0000-0002-3717-3939
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
title: Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in
  Logikblöcken hochintegrierter Schaltungen
type: dissertation
user_id: '22707'
year: '2023'
...
---
_id: '29769'
abstract:
- lang: eng
  text: 'Wettstreit zwischen der Entwicklung neuer Hardwaretrojaner und entsprechender
    Gegenmaßnahmen beschreiten Widersacher immer raffiniertere Wege um Schaltungsentwürfe
    zu infizieren und dabei selbst fortgeschrittene Test- und Verifikationsmethoden
    zu überlisten. Abgesehen von den konventionellen Methoden um einen Trojaner in
    eine Schaltung für ein Field-programmable Gate Array (FPGA) einzuschleusen, können
    auch die Entwurfswerkzeuge heimlich kompromittiert werden um einen Angreifer dabei
    zu unterstützen einen erfolgreichen Angriff durchzuführen, der zum Beispiel Fehlfunktionen
    oder ungewollte Informationsabflüsse bewirken kann. Diese Dissertation beschäftigt
    sich hauptsächlich mit den beiden Blickwinkeln auf Hardwaretrojaner in rekonfigurierbaren
    Systemen, einerseits der Perspektive des Verteidigers mit einer Methode zur Erkennung
    von Trojanern auf der Bitstromebene, und andererseits derjenigen des Angreifers
    mit einer neuartigen Angriffsmethode für FPGA Trojaner. Für die Verteidigung gegen
    den Trojaner ``Heimtückische LUT'''' stellen wir die allererste erfolgreiche Gegenmaßnahme
    vor, die durch Verifikation mittels Proof-carrying Hardware (PCH) auf der Bitstromebene
    direkt vor der Konfiguration der Hardware angewendet werden kann, und präsentieren
    ein vollständiges Schema für den Entwurf und die Verifikation von Schaltungen
    für iCE40 FPGAs. Für die Gegenseite führen wir einen neuen Angriff ein, welcher
    bösartiges Routing im eingefügten Trojaner ausnutzt um selbst im fertigen Bitstrom
    in einem inaktiven Zustand zu verbleiben: Hierdurch kann dieser neuartige Angriff
    zur Zeit weder von herkömmlichen Test- und Verifikationsmethoden, noch von unserer
    vorher vorgestellten Verifikation auf der Bitstromebene entdeckt werden.'
- lang: eng
  text: The battle of developing hardware Trojans and corresponding countermeasures
    has taken adversaries towards ingenious ways of compromising hardware designs
    by circumventing even advanced testing and verification methods. Besides conventional
    methods of inserting Trojans into a design by a malicious entity, the design flow
    for field-programmable gate arrays (FPGAs) can also be surreptitiously compromised
    to assist the attacker to perform a successful malfunctioning or information leakage
    attack. This thesis mainly focuses on the two aspects of hardware Trojans in reconfigurable
    systems, the defenders perspective which corresponds to the bitstream-level Trojan
    detection technique, and the attackers perspective which corresponds to a novel
    FPGA Trojan attack. From the defender's perspective, we introduce a first-ever
    successful pre-configuration countermeasure against the ``Malicious LUT''-hardware
    Trojan, by employing bitstream-level Proof-Carrying Hardware (PCH) and present
    the complete design-and-verification flow for iCE40 FPGAs. Likewise, from an attackers
    perspective, we present a novel attack that leverages malicious routing of the
    inserted Trojan circuit to acquire a dormant state even in the generated and transmitted
    bitstream. Since the Trojan is injected in a post-synthesis step and remains unconnected
    in the bitstream, the presented attack can currently neither be prevented by conventional
    testing and verification methods nor by bitstream-level verification techniques.
author:
- first_name: Qazi Arbab
  full_name: Ahmed, Qazi Arbab
  id: '72764'
  last_name: Ahmed
  orcid: 0000-0002-1837-2254
citation:
  ama: Ahmed QA. <i>Hardware Trojans in Reconfigurable Computing</i>.  Paderborn University,
    Paderborn, Germany; 2022. doi:<a href="https://doi.org/10.17619/UNIPB/1-1271">10.17619/UNIPB/1-1271</a>
  apa: Ahmed, Q. A. (2022). <i>Hardware Trojans in Reconfigurable Computing</i>.  Paderborn
    University, Paderborn, Germany. <a href="https://doi.org/10.17619/UNIPB/1-1271">https://doi.org/10.17619/UNIPB/1-1271</a>
  bibtex: '@book{Ahmed_2022, place={Paderborn}, title={Hardware Trojans in Reconfigurable
    Computing}, DOI={<a href="https://doi.org/10.17619/UNIPB/1-1271">10.17619/UNIPB/1-1271</a>},
    publisher={ Paderborn University, Paderborn, Germany}, author={Ahmed, Qazi Arbab},
    year={2022} }'
  chicago: 'Ahmed, Qazi Arbab. <i>Hardware Trojans in Reconfigurable Computing</i>.
    Paderborn:  Paderborn University, Paderborn, Germany, 2022. <a href="https://doi.org/10.17619/UNIPB/1-1271">https://doi.org/10.17619/UNIPB/1-1271</a>.'
  ieee: 'Q. A. Ahmed, <i>Hardware Trojans in Reconfigurable Computing</i>. Paderborn:  Paderborn
    University, Paderborn, Germany, 2022.'
  mla: Ahmed, Qazi Arbab. <i>Hardware Trojans in Reconfigurable Computing</i>.  Paderborn
    University, Paderborn, Germany, 2022, doi:<a href="https://doi.org/10.17619/UNIPB/1-1271">10.17619/UNIPB/1-1271</a>.
  short: Q.A. Ahmed, Hardware Trojans in Reconfigurable Computing,  Paderborn University,
    Paderborn, Germany, Paderborn, 2022.
date_created: 2022-02-07T14:02:36Z
date_updated: 2022-11-30T13:39:01Z
ddc:
- '004'
department:
- _id: '78'
doi: 10.17619/UNIPB/1-1271
has_accepted_license: '1'
keyword:
- FPGA Security
- Hardware Trojans
- Bitstream-level Trojans
- Bitstream Verification
language:
- iso: eng
main_file_link:
- open_access: '1'
  url: "\turn:nbn:de:hbz:466:2-40303"
oa: '1'
place: Paderborn
project:
- _id: '1'
  name: 'SFB 901: SFB 901'
- _id: '4'
  name: 'SFB 901 - C: SFB 901 - Project Area C'
- _id: '14'
  name: 'SFB 901 - C2: SFB 901 - Subproject C2'
publication_status: published
publisher: ' Paderborn University, Paderborn, Germany'
status: public
supervisor:
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
title: Hardware Trojans in Reconfigurable Computing
type: dissertation
user_id: '477'
year: '2022'
...
---
_id: '34041'
author:
- first_name: Linus Matthias
  full_name: Witschen, Linus Matthias
  id: '49051'
  last_name: Witschen
citation:
  ama: Witschen LM. <i>Frameworks and Methodologies for Search-Based Approximate Logic
    Synthesis</i>.; 2022. doi:<a href="https://doi.org/10.17619/UNIPB/1-1649">10.17619/UNIPB/1-1649</a>
  apa: Witschen, L. M. (2022). <i>Frameworks and Methodologies for Search-based Approximate
    Logic Synthesis</i>. <a href="https://doi.org/10.17619/UNIPB/1-1649">https://doi.org/10.17619/UNIPB/1-1649</a>
  bibtex: '@book{Witschen_2022, title={Frameworks and Methodologies for Search-based
    Approximate Logic Synthesis}, DOI={<a href="https://doi.org/10.17619/UNIPB/1-1649">10.17619/UNIPB/1-1649</a>},
    author={Witschen, Linus Matthias}, year={2022} }'
  chicago: Witschen, Linus Matthias. <i>Frameworks and Methodologies for Search-Based
    Approximate Logic Synthesis</i>, 2022. <a href="https://doi.org/10.17619/UNIPB/1-1649">https://doi.org/10.17619/UNIPB/1-1649</a>.
  ieee: L. M. Witschen, <i>Frameworks and Methodologies for Search-based Approximate
    Logic Synthesis</i>. 2022.
  mla: Witschen, Linus Matthias. <i>Frameworks and Methodologies for Search-Based
    Approximate Logic Synthesis</i>. 2022, doi:<a href="https://doi.org/10.17619/UNIPB/1-1649">10.17619/UNIPB/1-1649</a>.
  short: L.M. Witschen, Frameworks and Methodologies for Search-Based Approximate
    Logic Synthesis, 2022.
date_created: 2022-11-09T06:26:22Z
date_updated: 2023-01-19T06:41:22Z
department:
- _id: '78'
doi: 10.17619/UNIPB/1-1649
language:
- iso: eng
project:
- _id: '1'
  name: 'SFB 901: SFB 901'
- _id: '3'
  name: 'SFB 901 - B: SFB 901 - Project Area B'
- _id: '12'
  name: 'SFB 901 - B4: SFB 901 - Subproject B4'
status: public
supervisor:
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
title: Frameworks and Methodologies for Search-based Approximate Logic Synthesis
type: dissertation
user_id: '15504'
year: '2022'
...
---
_id: '45715'
author:
- first_name: Vanessa Ingrid
  full_name: Tcheussi Ngayap, Vanessa Ingrid
  last_name: Tcheussi Ngayap
citation:
  ama: Tcheussi Ngayap VI. <i>FreeRTOS on a MicroBlaze Soft-Core Processor with Hardware
    Accelerators</i>.; 2022.
  apa: Tcheussi Ngayap, V. I. (2022). <i>FreeRTOS on a MicroBlaze Soft-Core Processor
    with Hardware Accelerators</i>.
  bibtex: '@book{Tcheussi Ngayap_2022, title={FreeRTOS on a MicroBlaze Soft-Core Processor
    with Hardware Accelerators}, author={Tcheussi Ngayap, Vanessa Ingrid}, year={2022}
    }'
  chicago: Tcheussi Ngayap, Vanessa Ingrid. <i>FreeRTOS on a MicroBlaze Soft-Core
    Processor with Hardware Accelerators</i>, 2022.
  ieee: V. I. Tcheussi Ngayap, <i>FreeRTOS on a MicroBlaze Soft-Core Processor with
    Hardware Accelerators</i>. 2022.
  mla: Tcheussi Ngayap, Vanessa Ingrid. <i>FreeRTOS on a MicroBlaze Soft-Core Processor
    with Hardware Accelerators</i>. 2022.
  short: V.I. Tcheussi Ngayap, FreeRTOS on a MicroBlaze Soft-Core Processor with Hardware
    Accelerators, 2022.
date_created: 2023-06-22T12:04:57Z
date_updated: 2023-06-22T12:07:53Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '83'
  name: 'SFB 901 - T1: SFB 901 -Subproject T1'
- _id: '82'
  name: 'SFB 901 - T: SFB 901 - Project Area T'
- _id: '1'
  grant_number: '160364472'
  name: 'SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen
    in dynamischen Märkten '
status: public
supervisor:
- first_name: Lennart
  full_name: Clausing, Lennart
  id: '74287'
  last_name: Clausing
  orcid: 0000-0003-3789-6034
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Sybille
  full_name: Hellebrand, Sybille
  id: '209'
  last_name: Hellebrand
  orcid: 0000-0002-3717-3939
title: FreeRTOS on a MicroBlaze Soft-Core Processor with Hardware Accelerators
type: mastersthesis
user_id: '74287'
year: '2022'
...
---
_id: '26746'
abstract:
- lang: eng
  text: "Previous research in proof-carrying hardware has established the feasibility
    and utility of the approach, and provided a concrete solution for employing it
    for the certification of functional equivalence checking against a specification,
    but fell short in connecting it to state-of-the-art formal verification insights,
    methods and tools. Due to the immense complexity of modern circuits, and verification
    challenges such as the state explosion problem for sequential circuits, this restriction
    of readily-available verification solutions severely limited the applicability
    of the approach in wider contexts.\r\n\r\nThis thesis closes the gap between the
    PCH approach and current advances in formal hardware verification, provides methods
    and tools to express and certify a wide range of circuit properties, both functional
    and non-functional, and presents for the first time prototypes in which circuits
    that are implemented on actual reconfigurable hardware are verified with PCH methods.
    Using these results, designers can now apply PCH to establish trust in more complex
    circuits, by using more diverse properties which they can express using modern,
    efficient property specification techniques."
- lang: ger
  text: "Die bisherige Forschung zu Proof-Carrying Hardware (PCH) hat dessen Machbarkeit
    und Nützlichkeit gezeigt und einen Ansatz zur Zertifizierung der funktionalen
    Äquivalenz zu einer Spezifikation geliefert, jedoch ohne PCH mit aktuellen Erkenntnissen,
    Methoden oder Werkzeugen formaler Hardwareverifikation zu verknüpfen. Aufgrund
    der Komplexität moderner Schaltungen und Verifikationsherausforderungen wie der
    Zustandsexplosion bei sequentiellen Schaltungen, limitiert diese Einschränkung
    sofort verfügbarer Verifikationslösungen die Anwendbarkeit des Ansatzes in einem
    größeren Kontext signifikant.\r\n\r\nDiese Dissertation schließt die Lücke zwischen
    PCH und modernen Entwicklungen in der Schaltungsverifikation und stellt Methoden
    und Werkzeuge zur Verfügung, welche die Zertifizierung einer großen Bandbreite
    von Schaltungseigenschaften ermöglicht; sowohl funktionale, als auch nicht-funktionale.
    Überdies werden erstmals Prototypen vorgestellt in welchen Schaltungen mittels
    PCH verifiziert werden, die auf tatsächlicher rekonfigurierbarer Hardware realisiert
    sind. Dank dieser Ergebnisse können Entwickler PCH zur Herstellung von Vertrauen
    in weit komplexere Schaltungen verwenden, unter Zuhilfenahme einer größeren Vielfalt
    von Eigenschaften, welche durch moderne, effiziente Spezifikationstechniken ausgedrückt
    werden können."
author:
- first_name: Tobias
  full_name: Wiersema, Tobias
  id: '3118'
  last_name: Wiersema
citation:
  ama: Wiersema T. <i>Guaranteeing Properties of Reconfigurable Hardware Circuits
    with Proof-Carrying Hardware</i>. Paderborn University; 2021.
  apa: Wiersema, T. (2021). <i>Guaranteeing Properties of Reconfigurable Hardware
    Circuits with Proof-Carrying Hardware</i>. Paderborn University.
  bibtex: '@book{Wiersema_2021, place={Paderborn}, title={Guaranteeing Properties
    of Reconfigurable Hardware Circuits with Proof-Carrying Hardware}, publisher={Paderborn
    University}, author={Wiersema, Tobias}, year={2021} }'
  chicago: 'Wiersema, Tobias. <i>Guaranteeing Properties of Reconfigurable Hardware
    Circuits with Proof-Carrying Hardware</i>. Paderborn: Paderborn University, 2021.'
  ieee: 'T. Wiersema, <i>Guaranteeing Properties of Reconfigurable Hardware Circuits
    with Proof-Carrying Hardware</i>. Paderborn: Paderborn University, 2021.'
  mla: Wiersema, Tobias. <i>Guaranteeing Properties of Reconfigurable Hardware Circuits
    with Proof-Carrying Hardware</i>. Paderborn University, 2021.
  short: T. Wiersema, Guaranteeing Properties of Reconfigurable Hardware Circuits
    with Proof-Carrying Hardware, Paderborn University, Paderborn, 2021.
date_created: 2021-10-25T06:35:41Z
date_updated: 2022-01-06T06:57:26Z
ddc:
- '006'
department:
- _id: '78'
keyword:
- Proof-Carrying Hardware
- Formal Verification
- Sequential Circuits
- Non-Functional Properties
- Functional Properties
language:
- iso: eng
main_file_link:
- open_access: '1'
  url: https://nbn-resolving.de/urn:nbn:de:hbz:466:2-39800
oa: '1'
page: '293'
place: Paderborn
project:
- _id: '1'
  name: SFB 901
- _id: '3'
  name: SFB 901 - Project Area B
- _id: '12'
  name: SFB 901 - Subproject B4
publication_status: published
publisher: Paderborn University
status: public
supervisor:
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
title: Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying
  Hardware
type: dissertation
user_id: '3118'
year: '2021'
...
---
_id: '29151'
abstract:
- lang: eng
  text: Automation becomes a vital part in the High-Performance computing system in
    situational dynamics to take the decisions on the fly. Heterogeneous compute nodes
    consist of computing resources such as CPU, GPU and FPGA and are the important
    components of the high-performance computing system that can adapt the automation
    to achieve the given goal. While implanting automation in the computing resources,
    management of the resources is one of the essential aspects that need to be taken
    care of. Tasks are continuously executed on the resources using its unique characteristics.
    Effective scheduling is essential to make the best use of the characteristics
    provided by each resource. Scheduling enables the execution of each task by allocating
    resources so that they take advantage of all the characteristics of the compute
    resources. Various scheduling heuristics can be used to create effective scheduling,
    which might require the execution time to schedule the task efficiently. Providing
    actual execution time is not possible in many cases; hence we can provide the
    estimations for the actual execution time . The purpose of this master's thesis
    is to design a predictive model or system that estimates the execution time required
    to execute tasks using historical execution time data on the heterogeneous compute
    nodes. In this thesis, regression techniques(SGD Regressor, Passive-Aggressive
    Regressor, MLP Regressor, and XCSF Regressor) are compared in terms of their prediction
    accuracy in order to determine which technique produces reliable predictions for
    the execution time. These estimations must be generated in an online learning
    environment in which data points arrive in any sequence, one by one, and the regression
    model must learn from them. After evaluating the regression algorithms, it is
    seen that the XCSF regressor provides the highest overall prediction accuracy
    for the supplied data sets. The regression technique's parameters also play a
    significant role in achieving an acceptable prediction accuracy. As a remark,
    when using online learning in regression analysis, the accuracy depends upon both
    the order of sequential data points that are coming to train the model and the
    parameter configuration for each regression technique.
author:
- first_name: Chinmay
  full_name: Kashikar, Chinmay
  last_name: Kashikar
citation:
  ama: Kashikar C. <i>A Comparison of Machine Learning Techniques for the On-Line
    Characterization of Tasks Executed on Heterogeneous Compute Nodes</i>. Paderborn
    University; 2021.
  apa: Kashikar, C. (2021). <i>A Comparison of Machine Learning Techniques for the
    On-line Characterization of Tasks Executed on Heterogeneous Compute Nodes</i>.
    Paderborn University.
  bibtex: '@book{Kashikar_2021, place={Paderborn}, title={A Comparison of Machine
    Learning Techniques for the On-line Characterization of Tasks Executed on Heterogeneous
    Compute Nodes}, publisher={Paderborn University}, author={Kashikar, Chinmay},
    year={2021} }'
  chicago: 'Kashikar, Chinmay. <i>A Comparison of Machine Learning Techniques for
    the On-Line Characterization of Tasks Executed on Heterogeneous Compute Nodes</i>.
    Paderborn: Paderborn University, 2021.'
  ieee: 'C. Kashikar, <i>A Comparison of Machine Learning Techniques for the On-line
    Characterization of Tasks Executed on Heterogeneous Compute Nodes</i>. Paderborn:
    Paderborn University, 2021.'
  mla: Kashikar, Chinmay. <i>A Comparison of Machine Learning Techniques for the On-Line
    Characterization of Tasks Executed on Heterogeneous Compute Nodes</i>. Paderborn
    University, 2021.
  short: C. Kashikar, A Comparison of Machine Learning Techniques for the On-Line
    Characterization of Tasks Executed on Heterogeneous Compute Nodes, Paderborn University,
    Paderborn, 2021.
date_created: 2022-01-04T09:24:52Z
date_updated: 2022-01-06T06:58:46Z
department:
- _id: '78'
language:
- iso: eng
place: Paderborn
project:
- _id: '14'
  name: SFB 901 - Subproject C2
- _id: '4'
  name: SFB 901 - Project Area C
- _id: '1'
  name: SFB 901
publisher: Paderborn University
status: public
supervisor:
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Tim
  full_name: Hansmeier, Tim
  id: '49992'
  last_name: Hansmeier
  orcid: 0000-0003-1377-3339
title: A Comparison of Machine Learning Techniques for the On-line Characterization
  of Tasks Executed on Heterogeneous Compute Nodes
type: mastersthesis
user_id: '49992'
year: '2021'
...