---
_id: '22216'
author:
- first_name: Jakob Werner
  full_name: Rehnen, Jakob Werner
  last_name: Rehnen
citation:
  ama: Rehnen JW. <i>Decomposition of Arithmetic Components for the Approximate Circuit
    Synthesis with EvoApproxLib</i>.; 2021.
  apa: Rehnen, J. W. (2021). <i>Decomposition of Arithmetic Components for the Approximate
    Circuit Synthesis with EvoApproxLib</i>.
  bibtex: '@book{Rehnen_2021, title={Decomposition of Arithmetic Components for the
    Approximate Circuit Synthesis with EvoApproxLib}, author={Rehnen, Jakob Werner},
    year={2021} }'
  chicago: Rehnen, Jakob Werner. <i>Decomposition of Arithmetic Components for the
    Approximate Circuit Synthesis with EvoApproxLib</i>, 2021.
  ieee: J. W. Rehnen, <i>Decomposition of Arithmetic Components for the Approximate
    Circuit Synthesis with EvoApproxLib</i>. 2021.
  mla: Rehnen, Jakob Werner. <i>Decomposition of Arithmetic Components for the Approximate
    Circuit Synthesis with EvoApproxLib</i>. 2021.
  short: J.W. Rehnen, Decomposition of Arithmetic Components for the Approximate Circuit
    Synthesis with EvoApproxLib, 2021.
date_created: 2021-05-19T16:56:11Z
date_updated: 2022-01-06T06:55:29Z
department:
- _id: '78'
- _id: '7'
language:
- iso: eng
status: public
supervisor:
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Linus Matthias
  full_name: Witschen, Linus Matthias
  id: '49051'
  last_name: Witschen
title: Decomposition of Arithmetic Components for the Approximate Circuit Synthesis
  with EvoApproxLib
type: bachelorsthesis
user_id: '49051'
year: '2021'
...
---
_id: '22483'
abstract:
- lang: eng
  text: This bachelor thesis presents a C/C++ implementation of the XCS algorithm
    for an embedded system and profiling results concerning the execution time of
    the functions. These are then analyzed in relation to the input characteristics
    of the examined learning environments and compared with related work. Three main
    conclusions can be drawn from the measured results. First, the maximum size of
    the population of the classifiers influences the runtime of the genetic algorithm;
    second, the size of the input space has a direct effect on the execution time
    of the matching function; and last, a larger action space results in a longer
    runtime generating the prediction for the possible actions. The dependencies identified
    here can serve to optimize the computational efficiency and make XCS more suitable
    for embedded systems.
author:
- first_name: Mathis
  full_name: Brede, Mathis
  last_name: Brede
citation:
  ama: 'Brede M. <i>Implementation and Profiling of XCS in the Context of Embedded
    Systems</i>. Paderborn: Paderborn University; 2021.'
  apa: 'Brede, M. (2021). <i>Implementation and Profiling of XCS in the Context of
    Embedded Systems</i>. Paderborn: Paderborn University.'
  bibtex: '@book{Brede_2021, place={Paderborn}, title={Implementation and Profiling
    of XCS in the Context of Embedded Systems}, publisher={Paderborn University},
    author={Brede, Mathis}, year={2021} }'
  chicago: 'Brede, Mathis. <i>Implementation and Profiling of XCS in the Context of
    Embedded Systems</i>. Paderborn: Paderborn University, 2021.'
  ieee: 'M. Brede, <i>Implementation and Profiling of XCS in the Context of Embedded
    Systems</i>. Paderborn: Paderborn University, 2021.'
  mla: Brede, Mathis. <i>Implementation and Profiling of XCS in the Context of Embedded
    Systems</i>. Paderborn University, 2021.
  short: M. Brede, Implementation and Profiling of XCS in the Context of Embedded
    Systems, Paderborn University, Paderborn, 2021.
date_created: 2021-06-21T09:35:03Z
date_updated: 2022-01-06T06:55:33Z
department:
- _id: '78'
extern: '1'
language:
- iso: eng
place: Paderborn
project:
- _id: '14'
  name: SFB 901 - Subproject C2
- _id: '4'
  name: SFB 901 - Project Area C
- _id: '1'
  name: SFB 901
publisher: Paderborn University
status: public
supervisor:
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Tim
  full_name: Hansmeier, Tim
  id: '49992'
  last_name: Hansmeier
  orcid: 0000-0003-1377-3339
title: Implementation and Profiling of XCS in the Context of Embedded Systems
type: bachelorsthesis
user_id: '477'
year: '2021'
...
---
_id: '29540'
abstract:
- lang: eng
  text: "Autonomous mobile robots are becoming increasingly more capable and widespread.
    Reliable Obstacle avoidance is an integral part of autonomous navigation. This
    involves real time interpretation and processing of a complex environment. Strict
    time and energy constraints of a mobile autonomous system make efficient computation
    extremely desirable. The benefits of employing Hardware/Software co-designed applications
    are obvious and significant. Hardware accelerators are used for efficient processing
    of the algorithms by exploiting parallelism. FPGAs are a class of hardware accelerators,
    which\r\ncan contain hundreds of small execution units, and can be used for Hardware/Software
    co-designed application. However, there is a reluctance when it comes to adoption
    of these devices in well established application domains, such as Robotics, due
    to a steep learning curve needed for FPGA application design. ReconROS has successfully
    bridged the gap between robotic and FPGA application development, by providing
    an intuitive, common development platform for robotic application development
    for FPGA. It does so by integrating Robotics Operating System(ROS) which is an
    industry and academia standard for robotics application development, with ReconOS,
    an operating system for re-configurable hardware. In this thesis an obstacle avoidance
    system is designed and implemented for an autonomous vehicle using ReconROS. The
    objectives of the thesis is to demonstrate and explore ReconROS integration within
    the ROS ecosystem and explore the design process within ReconROS framework, and
    to demonstrate the effectiveness of Hardware Acceleration in Robotics, by analysing
    the resulting architectures for Latency and Power Consumption."
author:
- first_name: Muhammad Aamir
  full_name: Sheikh, Muhammad Aamir
  last_name: Sheikh
citation:
  ama: Sheikh MA. <i>Design and Implementation of a ReconROS-Based Obstacle Avoidance
    System</i>. Paderborn University; 2021.
  apa: Sheikh, M. A. (2021). <i>Design and Implementation of a ReconROS-based Obstacle
    Avoidance System</i>. Paderborn University.
  bibtex: '@book{Sheikh_2021, title={Design and Implementation of a ReconROS-based
    Obstacle Avoidance System}, publisher={Paderborn University}, author={Sheikh,
    Muhammad Aamir}, year={2021} }'
  chicago: Sheikh, Muhammad Aamir. <i>Design and Implementation of a ReconROS-Based
    Obstacle Avoidance System</i>. Paderborn University, 2021.
  ieee: M. A. Sheikh, <i>Design and Implementation of a ReconROS-based Obstacle Avoidance
    System</i>. Paderborn University, 2021.
  mla: Sheikh, Muhammad Aamir. <i>Design and Implementation of a ReconROS-Based Obstacle
    Avoidance System</i>. Paderborn University, 2021.
  short: M.A. Sheikh, Design and Implementation of a ReconROS-Based Obstacle Avoidance
    System, Paderborn University, 2021.
date_created: 2022-01-26T08:50:52Z
date_updated: 2022-01-28T08:30:46Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Christian
  full_name: Lienen, Christian
  id: '60323'
  last_name: Lienen
title: Design and Implementation of a ReconROS-based Obstacle Avoidance System
type: mastersthesis
user_id: '60323'
year: '2021'
...
---
_id: '21324'
author:
- first_name: Khushboo
  full_name: Chandrakar, Khushboo
  last_name: Chandrakar
citation:
  ama: Chandrakar K. <i>Comparison of Feature Selection Techniques to Improve Approximate
    Circuit Synthesis</i>.; 2020.
  apa: Chandrakar, K. (2020). <i>Comparison of Feature Selection Techniques to Improve
    Approximate Circuit Synthesis</i>.
  bibtex: '@book{Chandrakar_2020, title={Comparison of Feature Selection Techniques
    to Improve Approximate Circuit Synthesis}, author={Chandrakar, Khushboo}, year={2020}
    }'
  chicago: Chandrakar, Khushboo. <i>Comparison of Feature Selection Techniques to
    Improve Approximate Circuit Synthesis</i>, 2020.
  ieee: K. Chandrakar, <i>Comparison of Feature Selection Techniques to Improve Approximate
    Circuit Synthesis</i>. 2020.
  mla: Chandrakar, Khushboo. <i>Comparison of Feature Selection Techniques to Improve
    Approximate Circuit Synthesis</i>. 2020.
  short: K. Chandrakar, Comparison of Feature Selection Techniques to Improve Approximate
    Circuit Synthesis, 2020.
date_created: 2021-03-01T09:19:29Z
date_updated: 2022-01-06T06:54:54Z
department:
- _id: '78'
- _id: '7'
language:
- iso: eng
project:
- _id: '52'
  name: Computing Resources Provided by the Paderborn Center for Parallel Computing
status: public
supervisor:
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Linus Matthias
  full_name: Witschen, Linus Matthias
  id: '49051'
  last_name: Witschen
title: Comparison of Feature Selection Techniques to Improve Approximate Circuit Synthesis
type: mastersthesis
user_id: '49051'
year: '2020'
...
---
_id: '21432'
abstract:
- lang: eng
  text: "Robots are becoming increasingly autonomous and more capable. Because of
    a limited portable energy budget by e.g. batteries, and more demanding algorithms,
    an efficient computation is of interest. Field Programmable Gate Arrays (FPGAs)
    for example can provide fast and efficient processing and the Robot Operating
    System (ROS) is a popular\r\nmiddleware used for robotic applications. The novel
    ReconROS combines version 2 of the Robot Operating System with ReconOS, a framework
    for integrating reconfigurable hardware. It provides a unified interface between
    software and hardware. ReconROS is evaluated in this thesis by implementing a
    Sobel filter as the video processing application, running on a Zynq-7000 series
    System on Chip. Timing measurements were taken of execution and transfer times
    and were compared to theoretical values. Designing the hardware implementation
    is done by C code using High Level Synthesis and with the interface and functionality
    provided by ReconROS. An important aspect is the publish/subscribe mechanism of
    ROS. The Operating System interface functions for publishing and subscribing are
    reasonably fast at below 10 ms for a 1 MB color VGA image. The main memory interface
    performs well at higher data sizes, crossing 100 MB/s at 20 kB and increasing
    to a maximum of around 150 MB/s. Furthermore, the hardware implementation introduces
    consistency to the execution times and performs twice as fast as the software
    implementation."
author:
- first_name: Luca-Sebastian
  full_name: Henke, Luca-Sebastian
  last_name: Henke
citation:
  ama: Henke L-S. <i>Evaluation of a ReconOS-ROS Combination Based on a Video Processing
    Application</i>.; 2020.
  apa: Henke, L.-S. (2020). <i>Evaluation of a ReconOS-ROS Combination based on a
    Video Processing Application</i>.
  bibtex: '@book{Henke_2020, title={Evaluation of a ReconOS-ROS Combination based
    on a Video Processing Application}, author={Henke, Luca-Sebastian}, year={2020}
    }'
  chicago: Henke, Luca-Sebastian. <i>Evaluation of a ReconOS-ROS Combination Based
    on a Video Processing Application</i>, 2020.
  ieee: L.-S. Henke, <i>Evaluation of a ReconOS-ROS Combination based on a Video Processing
    Application</i>. 2020.
  mla: Henke, Luca-Sebastian. <i>Evaluation of a ReconOS-ROS Combination Based on
    a Video Processing Application</i>. 2020.
  short: L.-S. Henke, Evaluation of a ReconOS-ROS Combination Based on a Video Processing
    Application, 2020.
date_created: 2021-03-10T07:07:01Z
date_updated: 2022-01-06T06:54:59Z
department:
- _id: '78'
language:
- iso: eng
status: public
supervisor:
- first_name: Christian
  full_name: Lienen, Christian
  id: '60323'
  last_name: Lienen
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
title: Evaluation of a ReconOS-ROS Combination based on a Video Processing Application
type: bachelorsthesis
user_id: '60323'
year: '2020'
...
---
_id: '20820'
author:
- first_name: Simon
  full_name: Thiele, Simon
  last_name: Thiele
citation:
  ama: Thiele S. <i>Implementing Machine Learning Functions as PYNQ FPGA Overlays</i>.;
    2020.
  apa: Thiele, S. (2020). <i>Implementing Machine Learning Functions as PYNQ FPGA
    Overlays</i>.
  bibtex: '@book{Thiele_2020, title={Implementing Machine Learning Functions as PYNQ
    FPGA Overlays}, author={Thiele, Simon}, year={2020} }'
  chicago: Thiele, Simon. <i>Implementing Machine Learning Functions as PYNQ FPGA
    Overlays</i>, 2020.
  ieee: S. Thiele, <i>Implementing Machine Learning Functions as PYNQ FPGA Overlays</i>.
    2020.
  mla: Thiele, Simon. <i>Implementing Machine Learning Functions as PYNQ FPGA Overlays</i>.
    2020.
  short: S. Thiele, Implementing Machine Learning Functions as PYNQ FPGA Overlays,
    2020.
date_created: 2020-12-21T13:59:55Z
date_updated: 2022-01-06T06:54:40Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '1'
  name: SFB 901
- _id: '82'
  name: SFB 901 - Project Area T
- _id: '83'
  name: SFB 901 -Subproject T1
status: public
supervisor:
- first_name: Lennart
  full_name: Clausing, Lennart
  id: '74287'
  last_name: Clausing
  orcid: 0000-0003-3789-6034
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
title: Implementing Machine Learning Functions as PYNQ FPGA Overlays
type: bachelorsthesis
user_id: '74287'
year: '2020'
...
---
_id: '20821'
author:
- first_name: Vivek
  full_name: Jaganath, Vivek
  last_name: Jaganath
citation:
  ama: Jaganath V. <i>Extension and Evaluation of Python-Based High-Level Synthesis
    Tool Flows</i>.; 2020.
  apa: Jaganath, V. (2020). <i>Extension and Evaluation of Python-based High-Level
    Synthesis Tool Flows</i>.
  bibtex: '@book{Jaganath_2020, title={Extension and Evaluation of Python-based High-Level
    Synthesis Tool Flows}, author={Jaganath, Vivek}, year={2020} }'
  chicago: Jaganath, Vivek. <i>Extension and Evaluation of Python-Based High-Level
    Synthesis Tool Flows</i>, 2020.
  ieee: V. Jaganath, <i>Extension and Evaluation of Python-based High-Level Synthesis
    Tool Flows</i>. 2020.
  mla: Jaganath, Vivek. <i>Extension and Evaluation of Python-Based High-Level Synthesis
    Tool Flows</i>. 2020.
  short: V. Jaganath, Extension and Evaluation of Python-Based High-Level Synthesis
    Tool Flows, 2020.
date_created: 2020-12-21T14:02:42Z
date_updated: 2022-01-06T06:54:40Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '1'
  name: SFB 901
- _id: '82'
  name: SFB 901 - Project Area T
- _id: '83'
  name: SFB 901 -Subproject T1
status: public
supervisor:
- first_name: Lennart
  full_name: Clausing, Lennart
  id: '74287'
  last_name: Clausing
  orcid: 0000-0003-3789-6034
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
title: Extension and Evaluation of Python-based High-Level Synthesis Tool Flows
type: mastersthesis
user_id: '74287'
year: '2020'
...
---
_id: '21433'
abstract:
- lang: eng
  text: "Modern machine learning (ML) techniques continue to move into the embedded
    system space because traditional centralized compute resources do not suit certain
    application domains, for example in mobile or real-time environments. Google’s
    TensorFlow Lite (TFLite) framework supports this shift from cloud to edge computing
    and makes ML inference accessible on resource-constrained devices. While it offers
    the possibility to partially delegate computation to hardware accelerators, there
    is no such “delegate” available to utilize the promising characteristics of reconfigurable
    hardware.\r\nThis thesis incorporates modern platform FPGAs into TFLite by implementing
    a modular delegate framework, which allows accelerators within the programmable
    logic to take over the execution of neural network layers. To facilitate the necessary
    hardware/software codesign, the FPGA delegate is based on the operating system
    for reconfigurable\r\ncomputing (ReconOS), whose partial reconfiguration support
    enables the instantiation of model-tailored accelerator architectures. In the
    hardware back-end, a streaming-based prototype accelerator for the MobileNet model
    family showcases the working order of the platform, but falls short of the desired
    performance. Thus, it indicates the need for further exploration of alternative
    accelerator designs, which the delegate could automatically synthesize to meet
    a model’s demands."
author:
- first_name: Felix P.
  full_name: Jentzsch, Felix P.
  last_name: Jentzsch
citation:
  ama: Jentzsch FP. <i>Design and Implementation of a ReconOS-Based TensorFlow Lite
    Delegate Architecture</i>.; 2020.
  apa: Jentzsch, F. P. (2020). <i>Design and Implementation of a ReconOS-based TensorFlow
    Lite Delegate Architecture</i>.
  bibtex: '@book{Jentzsch_2020, title={Design and Implementation of a ReconOS-based
    TensorFlow Lite Delegate Architecture}, author={Jentzsch, Felix P.}, year={2020}
    }'
  chicago: Jentzsch, Felix P. <i>Design and Implementation of a ReconOS-Based TensorFlow
    Lite Delegate Architecture</i>, 2020.
  ieee: F. P. Jentzsch, <i>Design and Implementation of a ReconOS-based TensorFlow
    Lite Delegate Architecture</i>. 2020.
  mla: Jentzsch, Felix P. <i>Design and Implementation of a ReconOS-Based TensorFlow
    Lite Delegate Architecture</i>. 2020.
  short: F.P. Jentzsch, Design and Implementation of a ReconOS-Based TensorFlow Lite
    Delegate Architecture, 2020.
date_created: 2021-03-10T07:09:14Z
date_updated: 2023-07-09T17:12:52Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '1'
  grant_number: '160364472'
  name: 'SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen
    in dynamischen Märkten '
- _id: '82'
  name: 'SFB 901 - T: SFB 901 - Project Area T'
- _id: '83'
  name: 'SFB 901 - T1: SFB 901 -Subproject T1'
status: public
supervisor:
- first_name: Christian
  full_name: Lienen, Christian
  id: '60323'
  last_name: Lienen
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
title: Design and Implementation of a ReconOS-based TensorFlow Lite Delegate Architecture
type: mastersthesis
user_id: '398'
year: '2020'
...
---
_id: '15920'
abstract:
- lang: eng
  text: "Secure hardware design is the most important aspect to be considered in addition
    to functional correctness. Achieving hardware security in today’s globalized Integrated
    Cir- cuit(IC) supply chain is a challenging task. One solution that is widely
    considered to help achieve secure hardware designs is Information Flow Tracking(IFT).
    It provides an ap- proach to verify that the systems adhere to security properties
    either by static verification during design phase or dynamic checking during runtime.\r\nProof-Carrying
    Hardware(PCH) is an approach to verify a functional design prior to using it in
    hardware. It is a two-party verification approach, where the target party, the
    consumer requests new functionalities with pre-defined properties to the producer.
    In response, the producer designs the IP (Intellectual Property) cores with the
    requested functionalities that adhere to the consumer-defined properties. The
    producer provides the IP cores and a proof certificate combined into a proof-carrying
    bitstream to the consumer to verify it. If the verification is successful, the
    consumer can use the IP cores in his hardware. In essence, the consumer can only
    run verified IP cores. Correctly applied, PCH techniques can help consumers to
    defend against many unintentional modifications and malicious alterations of the
    modules they receive. There are numerous published examples of how to use PCH
    to detect any change in the functionality of a circuit, i.e., pairing a PCH approach
    with functional equivalence checking for combinational or sequential circuits.
    For non-functional properties, since opening new covert channels to leak secret
    information from secure circuits is a viable attack vector for hardware trojans,
    i.e., intentionally added malicious circuitry, IFT technique is employed to make
    sure that secret/untrusted information never reaches any unclassified/trusted
    outputs.\r\nThis master thesis aims to explore the possibility of adapting Information
    Flow Tracking into a Proof-Carrying Hardware scenario. It aims to create a method
    that combines Infor- mation Flow Tracking(IFT) with a PCH approach at bitstream
    level enabling consumers to validate the trustworthiness of a module’s information
    flow without the computational costs of a complete flow analysis."
author:
- first_name: Monica
  full_name: Keerthipati, Monica
  last_name: Keerthipati
citation:
  ama: Keerthipati M. <i>A Bitstream-Level Proof-Carrying Hardware Technique for Information
    Flow Tracking</i>. Universität Paderborn; 2019.
  apa: Keerthipati, M. (2019). <i>A Bitstream-Level Proof-Carrying Hardware Technique
    for Information Flow Tracking</i>. Universität Paderborn.
  bibtex: '@book{Keerthipati_2019, title={A Bitstream-Level Proof-Carrying Hardware
    Technique for Information Flow Tracking}, publisher={Universität Paderborn}, author={Keerthipati,
    Monica}, year={2019} }'
  chicago: Keerthipati, Monica. <i>A Bitstream-Level Proof-Carrying Hardware Technique
    for Information Flow Tracking</i>. Universität Paderborn, 2019.
  ieee: M. Keerthipati, <i>A Bitstream-Level Proof-Carrying Hardware Technique for
    Information Flow Tracking</i>. Universität Paderborn, 2019.
  mla: Keerthipati, Monica. <i>A Bitstream-Level Proof-Carrying Hardware Technique
    for Information Flow Tracking</i>. Universität Paderborn, 2019.
  short: M. Keerthipati, A Bitstream-Level Proof-Carrying Hardware Technique for Information
    Flow Tracking, Universität Paderborn, 2019.
date_created: 2020-02-17T12:03:40Z
date_updated: 2022-01-06T06:52:41Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '12'
  name: SFB 901 - Subproject B4
- _id: '3'
  name: SFB 901 - Project Area B
- _id: '1'
  name: SFB 901
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Tobias
  full_name: Wiersema, Tobias
  id: '3118'
  last_name: Wiersema
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Sybille
  full_name: Hellebrand, Sybille
  id: '209'
  last_name: Hellebrand
  orcid: 0000-0002-3717-3939
title: A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking
type: mastersthesis
user_id: '477'
year: '2019'
...
---
_id: '14831'
author:
- first_name: Nithin S.
  full_name: Sabu, Nithin S.
  last_name: Sabu
citation:
  ama: Sabu NS. <i>FPGA Acceleration of String Search Techniques in Huge Data Sets</i>.
    Paderborn University; 2019.
  apa: Sabu, N. S. (2019). <i>FPGA Acceleration of String Search Techniques in Huge
    Data Sets</i>. Paderborn University.
  bibtex: '@book{Sabu_2019, title={FPGA Acceleration of String Search Techniques in
    Huge Data Sets}, publisher={Paderborn University}, author={Sabu, Nithin S.}, year={2019}
    }'
  chicago: Sabu, Nithin S. <i>FPGA Acceleration of String Search Techniques in Huge
    Data Sets</i>. Paderborn University, 2019.
  ieee: N. S. Sabu, <i>FPGA Acceleration of String Search Techniques in Huge Data
    Sets</i>. Paderborn University, 2019.
  mla: Sabu, Nithin S. <i>FPGA Acceleration of String Search Techniques in Huge Data
    Sets</i>. Paderborn University, 2019.
  short: N.S. Sabu, FPGA Acceleration of String Search Techniques in Huge Data Sets,
    Paderborn University, 2019.
date_created: 2019-11-06T12:06:09Z
date_updated: 2022-01-06T06:52:07Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Stefan
  full_name: Böttcher, Stefan
  last_name: Böttcher
- first_name: Tobias
  full_name: Wiersema, Tobias
  id: '3118'
  last_name: Wiersema
title: FPGA Acceleration of String Search Techniques in Huge Data Sets
type: mastersthesis
user_id: '3118'
year: '2019'
...
---
_id: '14546'
author:
- first_name: Tim
  full_name: Hansmeier, Tim
  id: '49992'
  last_name: Hansmeier
  orcid: 0000-0003-1377-3339
citation:
  ama: Hansmeier T. <i>Autonomous Operation of High-Performance Compute Nodes through
    Self-Awareness and Learning Classifiers</i>. Universität Paderborn; 2019.
  apa: Hansmeier, T. (2019). <i>Autonomous Operation of High-Performance Compute Nodes
    through Self-Awareness and Learning Classifiers</i>. Universität Paderborn.
  bibtex: '@book{Hansmeier_2019, title={Autonomous Operation of High-Performance Compute
    Nodes through Self-Awareness and Learning Classifiers}, publisher={Universität
    Paderborn}, author={Hansmeier, Tim}, year={2019} }'
  chicago: Hansmeier, Tim. <i>Autonomous Operation of High-Performance Compute Nodes
    through Self-Awareness and Learning Classifiers</i>. Universität Paderborn, 2019.
  ieee: T. Hansmeier, <i>Autonomous Operation of High-Performance Compute Nodes through
    Self-Awareness and Learning Classifiers</i>. Universität Paderborn, 2019.
  mla: Hansmeier, Tim. <i>Autonomous Operation of High-Performance Compute Nodes through
    Self-Awareness and Learning Classifiers</i>. Universität Paderborn, 2019.
  short: T. Hansmeier, Autonomous Operation of High-Performance Compute Nodes through
    Self-Awareness and Learning Classifiers, Universität Paderborn, 2019.
date_created: 2019-11-05T14:32:46Z
date_updated: 2022-01-06T06:52:02Z
department:
- _id: '78'
- _id: '34'
- _id: '7'
language:
- iso: eng
project:
- _id: '14'
  name: SFB 901 - Subproject C2
- _id: '4'
  name: SFB 901 - Project Area C
- _id: '1'
  name: SFB 901
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
title: Autonomous Operation of High-Performance Compute Nodes through Self-Awareness
  and Learning Classifiers
type: mastersthesis
user_id: '477'
year: '2019'
...
---
_id: '15874'
author:
- first_name: Christian
  full_name: Lienen, Christian
  id: '60323'
  last_name: Lienen
citation:
  ama: Lienen C. <i>Implementing a Real-Time System on a Platform FPGA Operated with
    ReconOS</i>. Universität Paderborn
  apa: Lienen, C. (n.d.). <i>Implementing a Real-time System on a Platform FPGA operated
    with ReconOS</i>. Universität Paderborn.
  bibtex: '@book{Lienen, title={Implementing a Real-time System on a Platform FPGA
    operated with ReconOS}, publisher={Universität Paderborn}, author={Lienen, Christian}
    }'
  chicago: Lienen, Christian. <i>Implementing a Real-Time System on a Platform FPGA
    Operated with ReconOS</i>. Universität Paderborn, n.d.
  ieee: C. Lienen, <i>Implementing a Real-time System on a Platform FPGA operated
    with ReconOS</i>. Universität Paderborn.
  mla: Lienen, Christian. <i>Implementing a Real-Time System on a Platform FPGA Operated
    with ReconOS</i>. Universität Paderborn.
  short: C. Lienen, Implementing a Real-Time System on a Platform FPGA Operated with
    ReconOS, Universität Paderborn, n.d.
date_created: 2020-02-11T10:22:06Z
date_updated: 2023-07-31T11:58:50Z
ddc:
- '004'
department:
- _id: '78'
file:
- access_level: open_access
  content_type: application/pdf
  creator: clienen
  date_created: 2020-07-01T11:46:49Z
  date_updated: 2021-02-13T16:46:58Z
  file_id: '17351'
  file_name: thesis_main.pdf
  file_size: 5920668
  relation: main_file
file_date_updated: 2021-02-13T16:46:58Z
has_accepted_license: '1'
language:
- iso: eng
oa: '1'
project:
- _id: '83'
  name: 'SFB 901 - T1: SFB 901 -Subproject T1'
- _id: '82'
  name: 'SFB 901 - T: SFB 901 - Project Area T'
- _id: '1'
  grant_number: '160364472'
  name: 'SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen
    in dynamischen Märkten '
publication_status: submitted
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Lennart
  full_name: Clausing, Lennart
  id: '74287'
  last_name: Clausing
  orcid: 0000-0003-3789-6034
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Sybille
  full_name: Hellebrand, Sybille
  id: '209'
  last_name: Hellebrand
  orcid: 0000-0002-3717-3939
title: Implementing a Real-time System on a Platform FPGA operated with ReconOS
type: mastersthesis
user_id: '60323'
year: '2019'
...
---
_id: '3365'
author:
- first_name: Jan-Philip
  full_name: Schnuer, Jan-Philip
  last_name: Schnuer
citation:
  ama: Schnuer J-P. <i>Static Scheduling Algorithms for Heterogeneous Compute Nodes</i>.
    Universität Paderborn; 2018.
  apa: Schnuer, J.-P. (2018). <i>Static Scheduling Algorithms for Heterogeneous Compute
    Nodes</i>. Universität Paderborn.
  bibtex: '@book{Schnuer_2018, title={Static Scheduling Algorithms for Heterogeneous
    Compute Nodes}, publisher={Universität Paderborn}, author={Schnuer, Jan-Philip},
    year={2018} }'
  chicago: Schnuer, Jan-Philip. <i>Static Scheduling Algorithms for Heterogeneous
    Compute Nodes</i>. Universität Paderborn, 2018.
  ieee: J.-P. Schnuer, <i>Static Scheduling Algorithms for Heterogeneous Compute Nodes</i>.
    Universität Paderborn, 2018.
  mla: Schnuer, Jan-Philip. <i>Static Scheduling Algorithms for Heterogeneous Compute
    Nodes</i>. Universität Paderborn, 2018.
  short: J.-P. Schnuer, Static Scheduling Algorithms for Heterogeneous Compute Nodes,
    Universität Paderborn, 2018.
date_created: 2018-06-26T14:10:18Z
date_updated: 2022-01-06T06:59:13Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '14'
  name: SFB 901 - Subproject C2
- _id: '1'
  name: SFB 901
- _id: '4'
  name: SFB 901 - Project Area C
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Achim
  full_name: Lösch, Achim
  id: '43646'
  last_name: Lösch
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
title: Static Scheduling Algorithms for Heterogeneous Compute Nodes
type: bachelorsthesis
user_id: '477'
year: '2018'
...
---
_id: '3366'
author:
- first_name: Marcel
  full_name: Croce, Marcel
  last_name: Croce
citation:
  ama: Croce M. <i>Evaluation of OpenCL-Based Compilation for FPGAs</i>. Universität
    Paderborn; 2018.
  apa: Croce, M. (2018). <i>Evaluation of OpenCL-based Compilation for FPGAs</i>.
    Universität Paderborn.
  bibtex: '@book{Croce_2018, title={Evaluation of OpenCL-based Compilation for FPGAs},
    publisher={Universität Paderborn}, author={Croce, Marcel}, year={2018} }'
  chicago: Croce, Marcel. <i>Evaluation of OpenCL-Based Compilation for FPGAs</i>.
    Universität Paderborn, 2018.
  ieee: M. Croce, <i>Evaluation of OpenCL-based Compilation for FPGAs</i>. Universität
    Paderborn, 2018.
  mla: Croce, Marcel. <i>Evaluation of OpenCL-Based Compilation for FPGAs</i>. Universität
    Paderborn, 2018.
  short: M. Croce, Evaluation of OpenCL-Based Compilation for FPGAs, Universität Paderborn,
    2018.
date_created: 2018-06-26T14:12:00Z
date_updated: 2022-01-06T06:59:13Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '14'
  name: SFB 901 - Subproject C2
- _id: '1'
  name: SFB 901
- _id: '4'
  name: SFB 901 - Project Area C
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Achim
  full_name: Lösch, Achim
  id: '43646'
  last_name: Lösch
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
title: Evaluation of OpenCL-based Compilation for FPGAs
type: bachelorsthesis
user_id: '477'
year: '2018'
...
---
_id: '3720'
abstract:
- lang: eng
  text: Traditional cache design uses a consolidated block of memory address bits
    to index a cache set, equivalent to the use of modulo functions. While this module-based
    mapping scheme is widely used in contemporary cache structures due to the simplicity
    of its hardware design and its good performance for sequences of consecutive addresses,
    its use may not be satisfactory for a variety of application domains having different
    characteristics.This thesis presents a new type of cache mapping scheme, motivated
    by programmable capabilities combined with Nature-inspired optimization of reconfigurable
    hardware. This research has focussed on an FPGA-based evolvable cache structure
    of the first level cache in a multi-core processor architecture, able to dynamically
    change cache indexing. To solve the challenge of reconfigurable cache mappings,
    a programmable Boolean circuit based on a combination of Look-up Table (LUT) memory
    elements is proposed. Focusing on optimization aspects at the system level, a
    Performance Measurement Infrastructure is introduced that is able to monitor the
    underlying microarchitectural metrics, and an adaptive evaluation strategy is
    presented that leverages on Evolutionary Algorithms, that is not only capable
    of evolving application-specific address-to-cache-index mappings for level one
    split caches but also of reducing optimization times. Putting this all together
    and prototyping in an FPGA for a LEON3/Linux-based multi-core processor, the creation
    of a system architecture reduces cache misses and improves performance over the
    use of conventional caches.
- lang: ger
  text: Traditionelle Cachedesigns verwenden konsolidierte Blöcke von Speicheradressbits
    um einen Cachesatz zu indizieren, vergleichbar mit der Anwendung einer Modulofunktion.
    Obwohl dieses modulobasierte Abbildungsschema in heutigen Cachestrukturen weit
    verbreitet ist, vor allem wegen seiner einfachen Anforderungen an das Hardwaredesign
    und seiner Effizienz für die Indizierung eufeinanderfolgender Speicheradressen,
    kann seine Verwendung für eine Vielzahl von Anwendungsdomänen mit unterschiedlichen
    Charakteristiken zu suboptimalen Ergebnissen führen. Diese Dissertation präsentiert
    einen neuen Typ von Cacheabbildungsschema, motiviert durch die Kombination programmierbarer
    Ressourcen mit der naturinspirierten Optimierung rekonfigurierbarer Hardware.
    Im Fokus dieser Forschung steht eine FPGA-basierte Cachestruktur für den first
    level Cache einer Mehrkernprozessorarchitektur, welche die Cacheindizierung dynamisch
    ändern kann. Um die Herausforderung rekonfigurierbarer Cacheabbildungen zu lösen,
    wird eine reprogrammierbare Boolesche Schaltung eingeführt, die auf Look-up Table
    (LUT) Speicherelementen basiert. Weiterhin wird eine Infrastruktur zur Effizienzmessung
    eingeführt, welche die zugrundeliege Mikroarchitektur überwachen kann, sowie eine
    adaptive Evaluationsstrategie präsentiert, die evolutionäre Algorithmen wirksam
    einsetzt, und die nicht nur anwendungsspezifische Abbildungen von Speicheradressen
    zu Cacheindizes für level one Caches evolvieren sondern dabei auch die Optimierungszeiten
    reduzieren kann. All diese Aspekte zusammen in einer prototypischen Implementierung
    auf einem FPGA für einen LEON3/Linux-basierten Mehrkernprozessor zeigen, dass
    evolvierbare Cacheabbildungsfunktionen Cache Misses reduzieren, sowie die Effizienz
    im Vergleich zu konventionellen Caches erhöhen können.
author:
- first_name: Nam
  full_name: Ho, Nam
  last_name: Ho
citation:
  ama: 'Ho N. <i>FPGA-Based Reconfigurable Cache Mapping Schemes: Design and Optimization</i>.
    Universität Paderborn; 2018. doi:<a href="https://doi.org/10.17619/UNIPB/1-376">10.17619/UNIPB/1-376</a>'
  apa: 'Ho, N. (2018). <i>FPGA-based Reconfigurable Cache Mapping Schemes: Design
    and Optimization</i>. Universität Paderborn. <a href="https://doi.org/10.17619/UNIPB/1-376">https://doi.org/10.17619/UNIPB/1-376</a>'
  bibtex: '@book{Ho_2018, title={FPGA-based Reconfigurable Cache Mapping Schemes:
    Design and Optimization}, DOI={<a href="https://doi.org/10.17619/UNIPB/1-376">10.17619/UNIPB/1-376</a>},
    publisher={Universität Paderborn}, author={Ho, Nam}, year={2018} }'
  chicago: 'Ho, Nam. <i>FPGA-Based Reconfigurable Cache Mapping Schemes: Design and
    Optimization</i>. Universität Paderborn, 2018. <a href="https://doi.org/10.17619/UNIPB/1-376">https://doi.org/10.17619/UNIPB/1-376</a>.'
  ieee: 'N. Ho, <i>FPGA-based Reconfigurable Cache Mapping Schemes: Design and Optimization</i>.
    Universität Paderborn, 2018.'
  mla: 'Ho, Nam. <i>FPGA-Based Reconfigurable Cache Mapping Schemes: Design and Optimization</i>.
    Universität Paderborn, 2018, doi:<a href="https://doi.org/10.17619/UNIPB/1-376">10.17619/UNIPB/1-376</a>.'
  short: 'N. Ho, FPGA-Based Reconfigurable Cache Mapping Schemes: Design and Optimization,
    Universität Paderborn, 2018.'
date_created: 2018-07-27T06:41:13Z
date_updated: 2022-01-06T06:59:31Z
department:
- _id: '78'
doi: 10.17619/UNIPB/1-376
language:
- iso: eng
page: '139'
project:
- _id: '12'
  name: SFB 901 - Subproject B4
- _id: '1'
  name: SFB 901
- _id: '3'
  name: SFB 901 - Project Area B
publication_status: published
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Paul
  full_name: Kaufmann, Paul
  last_name: Kaufmann
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
title: 'FPGA-based Reconfigurable Cache Mapping Schemes: Design and Optimization'
type: dissertation
user_id: '477'
year: '2018'
...
---
_id: '3580'
author:
- first_name: Tim
  full_name: Hansmeier, Tim
  id: '49992'
  last_name: Hansmeier
  orcid: 0000-0003-1377-3339
citation:
  ama: Hansmeier T. <i>An FPGA Accelerator for Checking Resolution Proofs</i>. Universität
    Paderborn; 2017.
  apa: Hansmeier, T. (2017). <i>An FPGA Accelerator for Checking Resolution Proofs</i>.
    Universität Paderborn.
  bibtex: '@book{Hansmeier_2017, title={An FPGA Accelerator for Checking Resolution
    Proofs}, publisher={Universität Paderborn}, author={Hansmeier, Tim}, year={2017}
    }'
  chicago: Hansmeier, Tim. <i>An FPGA Accelerator for Checking Resolution Proofs</i>.
    Universität Paderborn, 2017.
  ieee: T. Hansmeier, <i>An FPGA Accelerator for Checking Resolution Proofs</i>. Universität
    Paderborn, 2017.
  mla: Hansmeier, Tim. <i>An FPGA Accelerator for Checking Resolution Proofs</i>.
    Universität Paderborn, 2017.
  short: T. Hansmeier, An FPGA Accelerator for Checking Resolution Proofs, Universität
    Paderborn, 2017.
date_created: 2018-07-20T13:44:34Z
date_updated: 2022-01-06T06:59:25Z
department:
- _id: '78'
- _id: '34'
- _id: '7'
language:
- iso: eng
project:
- _id: '1'
  name: SFB 901
- _id: '3'
  name: SFB 901 - Project Area B
- _id: '12'
  name: SFB 901 - Subproject B4
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
title: An FPGA Accelerator for Checking Resolution Proofs
type: bachelorsthesis
user_id: '3118'
year: '2017'
...
---
_id: '1157'
author:
- first_name: Linus Matthias
  full_name: Witschen, Linus Matthias
  id: '49051'
  last_name: Witschen
citation:
  ama: Witschen LM. <i>A Framework for the Synthesis of Approximate Circuits</i>.
    Universität Paderborn; 2017.
  apa: Witschen, L. M. (2017). <i>A Framework for the Synthesis of Approximate Circuits</i>.
    Universität Paderborn.
  bibtex: '@book{Witschen_2017, title={A Framework for the Synthesis of Approximate
    Circuits}, publisher={Universität Paderborn}, author={Witschen, Linus Matthias},
    year={2017} }'
  chicago: Witschen, Linus Matthias. <i>A Framework for the Synthesis of Approximate
    Circuits</i>. Universität Paderborn, 2017.
  ieee: L. M. Witschen, <i>A Framework for the Synthesis of Approximate Circuits</i>.
    Universität Paderborn, 2017.
  mla: Witschen, Linus Matthias. <i>A Framework for the Synthesis of Approximate Circuits</i>.
    Universität Paderborn, 2017.
  short: L.M. Witschen, A Framework for the Synthesis of Approximate Circuits, Universität
    Paderborn, 2017.
date_created: 2018-02-01T14:21:19Z
date_updated: 2022-01-06T06:51:03Z
department:
- _id: '78'
- _id: '7'
language:
- iso: eng
project:
- _id: '1'
  name: SFB 901
- _id: '3'
  name: SFB 901 - Project Area B
- _id: '12'
  name: SFB 901 - Subproject B4
- _id: '52'
  name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Tobias
  full_name: Wiersema, Tobias
  id: '3118'
  last_name: Wiersema
title: A Framework for the Synthesis of Approximate Circuits
type: mastersthesis
user_id: '477'
year: '2017'
...
---
_id: '74'
author:
- first_name: Christoph
  full_name: Knorr, Christoph
  last_name: Knorr
citation:
  ama: Knorr C. <i>OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten</i>.
    Universität Paderborn; 2017.
  apa: Knorr, C. (2017). <i>OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten</i>.
    Universität Paderborn.
  bibtex: '@book{Knorr_2017, title={OpenCL-basierte Videoverarbeitung auf heterogenen
    Rechenknoten}, publisher={Universität Paderborn}, author={Knorr, Christoph}, year={2017}
    }'
  chicago: Knorr, Christoph. <i>OpenCL-basierte Videoverarbeitung auf heterogenen
    Rechenknoten</i>. Universität Paderborn, 2017.
  ieee: C. Knorr, <i>OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten</i>.
    Universität Paderborn, 2017.
  mla: Knorr, Christoph. <i>OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten</i>.
    Universität Paderborn, 2017.
  short: C. Knorr, OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten,
    Universität Paderborn, 2017.
date_created: 2017-10-17T12:41:05Z
date_updated: 2022-01-06T07:03:36Z
department:
- _id: '78'
language:
- iso: ger
project:
- _id: '1'
  name: SFB 901
- _id: '14'
  name: SFB 901 - Subprojekt C2
- _id: '4'
  name: SFB 901 - Project Area C
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Achim
  full_name: Lösch, Achim
  id: '43646'
  last_name: Lösch
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
title: OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten
type: mastersthesis
user_id: '477'
year: '2017'
...
---
_id: '3364'
author:
- first_name: Christoph
  full_name: Knorr, Christoph
  last_name: Knorr
citation:
  ama: Knorr C. <i>Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten</i>.
    Universität Paderborn; 2015.
  apa: Knorr, C. (2015). <i>Evaluation von Bildverarbeitungsalgorithmen in heterogenen
    Rechenknoten</i>. Universität Paderborn.
  bibtex: '@book{Knorr_2015, title={Evaluation von Bildverarbeitungsalgorithmen in
    heterogenen Rechenknoten}, publisher={Universität Paderborn}, author={Knorr, Christoph},
    year={2015} }'
  chicago: Knorr, Christoph. <i>Evaluation von Bildverarbeitungsalgorithmen in heterogenen
    Rechenknoten</i>. Universität Paderborn, 2015.
  ieee: C. Knorr, <i>Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten</i>.
    Universität Paderborn, 2015.
  mla: Knorr, Christoph. <i>Evaluation von Bildverarbeitungsalgorithmen in heterogenen
    Rechenknoten</i>. Universität Paderborn, 2015.
  short: C. Knorr, Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten,
    Universität Paderborn, 2015.
date_created: 2018-06-26T14:06:07Z
date_updated: 2022-01-06T06:59:13Z
department:
- _id: '78'
language:
- iso: ger
project:
- _id: '14'
  name: SFB 901 - Subproject C2
- _id: '1'
  name: SFB 901
- _id: '4'
  name: SFB 901 - Project Area C
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Achim
  full_name: Lösch, Achim
  id: '43646'
  last_name: Lösch
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
title: Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten
type: bachelorsthesis
user_id: '477'
year: '2015'
...
---
_id: '10701'
author:
- first_name: Benjamin
  full_name: Koch, Benjamin
  last_name: Koch
citation:
  ama: Koch B. <i>Hardware Acceleration of Mechatronic Controllers on a Zynq Platform
    FPGA</i>. Paderborn University; 2014.
  apa: Koch, B. (2014). <i>Hardware Acceleration of Mechatronic Controllers on a Zynq
    Platform FPGA</i>. Paderborn University.
  bibtex: '@book{Koch_2014, title={Hardware Acceleration of Mechatronic Controllers
    on a Zynq Platform FPGA}, publisher={Paderborn University}, author={Koch, Benjamin},
    year={2014} }'
  chicago: Koch, Benjamin. <i>Hardware Acceleration of Mechatronic Controllers on
    a Zynq Platform FPGA</i>. Paderborn University, 2014.
  ieee: B. Koch, <i>Hardware Acceleration of Mechatronic Controllers on a Zynq Platform
    FPGA</i>. Paderborn University, 2014.
  mla: Koch, Benjamin. <i>Hardware Acceleration of Mechatronic Controllers on a Zynq
    Platform FPGA</i>. Paderborn University, 2014.
  short: B. Koch, Hardware Acceleration of Mechatronic Controllers on a Zynq Platform
    FPGA, Paderborn University, 2014.
date_created: 2019-07-10T11:38:27Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
title: Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA
type: mastersthesis
user_id: '3118'
year: '2014'
...