---
_id: '14546'
author:
- first_name: Tim
  full_name: Hansmeier, Tim
  id: '49992'
  last_name: Hansmeier
  orcid: 0000-0003-1377-3339
citation:
  ama: Hansmeier T. <i>Autonomous Operation of High-Performance Compute Nodes through
    Self-Awareness and Learning Classifiers</i>. Universität Paderborn; 2019.
  apa: Hansmeier, T. (2019). <i>Autonomous Operation of High-Performance Compute Nodes
    through Self-Awareness and Learning Classifiers</i>. Universität Paderborn.
  bibtex: '@book{Hansmeier_2019, title={Autonomous Operation of High-Performance Compute
    Nodes through Self-Awareness and Learning Classifiers}, publisher={Universität
    Paderborn}, author={Hansmeier, Tim}, year={2019} }'
  chicago: Hansmeier, Tim. <i>Autonomous Operation of High-Performance Compute Nodes
    through Self-Awareness and Learning Classifiers</i>. Universität Paderborn, 2019.
  ieee: T. Hansmeier, <i>Autonomous Operation of High-Performance Compute Nodes through
    Self-Awareness and Learning Classifiers</i>. Universität Paderborn, 2019.
  mla: Hansmeier, Tim. <i>Autonomous Operation of High-Performance Compute Nodes through
    Self-Awareness and Learning Classifiers</i>. Universität Paderborn, 2019.
  short: T. Hansmeier, Autonomous Operation of High-Performance Compute Nodes through
    Self-Awareness and Learning Classifiers, Universität Paderborn, 2019.
date_created: 2019-11-05T14:32:46Z
date_updated: 2022-01-06T06:52:02Z
department:
- _id: '78'
- _id: '34'
- _id: '7'
language:
- iso: eng
project:
- _id: '14'
  name: SFB 901 - Subproject C2
- _id: '4'
  name: SFB 901 - Project Area C
- _id: '1'
  name: SFB 901
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
title: Autonomous Operation of High-Performance Compute Nodes through Self-Awareness
  and Learning Classifiers
type: mastersthesis
user_id: '477'
year: '2019'
...
---
_id: '15874'
author:
- first_name: Christian
  full_name: Lienen, Christian
  id: '60323'
  last_name: Lienen
citation:
  ama: Lienen C. <i>Implementing a Real-Time System on a Platform FPGA Operated with
    ReconOS</i>. Universität Paderborn
  apa: Lienen, C. (n.d.). <i>Implementing a Real-time System on a Platform FPGA operated
    with ReconOS</i>. Universität Paderborn.
  bibtex: '@book{Lienen, title={Implementing a Real-time System on a Platform FPGA
    operated with ReconOS}, publisher={Universität Paderborn}, author={Lienen, Christian}
    }'
  chicago: Lienen, Christian. <i>Implementing a Real-Time System on a Platform FPGA
    Operated with ReconOS</i>. Universität Paderborn, n.d.
  ieee: C. Lienen, <i>Implementing a Real-time System on a Platform FPGA operated
    with ReconOS</i>. Universität Paderborn.
  mla: Lienen, Christian. <i>Implementing a Real-Time System on a Platform FPGA Operated
    with ReconOS</i>. Universität Paderborn.
  short: C. Lienen, Implementing a Real-Time System on a Platform FPGA Operated with
    ReconOS, Universität Paderborn, n.d.
date_created: 2020-02-11T10:22:06Z
date_updated: 2023-07-31T11:58:50Z
ddc:
- '004'
department:
- _id: '78'
file:
- access_level: open_access
  content_type: application/pdf
  creator: clienen
  date_created: 2020-07-01T11:46:49Z
  date_updated: 2021-02-13T16:46:58Z
  file_id: '17351'
  file_name: thesis_main.pdf
  file_size: 5920668
  relation: main_file
file_date_updated: 2021-02-13T16:46:58Z
has_accepted_license: '1'
language:
- iso: eng
oa: '1'
project:
- _id: '83'
  name: 'SFB 901 - T1: SFB 901 -Subproject T1'
- _id: '82'
  name: 'SFB 901 - T: SFB 901 - Project Area T'
- _id: '1'
  grant_number: '160364472'
  name: 'SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen
    in dynamischen Märkten '
publication_status: submitted
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Lennart
  full_name: Clausing, Lennart
  id: '74287'
  last_name: Clausing
  orcid: 0000-0003-3789-6034
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Sybille
  full_name: Hellebrand, Sybille
  id: '209'
  last_name: Hellebrand
  orcid: 0000-0002-3717-3939
title: Implementing a Real-time System on a Platform FPGA operated with ReconOS
type: mastersthesis
user_id: '60323'
year: '2019'
...
---
_id: '3365'
author:
- first_name: Jan-Philip
  full_name: Schnuer, Jan-Philip
  last_name: Schnuer
citation:
  ama: Schnuer J-P. <i>Static Scheduling Algorithms for Heterogeneous Compute Nodes</i>.
    Universität Paderborn; 2018.
  apa: Schnuer, J.-P. (2018). <i>Static Scheduling Algorithms for Heterogeneous Compute
    Nodes</i>. Universität Paderborn.
  bibtex: '@book{Schnuer_2018, title={Static Scheduling Algorithms for Heterogeneous
    Compute Nodes}, publisher={Universität Paderborn}, author={Schnuer, Jan-Philip},
    year={2018} }'
  chicago: Schnuer, Jan-Philip. <i>Static Scheduling Algorithms for Heterogeneous
    Compute Nodes</i>. Universität Paderborn, 2018.
  ieee: J.-P. Schnuer, <i>Static Scheduling Algorithms for Heterogeneous Compute Nodes</i>.
    Universität Paderborn, 2018.
  mla: Schnuer, Jan-Philip. <i>Static Scheduling Algorithms for Heterogeneous Compute
    Nodes</i>. Universität Paderborn, 2018.
  short: J.-P. Schnuer, Static Scheduling Algorithms for Heterogeneous Compute Nodes,
    Universität Paderborn, 2018.
date_created: 2018-06-26T14:10:18Z
date_updated: 2022-01-06T06:59:13Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '14'
  name: SFB 901 - Subproject C2
- _id: '1'
  name: SFB 901
- _id: '4'
  name: SFB 901 - Project Area C
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Achim
  full_name: Lösch, Achim
  id: '43646'
  last_name: Lösch
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
title: Static Scheduling Algorithms for Heterogeneous Compute Nodes
type: bachelorsthesis
user_id: '477'
year: '2018'
...
---
_id: '3366'
author:
- first_name: Marcel
  full_name: Croce, Marcel
  last_name: Croce
citation:
  ama: Croce M. <i>Evaluation of OpenCL-Based Compilation for FPGAs</i>. Universität
    Paderborn; 2018.
  apa: Croce, M. (2018). <i>Evaluation of OpenCL-based Compilation for FPGAs</i>.
    Universität Paderborn.
  bibtex: '@book{Croce_2018, title={Evaluation of OpenCL-based Compilation for FPGAs},
    publisher={Universität Paderborn}, author={Croce, Marcel}, year={2018} }'
  chicago: Croce, Marcel. <i>Evaluation of OpenCL-Based Compilation for FPGAs</i>.
    Universität Paderborn, 2018.
  ieee: M. Croce, <i>Evaluation of OpenCL-based Compilation for FPGAs</i>. Universität
    Paderborn, 2018.
  mla: Croce, Marcel. <i>Evaluation of OpenCL-Based Compilation for FPGAs</i>. Universität
    Paderborn, 2018.
  short: M. Croce, Evaluation of OpenCL-Based Compilation for FPGAs, Universität Paderborn,
    2018.
date_created: 2018-06-26T14:12:00Z
date_updated: 2022-01-06T06:59:13Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '14'
  name: SFB 901 - Subproject C2
- _id: '1'
  name: SFB 901
- _id: '4'
  name: SFB 901 - Project Area C
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Achim
  full_name: Lösch, Achim
  id: '43646'
  last_name: Lösch
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
title: Evaluation of OpenCL-based Compilation for FPGAs
type: bachelorsthesis
user_id: '477'
year: '2018'
...
---
_id: '3720'
abstract:
- lang: eng
  text: Traditional cache design uses a consolidated block of memory address bits
    to index a cache set, equivalent to the use of modulo functions. While this module-based
    mapping scheme is widely used in contemporary cache structures due to the simplicity
    of its hardware design and its good performance for sequences of consecutive addresses,
    its use may not be satisfactory for a variety of application domains having different
    characteristics.This thesis presents a new type of cache mapping scheme, motivated
    by programmable capabilities combined with Nature-inspired optimization of reconfigurable
    hardware. This research has focussed on an FPGA-based evolvable cache structure
    of the first level cache in a multi-core processor architecture, able to dynamically
    change cache indexing. To solve the challenge of reconfigurable cache mappings,
    a programmable Boolean circuit based on a combination of Look-up Table (LUT) memory
    elements is proposed. Focusing on optimization aspects at the system level, a
    Performance Measurement Infrastructure is introduced that is able to monitor the
    underlying microarchitectural metrics, and an adaptive evaluation strategy is
    presented that leverages on Evolutionary Algorithms, that is not only capable
    of evolving application-specific address-to-cache-index mappings for level one
    split caches but also of reducing optimization times. Putting this all together
    and prototyping in an FPGA for a LEON3/Linux-based multi-core processor, the creation
    of a system architecture reduces cache misses and improves performance over the
    use of conventional caches.
- lang: ger
  text: Traditionelle Cachedesigns verwenden konsolidierte Blöcke von Speicheradressbits
    um einen Cachesatz zu indizieren, vergleichbar mit der Anwendung einer Modulofunktion.
    Obwohl dieses modulobasierte Abbildungsschema in heutigen Cachestrukturen weit
    verbreitet ist, vor allem wegen seiner einfachen Anforderungen an das Hardwaredesign
    und seiner Effizienz für die Indizierung eufeinanderfolgender Speicheradressen,
    kann seine Verwendung für eine Vielzahl von Anwendungsdomänen mit unterschiedlichen
    Charakteristiken zu suboptimalen Ergebnissen führen. Diese Dissertation präsentiert
    einen neuen Typ von Cacheabbildungsschema, motiviert durch die Kombination programmierbarer
    Ressourcen mit der naturinspirierten Optimierung rekonfigurierbarer Hardware.
    Im Fokus dieser Forschung steht eine FPGA-basierte Cachestruktur für den first
    level Cache einer Mehrkernprozessorarchitektur, welche die Cacheindizierung dynamisch
    ändern kann. Um die Herausforderung rekonfigurierbarer Cacheabbildungen zu lösen,
    wird eine reprogrammierbare Boolesche Schaltung eingeführt, die auf Look-up Table
    (LUT) Speicherelementen basiert. Weiterhin wird eine Infrastruktur zur Effizienzmessung
    eingeführt, welche die zugrundeliege Mikroarchitektur überwachen kann, sowie eine
    adaptive Evaluationsstrategie präsentiert, die evolutionäre Algorithmen wirksam
    einsetzt, und die nicht nur anwendungsspezifische Abbildungen von Speicheradressen
    zu Cacheindizes für level one Caches evolvieren sondern dabei auch die Optimierungszeiten
    reduzieren kann. All diese Aspekte zusammen in einer prototypischen Implementierung
    auf einem FPGA für einen LEON3/Linux-basierten Mehrkernprozessor zeigen, dass
    evolvierbare Cacheabbildungsfunktionen Cache Misses reduzieren, sowie die Effizienz
    im Vergleich zu konventionellen Caches erhöhen können.
author:
- first_name: Nam
  full_name: Ho, Nam
  last_name: Ho
citation:
  ama: 'Ho N. <i>FPGA-Based Reconfigurable Cache Mapping Schemes: Design and Optimization</i>.
    Universität Paderborn; 2018. doi:<a href="https://doi.org/10.17619/UNIPB/1-376">10.17619/UNIPB/1-376</a>'
  apa: 'Ho, N. (2018). <i>FPGA-based Reconfigurable Cache Mapping Schemes: Design
    and Optimization</i>. Universität Paderborn. <a href="https://doi.org/10.17619/UNIPB/1-376">https://doi.org/10.17619/UNIPB/1-376</a>'
  bibtex: '@book{Ho_2018, title={FPGA-based Reconfigurable Cache Mapping Schemes:
    Design and Optimization}, DOI={<a href="https://doi.org/10.17619/UNIPB/1-376">10.17619/UNIPB/1-376</a>},
    publisher={Universität Paderborn}, author={Ho, Nam}, year={2018} }'
  chicago: 'Ho, Nam. <i>FPGA-Based Reconfigurable Cache Mapping Schemes: Design and
    Optimization</i>. Universität Paderborn, 2018. <a href="https://doi.org/10.17619/UNIPB/1-376">https://doi.org/10.17619/UNIPB/1-376</a>.'
  ieee: 'N. Ho, <i>FPGA-based Reconfigurable Cache Mapping Schemes: Design and Optimization</i>.
    Universität Paderborn, 2018.'
  mla: 'Ho, Nam. <i>FPGA-Based Reconfigurable Cache Mapping Schemes: Design and Optimization</i>.
    Universität Paderborn, 2018, doi:<a href="https://doi.org/10.17619/UNIPB/1-376">10.17619/UNIPB/1-376</a>.'
  short: 'N. Ho, FPGA-Based Reconfigurable Cache Mapping Schemes: Design and Optimization,
    Universität Paderborn, 2018.'
date_created: 2018-07-27T06:41:13Z
date_updated: 2022-01-06T06:59:31Z
department:
- _id: '78'
doi: 10.17619/UNIPB/1-376
language:
- iso: eng
page: '139'
project:
- _id: '12'
  name: SFB 901 - Subproject B4
- _id: '1'
  name: SFB 901
- _id: '3'
  name: SFB 901 - Project Area B
publication_status: published
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Paul
  full_name: Kaufmann, Paul
  last_name: Kaufmann
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
title: 'FPGA-based Reconfigurable Cache Mapping Schemes: Design and Optimization'
type: dissertation
user_id: '477'
year: '2018'
...
---
_id: '3580'
author:
- first_name: Tim
  full_name: Hansmeier, Tim
  id: '49992'
  last_name: Hansmeier
  orcid: 0000-0003-1377-3339
citation:
  ama: Hansmeier T. <i>An FPGA Accelerator for Checking Resolution Proofs</i>. Universität
    Paderborn; 2017.
  apa: Hansmeier, T. (2017). <i>An FPGA Accelerator for Checking Resolution Proofs</i>.
    Universität Paderborn.
  bibtex: '@book{Hansmeier_2017, title={An FPGA Accelerator for Checking Resolution
    Proofs}, publisher={Universität Paderborn}, author={Hansmeier, Tim}, year={2017}
    }'
  chicago: Hansmeier, Tim. <i>An FPGA Accelerator for Checking Resolution Proofs</i>.
    Universität Paderborn, 2017.
  ieee: T. Hansmeier, <i>An FPGA Accelerator for Checking Resolution Proofs</i>. Universität
    Paderborn, 2017.
  mla: Hansmeier, Tim. <i>An FPGA Accelerator for Checking Resolution Proofs</i>.
    Universität Paderborn, 2017.
  short: T. Hansmeier, An FPGA Accelerator for Checking Resolution Proofs, Universität
    Paderborn, 2017.
date_created: 2018-07-20T13:44:34Z
date_updated: 2022-01-06T06:59:25Z
department:
- _id: '78'
- _id: '34'
- _id: '7'
language:
- iso: eng
project:
- _id: '1'
  name: SFB 901
- _id: '3'
  name: SFB 901 - Project Area B
- _id: '12'
  name: SFB 901 - Subproject B4
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
title: An FPGA Accelerator for Checking Resolution Proofs
type: bachelorsthesis
user_id: '3118'
year: '2017'
...
---
_id: '1157'
author:
- first_name: Linus Matthias
  full_name: Witschen, Linus Matthias
  id: '49051'
  last_name: Witschen
citation:
  ama: Witschen LM. <i>A Framework for the Synthesis of Approximate Circuits</i>.
    Universität Paderborn; 2017.
  apa: Witschen, L. M. (2017). <i>A Framework for the Synthesis of Approximate Circuits</i>.
    Universität Paderborn.
  bibtex: '@book{Witschen_2017, title={A Framework for the Synthesis of Approximate
    Circuits}, publisher={Universität Paderborn}, author={Witschen, Linus Matthias},
    year={2017} }'
  chicago: Witschen, Linus Matthias. <i>A Framework for the Synthesis of Approximate
    Circuits</i>. Universität Paderborn, 2017.
  ieee: L. M. Witschen, <i>A Framework for the Synthesis of Approximate Circuits</i>.
    Universität Paderborn, 2017.
  mla: Witschen, Linus Matthias. <i>A Framework for the Synthesis of Approximate Circuits</i>.
    Universität Paderborn, 2017.
  short: L.M. Witschen, A Framework for the Synthesis of Approximate Circuits, Universität
    Paderborn, 2017.
date_created: 2018-02-01T14:21:19Z
date_updated: 2022-01-06T06:51:03Z
department:
- _id: '78'
- _id: '7'
language:
- iso: eng
project:
- _id: '1'
  name: SFB 901
- _id: '3'
  name: SFB 901 - Project Area B
- _id: '12'
  name: SFB 901 - Subproject B4
- _id: '52'
  name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Tobias
  full_name: Wiersema, Tobias
  id: '3118'
  last_name: Wiersema
title: A Framework for the Synthesis of Approximate Circuits
type: mastersthesis
user_id: '477'
year: '2017'
...
---
_id: '74'
author:
- first_name: Christoph
  full_name: Knorr, Christoph
  last_name: Knorr
citation:
  ama: Knorr C. <i>OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten</i>.
    Universität Paderborn; 2017.
  apa: Knorr, C. (2017). <i>OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten</i>.
    Universität Paderborn.
  bibtex: '@book{Knorr_2017, title={OpenCL-basierte Videoverarbeitung auf heterogenen
    Rechenknoten}, publisher={Universität Paderborn}, author={Knorr, Christoph}, year={2017}
    }'
  chicago: Knorr, Christoph. <i>OpenCL-basierte Videoverarbeitung auf heterogenen
    Rechenknoten</i>. Universität Paderborn, 2017.
  ieee: C. Knorr, <i>OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten</i>.
    Universität Paderborn, 2017.
  mla: Knorr, Christoph. <i>OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten</i>.
    Universität Paderborn, 2017.
  short: C. Knorr, OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten,
    Universität Paderborn, 2017.
date_created: 2017-10-17T12:41:05Z
date_updated: 2022-01-06T07:03:36Z
department:
- _id: '78'
language:
- iso: ger
project:
- _id: '1'
  name: SFB 901
- _id: '14'
  name: SFB 901 - Subprojekt C2
- _id: '4'
  name: SFB 901 - Project Area C
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Achim
  full_name: Lösch, Achim
  id: '43646'
  last_name: Lösch
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
title: OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten
type: mastersthesis
user_id: '477'
year: '2017'
...
---
_id: '3364'
author:
- first_name: Christoph
  full_name: Knorr, Christoph
  last_name: Knorr
citation:
  ama: Knorr C. <i>Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten</i>.
    Universität Paderborn; 2015.
  apa: Knorr, C. (2015). <i>Evaluation von Bildverarbeitungsalgorithmen in heterogenen
    Rechenknoten</i>. Universität Paderborn.
  bibtex: '@book{Knorr_2015, title={Evaluation von Bildverarbeitungsalgorithmen in
    heterogenen Rechenknoten}, publisher={Universität Paderborn}, author={Knorr, Christoph},
    year={2015} }'
  chicago: Knorr, Christoph. <i>Evaluation von Bildverarbeitungsalgorithmen in heterogenen
    Rechenknoten</i>. Universität Paderborn, 2015.
  ieee: C. Knorr, <i>Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten</i>.
    Universität Paderborn, 2015.
  mla: Knorr, Christoph. <i>Evaluation von Bildverarbeitungsalgorithmen in heterogenen
    Rechenknoten</i>. Universität Paderborn, 2015.
  short: C. Knorr, Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten,
    Universität Paderborn, 2015.
date_created: 2018-06-26T14:06:07Z
date_updated: 2022-01-06T06:59:13Z
department:
- _id: '78'
language:
- iso: ger
project:
- _id: '14'
  name: SFB 901 - Subproject C2
- _id: '1'
  name: SFB 901
- _id: '4'
  name: SFB 901 - Project Area C
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Achim
  full_name: Lösch, Achim
  id: '43646'
  last_name: Lösch
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
title: Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten
type: bachelorsthesis
user_id: '477'
year: '2015'
...
---
_id: '10701'
author:
- first_name: Benjamin
  full_name: Koch, Benjamin
  last_name: Koch
citation:
  ama: Koch B. <i>Hardware Acceleration of Mechatronic Controllers on a Zynq Platform
    FPGA</i>. Paderborn University; 2014.
  apa: Koch, B. (2014). <i>Hardware Acceleration of Mechatronic Controllers on a Zynq
    Platform FPGA</i>. Paderborn University.
  bibtex: '@book{Koch_2014, title={Hardware Acceleration of Mechatronic Controllers
    on a Zynq Platform FPGA}, publisher={Paderborn University}, author={Koch, Benjamin},
    year={2014} }'
  chicago: Koch, Benjamin. <i>Hardware Acceleration of Mechatronic Controllers on
    a Zynq Platform FPGA</i>. Paderborn University, 2014.
  ieee: B. Koch, <i>Hardware Acceleration of Mechatronic Controllers on a Zynq Platform
    FPGA</i>. Paderborn University, 2014.
  mla: Koch, Benjamin. <i>Hardware Acceleration of Mechatronic Controllers on a Zynq
    Platform FPGA</i>. Paderborn University, 2014.
  short: B. Koch, Hardware Acceleration of Mechatronic Controllers on a Zynq Platform
    FPGA, Paderborn University, 2014.
date_created: 2019-07-10T11:38:27Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
title: Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA
type: mastersthesis
user_id: '3118'
year: '2014'
...
---
_id: '10733'
abstract:
- lang: eng
  text: "Monte-Carlo Tree Search (MCTS) is a class of simulation-based search algorithms.
    It brought about great success in the past few years regarding the evaluation
    of deterministic two-player games such as the Asian board game Go.\r\n\r\nIn this
    thesis, we present a parallelization of the most popular MCTS variant for large
    HPC compute clusters that efficiently shares a single game tree representation
    in a distributed memory environment and scales up to 128 compute nodes and 2048
    cores. It is hereby one of the most powerful MCTS parallelizations to date.\r\n\r\nIn
    order to measure the impact of our parallelization on the search quality and remain
    comparable to the most advanced MCTS implementations to date, we implemented it
    in a state-of-the-art Go engine Gomorra, making it competitive with the strongest
    Go programs in the world.\r\n\r\nWe further present an empirical comparison of
    different Bayesian ranking systems when being used for predicting expert moves
    for the game of Go and introduce a novel technique for automated detection and
    analysis of evaluation uncertainties that show up during MCTS searches."
author:
- first_name: Lars
  full_name: Schäfers, Lars
  last_name: Schäfers
citation:
  ama: 'Schäfers L. <i>Parallel Monte-Carlo Tree Search for HPC Systems and Its Application
    to Computer Go</i>. Berlin: Logos Verlag Berlin GmbH; 2014.'
  apa: 'Schäfers, L. (2014). <i>Parallel Monte-Carlo Tree Search for HPC Systems and
    its Application to Computer Go</i>. Berlin: Logos Verlag Berlin GmbH.'
  bibtex: '@book{Schäfers_2014, place={Berlin}, title={Parallel Monte-Carlo Tree Search
    for HPC Systems and its Application to Computer Go}, publisher={Logos Verlag Berlin
    GmbH}, author={Schäfers, Lars}, year={2014} }'
  chicago: 'Schäfers, Lars. <i>Parallel Monte-Carlo Tree Search for HPC Systems and
    Its Application to Computer Go</i>. Berlin: Logos Verlag Berlin GmbH, 2014.'
  ieee: 'L. Schäfers, <i>Parallel Monte-Carlo Tree Search for HPC Systems and its
    Application to Computer Go</i>. Berlin: Logos Verlag Berlin GmbH, 2014.'
  mla: Schäfers, Lars. <i>Parallel Monte-Carlo Tree Search for HPC Systems and Its
    Application to Computer Go</i>. Logos Verlag Berlin GmbH, 2014.
  short: L. Schäfers, Parallel Monte-Carlo Tree Search for HPC Systems and Its Application
    to Computer Go, Logos Verlag Berlin GmbH, Berlin, 2014.
date_created: 2019-07-10T11:58:06Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
page: '133'
place: Berlin
publication_identifier:
  isbn:
  - 978-3-8325-3748-7
publication_status: published
publisher: Logos Verlag Berlin GmbH
status: public
supervisor:
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
title: Parallel Monte-Carlo Tree Search for HPC Systems and its Application to Computer
  Go
type: dissertation
user_id: '3118'
year: '2014'
...
---
_id: '10744'
author:
- first_name: Sebastian
  full_name: Surmund, Sebastian
  last_name: Surmund
citation:
  ama: Surmund S. <i>Multithreaded Parallelization of Mechatronic Controllers on a
    Zynq Platform FPGA</i>. Paderborn University; 2014.
  apa: Surmund, S. (2014). <i>Multithreaded Parallelization of Mechatronic Controllers
    on a Zynq Platform FPGA</i>. Paderborn University.
  bibtex: '@book{Surmund_2014, title={Multithreaded Parallelization of Mechatronic
    Controllers on a Zynq Platform FPGA}, publisher={Paderborn University}, author={Surmund,
    Sebastian}, year={2014} }'
  chicago: Surmund, Sebastian. <i>Multithreaded Parallelization of Mechatronic Controllers
    on a Zynq Platform FPGA</i>. Paderborn University, 2014.
  ieee: S. Surmund, <i>Multithreaded Parallelization of Mechatronic Controllers on
    a Zynq Platform FPGA</i>. Paderborn University, 2014.
  mla: Surmund, Sebastian. <i>Multithreaded Parallelization of Mechatronic Controllers
    on a Zynq Platform FPGA</i>. Paderborn University, 2014.
  short: S. Surmund, Multithreaded Parallelization of Mechatronic Controllers on a
    Zynq Platform FPGA, Paderborn University, 2014.
date_created: 2019-07-10T12:00:45Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
title: Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform
  FPGA
type: mastersthesis
user_id: '3118'
year: '2014'
...
---
_id: '11619'
abstract:
- lang: eng
  text: "Reconfigurable circuit devices have opened up a fundamentally new way of
    creating adaptable systems. Combined with artificial evolution, reconfigurable
    circuits allow an elegant adaptation approach to compensating for changes in the
    distribution of input data, computational resource errors, and variations in resource
    requirements. Referred to as ``Evolvable Hardware'' (EHW), this paradigm has yielded
    astonishing results for traditional engineering challenges and has discovered
    intriguing design principles, which have not yet been seen in conventional engineering.\r\n\r\nIn
    this thesis, we present new and fundamental work on Evolvable Hardware motivated
    by the insight that Evolvable Hardware needs to compensate for events with different
    change rates. To solve the challenge of different adaptation speeds, we propose
    a unified adaptation approach based on multi-objective evolution, evolving and
    propagating candidate solutions that are diverse in objectives that may experience
    radical changes.\r\n\r\nFocusing on algorithmic aspects, we enable Cartesian Genetic
    Programming (CGP) model, which we are using to encode Boolean circuits, for multi-objective
    optimization by introducing a meaningful recombination operator. We improve the
    scalability of CGP by objectives scaling, periodization of local- and global-search
    algorithms, and the automatic acquisition and reuse of subfunctions using age-
    and cone-based techniques. We validate our methods on the applications of adaptation
    of hardware classifiers to resource changes, recognition of muscular signals for
    prosthesis control and optimization of processor caches."
author:
- first_name: Paul
  full_name: Kaufmann, Paul
  last_name: Kaufmann
citation:
  ama: 'Kaufmann P. <i>Adapting Hardware Systems by Means of Multi-Objective Evolution</i>.
    Berlin: Logos Verlag Berlin GmbH; 2013.'
  apa: 'Kaufmann, P. (2013). <i>Adapting Hardware Systems by Means of Multi-Objective
    Evolution</i>. Berlin: Logos Verlag Berlin GmbH.'
  bibtex: '@book{Kaufmann_2013, place={Berlin}, title={Adapting Hardware Systems by
    Means of Multi-Objective Evolution}, publisher={Logos Verlag Berlin GmbH}, author={Kaufmann,
    Paul}, year={2013} }'
  chicago: 'Kaufmann, Paul. <i>Adapting Hardware Systems by Means of Multi-Objective
    Evolution</i>. Berlin: Logos Verlag Berlin GmbH, 2013.'
  ieee: 'P. Kaufmann, <i>Adapting Hardware Systems by Means of Multi-Objective Evolution</i>.
    Berlin: Logos Verlag Berlin GmbH, 2013.'
  mla: Kaufmann, Paul. <i>Adapting Hardware Systems by Means of Multi-Objective Evolution</i>.
    Logos Verlag Berlin GmbH, 2013.
  short: P. Kaufmann, Adapting Hardware Systems by Means of Multi-Objective Evolution,
    Logos Verlag Berlin GmbH, Berlin, 2013.
date_created: 2019-07-11T11:51:51Z
date_updated: 2022-01-06T06:51:04Z
department:
- _id: '78'
language:
- iso: eng
page: '249'
place: Berlin
publication_identifier:
  isbn:
  - 978-3-8325-3530-8
publication_status: published
publisher: Logos Verlag Berlin GmbH
status: public
supervisor:
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
title: Adapting Hardware Systems by Means of Multi-Objective Evolution
type: dissertation
user_id: '3118'
year: '2013'
...
---
_id: '501'
abstract:
- lang: eng
  text: 'Handling run-time dynamics on embedded system-on-chip architectures has become
    more challenging over the years. On the one hand, the impact of workload and physical
    dynamics on the system behavior has dramatically increased. On the other hand,
    embedded architectures have become more complex as they have evolved from single-processor
    systems over multi-processor systems to hybrid multi-core platforms.Static design-time
    techniques no longer provide suitable solutions to deal with the run-time dynamics
    of today''s embedded systems. Therefore, system designers have to apply run-time
    solutions, which have hardly been investigated for hybrid multi-core platforms.In
    this thesis, we present fundamental work in the new area of run-time management
    on hybrid multi-core platforms. We propose a novel architecture, a self-adaptive
    hybrid multi-core system, that combines heterogeneous processors, reconfigurable
    hardware cores, and monitoring cores on a single chip. Using self-adaptation on
    thread-level, our hybrid multi-core systems can effectively perform performance
    and thermal management autonomously at run-time. '
author:
- first_name: Markus
  full_name: Happe, Markus
  last_name: Happe
citation:
  ama: 'Happe M. <i>Performance and Thermal Management on Self-Adaptive Hybrid Multi-Cores</i>.
    Berlin: Logos Verlag Berlin GmbH; 2013.'
  apa: 'Happe, M. (2013). <i>Performance and thermal management on self-adaptive hybrid
    multi-cores</i>. Berlin: Logos Verlag Berlin GmbH.'
  bibtex: '@book{Happe_2013, place={Berlin}, title={Performance and thermal management
    on self-adaptive hybrid multi-cores}, publisher={Logos Verlag Berlin GmbH}, author={Happe,
    Markus}, year={2013} }'
  chicago: 'Happe, Markus. <i>Performance and Thermal Management on Self-Adaptive
    Hybrid Multi-Cores</i>. Berlin: Logos Verlag Berlin GmbH, 2013.'
  ieee: 'M. Happe, <i>Performance and thermal management on self-adaptive hybrid multi-cores</i>.
    Berlin: Logos Verlag Berlin GmbH, 2013.'
  mla: Happe, Markus. <i>Performance and Thermal Management on Self-Adaptive Hybrid
    Multi-Cores</i>. Logos Verlag Berlin GmbH, 2013.
  short: M. Happe, Performance and Thermal Management on Self-Adaptive Hybrid Multi-Cores,
    Logos Verlag Berlin GmbH, Berlin, 2013.
date_created: 2017-10-17T12:42:30Z
date_updated: 2022-01-06T07:01:34Z
department:
- _id: '78'
language:
- iso: eng
page: '220'
place: Berlin
project:
- _id: '14'
  name: SFB 901 - Subprojekt C2
- _id: '1'
  name: SFB 901
- _id: '4'
  name: SFB 901 - Project Area C
publication_identifier:
  isbn:
  - 978-3-8325-3425-7
publication_status: published
publisher: Logos Verlag Berlin GmbH
related_material:
  link:
  - relation: confirmation
    url: https://www.logos-verlag.de/cgi-bin/engbuchmid?isbn=3425&lng=deu&id=
status: public
supervisor:
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
title: Performance and thermal management on self-adaptive hybrid multi-cores
type: dissertation
user_id: '477'
year: '2013'
...
---
_id: '586'
abstract:
- lang: eng
  text: FPGAs, systems on chip and embedded systems are nowadays irreplaceable. They
    combine the computational power of application specific hardware with software-like
    flexibility. At runtime, they can adjust their functionality by downloading new
    hardware modules and integrating their functionality. Due to their growing capabilities,
    the demands made to reconfigurable hardware grow. Their deployment in increasingly
    security critical scenarios requires new ways of enforcing security since a failure
    in security has severe consequences. Aside from financial losses, a loss of human
    life and risks to national security are possible. With this work I present the
    novel and groundbreaking concept of proof-carrying hardware. It is a method for
    the verification of properties of hardware modules to guarantee security for a
    target platform at runtime. The producer of a hardware module delivers based on
    the consumer's safety policy a safety proof in combination with the reconfiguration
    bitstream. The extensive computation of a proof is a contrast to the comparatively
    undemanding checking of the proof. I present a prototype based on open-source
    tools and an abstract FPGA architecture and bitstream format. The proof of the
    usability of proof-carrying hardware provides the evaluation of the prototype
    with the exemplary application of securing combinational and bounded sequential
    equivalence of reference monitor modules for memory safety.
- lang: ger
  text: FPGAs, System on Chips und eingebettete Systeme sind heutzutage kaum mehr
    wegzudenken. Sie kombinieren die Rechenleistung von spezialisierter Hardware mit
    einer Software-ähnlichen Flexibilität. Zur Laufzeit können sie ihre Funktionalität
    anpassen, indem sie online neue Hardware Module beziehen und deren Funktionalität
    integrieren. Mit der Leistung wachsen auch die Anforderungen an rekonfigurierbare
    Hardware. Ihr Einsatz in immer sicherheitskritischeren Szenarien erfordert neue
    Wege um Sicherheit zu gewährleisten, da ein Versagen der Sicherheit gravierende
    Folgen mit sich bringt. Neben finanziellen Verlusten sind auch der Verlust von
    Menschenleben oder Einbußen in der nationalen Sicherheit denkbar. In dieser Arbeit
    stelle ich das neue und wegweisende Konzept der beweistragenden Hardware vor.
    Es ist eine Methode zur Verifizierung von Eigenschaften von Hardware Modulen um
    die Sicherheit der Zielplatformen zur Laufzeit zu garantieren. Der Produzent eines
    Hardware Moduls liefert, basierend auf den Sicherheitsbestimmungen des Konsumenten,
    einen Beweis der Sicherheit mit dem Rekonfigurierungsbitstrom. Die aufwendige
    Berechnung des Beweises steht im Kontrast zu der vergleichsweise unaufwendigen
    Überprüfung durch den Konsumenten. Ich präsentiere einen Prototypen basierend
    auf Open Source Werkzeugen und einer eigenen abstrakten FPGA Architektur samt
    Bitstromformat. Den Nachweis über die Nutzbarkeit von beweistragender Hardware
    erbringt die Evaluierung des Prototypen zur beispielhaften Anwendung der Sicherung
    von kombinatorischer und begrenzt sequenzieller Äquivalenz von Referenzmonitor-Modulen
    zur Speichersicherheit.
author:
- first_name: Stephanie
  full_name: Drzevitzky, Stephanie
  last_name: Drzevitzky
citation:
  ama: 'Drzevitzky S. <i>Proof-Carrying Hardware: A Novel Approach to Reconfigurable
    Hardware Security</i>. Universität Paderborn; 2012.'
  apa: 'Drzevitzky, S. (2012). <i>Proof-Carrying Hardware: A Novel Approach to Reconfigurable
    Hardware Security</i>. Universität Paderborn.'
  bibtex: '@book{Drzevitzky_2012, title={Proof-Carrying Hardware: A Novel Approach
    to Reconfigurable Hardware Security}, publisher={Universität Paderborn}, author={Drzevitzky,
    Stephanie}, year={2012} }'
  chicago: 'Drzevitzky, Stephanie. <i>Proof-Carrying Hardware: A Novel Approach to
    Reconfigurable Hardware Security</i>. Universität Paderborn, 2012.'
  ieee: 'S. Drzevitzky, <i>Proof-Carrying Hardware: A Novel Approach to Reconfigurable
    Hardware Security</i>. Universität Paderborn, 2012.'
  mla: 'Drzevitzky, Stephanie. <i>Proof-Carrying Hardware: A Novel Approach to Reconfigurable
    Hardware Security</i>. Universität Paderborn, 2012.'
  short: 'S. Drzevitzky, Proof-Carrying Hardware: A Novel Approach to Reconfigurable
    Hardware Security, Universität Paderborn, 2012.'
date_created: 2017-10-17T12:42:46Z
date_updated: 2022-01-06T07:02:44Z
ddc:
- '040'
department:
- _id: '78'
file:
- access_level: closed
  content_type: application/pdf
  creator: florida
  date_created: 2018-03-15T08:38:19Z
  date_updated: 2018-03-15T08:38:19Z
  file_id: '1261'
  file_name: 586-Drzevitzky-PhD_01.pdf
  file_size: 1438436
  relation: main_file
  success: 1
file_date_updated: 2018-03-15T08:38:19Z
has_accepted_license: '1'
language:
- iso: eng
main_file_link:
- open_access: '1'
  url: https://nbn-resolving.de/urn:nbn:de:hbz:466:2-10423
oa: '1'
page: '114'
project:
- _id: '12'
  name: SFB 901 - Subprojekt B4
- _id: '1'
  name: SFB 901
- _id: '3'
  name: SFB 901 - Project Area B
publication_status: published
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
title: 'Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security'
type: dissertation
user_id: '477'
year: '2012'
...
---
_id: '10652'
abstract:
- lang: eng
  text: "The paradigm shift towards many-core parallelism is accompanied by two fundamental
    questions: how should the many processors on a single die communicate to each
    other and what are suitable programming models for these novel architectures?
    In this thesis, the author tackles both questions by reviewing the reconfigurable
    mesh model of massively parallel computation for many-cores.\r\n\r\nThe book presents
    the design, implementation and evaluation of a many-core architecture that is
    based on the execution principles and communication infrastructure of the reconfigurable
    mesh. This work fundamentally rests on FPGA implementations and shows that reconfigurable
    mesh processors with hundreds of autonomous cores are feasible. Several case studies
    demonstrate the effectiveness of programming and illustrate why the reconfigurable
    mesh is a promising model for many-cores."
author:
- first_name: Heiner
  full_name: Giefers, Heiner
  last_name: Giefers
citation:
  ama: 'Giefers H. <i>Design and Programming of Reconfigurable Mesh Based Many-Cores</i>.
    Berlin: Logos Verlag Berlin GmbH; 2012.'
  apa: 'Giefers, H. (2012). <i>Design and Programming of Reconfigurable Mesh based
    Many-Cores</i>. Berlin: Logos Verlag Berlin GmbH.'
  bibtex: '@book{Giefers_2012, place={Berlin}, title={Design and Programming of Reconfigurable
    Mesh based Many-Cores}, publisher={Logos Verlag Berlin GmbH}, author={Giefers,
    Heiner}, year={2012} }'
  chicago: 'Giefers, Heiner. <i>Design and Programming of Reconfigurable Mesh Based
    Many-Cores</i>. Berlin: Logos Verlag Berlin GmbH, 2012.'
  ieee: 'H. Giefers, <i>Design and Programming of Reconfigurable Mesh based Many-Cores</i>.
    Berlin: Logos Verlag Berlin GmbH, 2012.'
  mla: Giefers, Heiner. <i>Design and Programming of Reconfigurable Mesh Based Many-Cores</i>.
    Logos Verlag Berlin GmbH, 2012.
  short: H. Giefers, Design and Programming of Reconfigurable Mesh Based Many-Cores,
    Logos Verlag Berlin GmbH, Berlin, 2012.
date_created: 2019-07-10T11:13:12Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
language:
- iso: eng
page: '159'
place: Berlin
publication_identifier:
  isbn:
  - 978-3-8325-3165-2
publication_status: published
publisher: Logos Verlag Berlin GmbH
status: public
supervisor:
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
title: Design and Programming of Reconfigurable Mesh based Many-Cores
type: dissertation
user_id: '3118'
year: '2012'
...