[{"status":"public","type":"bachelorsthesis","language":[{"iso":"ger"}],"department":[{"_id":"78"}],"user_id":"398","_id":"54246","citation":{"ama":"Hamm R. <i>Verarbeitung von Sensordaten auf eingebetteten heterogenen FPGA-Systemen</i>. Paderborn University; 2023.","chicago":"Hamm, Robin. <i>Verarbeitung von Sensordaten auf eingebetteten heterogenen FPGA-Systemen</i>. Paderborn University, 2023.","ieee":"R. Hamm, <i>Verarbeitung von Sensordaten auf eingebetteten heterogenen FPGA-Systemen</i>. Paderborn University, 2023.","short":"R. Hamm, Verarbeitung von Sensordaten auf eingebetteten heterogenen FPGA-Systemen, Paderborn University, 2023.","mla":"Hamm, Robin. <i>Verarbeitung von Sensordaten auf eingebetteten heterogenen FPGA-Systemen</i>. Paderborn University, 2023.","bibtex":"@book{Hamm_2023, title={Verarbeitung von Sensordaten auf eingebetteten heterogenen FPGA-Systemen}, publisher={Paderborn University}, author={Hamm, Robin}, year={2023} }","apa":"Hamm, R. (2023). <i>Verarbeitung von Sensordaten auf eingebetteten heterogenen FPGA-Systemen</i>. Paderborn University."},"year":"2023","title":"Verarbeitung von Sensordaten auf eingebetteten heterogenen FPGA-Systemen","author":[{"first_name":"Robin","full_name":"Hamm, Robin","last_name":"Hamm"}],"supervisor":[{"id":"74287","full_name":"Clausing, Lennart","orcid":"0000-0003-3789-6034","last_name":"Clausing","first_name":"Lennart"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}],"date_created":"2024-05-13T14:01:01Z","date_updated":"2024-05-15T13:29:49Z","publisher":"Paderborn University"},{"status":"public","type":"bachelorsthesis","language":[{"iso":"eng"}],"user_id":"398","department":[{"_id":"78"}],"_id":"52480","citation":{"apa":"Klassen, A. (2023). <i>Fast Partial Reconfiguration for ReconOS64 on Xilinx MPSoC Devices</i>. Paderborn University.","mla":"Klassen, Alexander. <i>Fast Partial Reconfiguration for ReconOS64 on Xilinx MPSoC Devices</i>. Paderborn University, 2023.","short":"A. Klassen, Fast Partial Reconfiguration for ReconOS64 on Xilinx MPSoC Devices, Paderborn University, 2023.","bibtex":"@book{Klassen_2023, title={Fast Partial Reconfiguration for ReconOS64 on Xilinx MPSoC Devices}, publisher={Paderborn University}, author={Klassen, Alexander}, year={2023} }","chicago":"Klassen, Alexander. <i>Fast Partial Reconfiguration for ReconOS64 on Xilinx MPSoC Devices</i>. Paderborn University, 2023.","ieee":"A. Klassen, <i>Fast Partial Reconfiguration for ReconOS64 on Xilinx MPSoC Devices</i>. Paderborn University, 2023.","ama":"Klassen A. <i>Fast Partial Reconfiguration for ReconOS64 on Xilinx MPSoC Devices</i>. Paderborn University; 2023."},"year":"2023","title":"Fast Partial Reconfiguration for ReconOS64 on Xilinx MPSoC Devices","date_created":"2024-03-11T16:06:00Z","author":[{"full_name":"Klassen, Alexander","last_name":"Klassen","first_name":"Alexander"}],"supervisor":[{"last_name":"Clausing","orcid":"0000-0003-3789-6034","full_name":"Clausing, Lennart","id":"74287","first_name":"Lennart"}],"date_updated":"2024-05-15T13:28:54Z","publisher":"Paderborn University"},{"citation":{"apa":"Evers, G. (2023). <i>Bewertung der Xilinx Runtime Library zur Hardware/Software-Kommunikation</i>. Paderborn University.","bibtex":"@book{Evers_2023, title={Bewertung der Xilinx Runtime Library zur Hardware/Software-Kommunikation}, publisher={Paderborn University}, author={Evers, Gerrit}, year={2023} }","mla":"Evers, Gerrit. <i>Bewertung der Xilinx Runtime Library zur Hardware/Software-Kommunikation</i>. Paderborn University, 2023.","short":"G. Evers, Bewertung der Xilinx Runtime Library zur Hardware/Software-Kommunikation, Paderborn University, 2023.","chicago":"Evers, Gerrit. <i>Bewertung der Xilinx Runtime Library zur Hardware/Software-Kommunikation</i>. Paderborn University, 2023.","ieee":"G. Evers, <i>Bewertung der Xilinx Runtime Library zur Hardware/Software-Kommunikation</i>. Paderborn University, 2023.","ama":"Evers G. <i>Bewertung der Xilinx Runtime Library zur Hardware/Software-Kommunikation</i>. Paderborn University; 2023."},"year":"2023","title":"Bewertung der Xilinx Runtime Library zur Hardware/Software-Kommunikation","supervisor":[{"first_name":"Lennart","orcid":"0000-0003-3789-6034","last_name":"Clausing","full_name":"Clausing, Lennart","id":"74287"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"}],"author":[{"full_name":"Evers, Gerrit","last_name":"Evers","first_name":"Gerrit"}],"date_created":"2024-05-13T13:59:09Z","date_updated":"2024-05-15T13:31:08Z","publisher":"Paderborn University","status":"public","type":"bachelorsthesis","language":[{"iso":"ger"}],"department":[{"_id":"78"}],"user_id":"398","_id":"54242"},{"author":[{"first_name":"Masood","last_name":"Raeisi Nafchi","full_name":"Raeisi Nafchi, Masood"}],"supervisor":[{"full_name":"Clausing, Lennart","id":"74287","last_name":"Clausing","orcid":"0000-0003-3789-6034","first_name":"Lennart"}],"date_created":"2023-07-18T08:55:14Z","date_updated":"2024-05-15T13:32:14Z","publisher":"Paderborn University","title":"Reconfigurable Random Forest Implementation on FPGA","citation":{"ama":"Raeisi Nafchi M. <i>Reconfigurable Random Forest Implementation on FPGA</i>. Paderborn University; 2023.","chicago":"Raeisi Nafchi, Masood. <i>Reconfigurable Random Forest Implementation on FPGA</i>. Paderborn University, 2023.","ieee":"M. Raeisi Nafchi, <i>Reconfigurable Random Forest Implementation on FPGA</i>. Paderborn University, 2023.","apa":"Raeisi Nafchi, M. (2023). <i>Reconfigurable Random Forest Implementation on FPGA</i>. Paderborn University.","mla":"Raeisi Nafchi, Masood. <i>Reconfigurable Random Forest Implementation on FPGA</i>. Paderborn University, 2023.","bibtex":"@book{Raeisi Nafchi_2023, title={Reconfigurable Random Forest Implementation on FPGA}, publisher={Paderborn University}, author={Raeisi Nafchi, Masood}, year={2023} }","short":"M. Raeisi Nafchi, Reconfigurable Random Forest Implementation on FPGA, Paderborn University, 2023."},"year":"2023","user_id":"398","department":[{"_id":"78"}],"_id":"46075","language":[{"iso":"eng"}],"type":"mastersthesis","status":"public"},{"type":"mastersthesis","status":"public","_id":"45715","project":[{"_id":"83","name":"SFB 901 - T1: SFB 901 -Subproject T1"},{"name":"SFB 901 - T: SFB 901 - Project Area T","_id":"82"},{"name":"SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen in dynamischen Märkten ","_id":"1","grant_number":"160364472"}],"department":[{"_id":"78"}],"user_id":"74287","language":[{"iso":"eng"}],"year":"2022","citation":{"apa":"Tcheussi Ngayap, V. I. (2022). <i>FreeRTOS on a MicroBlaze Soft-Core Processor with Hardware Accelerators</i>.","mla":"Tcheussi Ngayap, Vanessa Ingrid. <i>FreeRTOS on a MicroBlaze Soft-Core Processor with Hardware Accelerators</i>. 2022.","bibtex":"@book{Tcheussi Ngayap_2022, title={FreeRTOS on a MicroBlaze Soft-Core Processor with Hardware Accelerators}, author={Tcheussi Ngayap, Vanessa Ingrid}, year={2022} }","short":"V.I. Tcheussi Ngayap, FreeRTOS on a MicroBlaze Soft-Core Processor with Hardware Accelerators, 2022.","chicago":"Tcheussi Ngayap, Vanessa Ingrid. <i>FreeRTOS on a MicroBlaze Soft-Core Processor with Hardware Accelerators</i>, 2022.","ieee":"V. I. Tcheussi Ngayap, <i>FreeRTOS on a MicroBlaze Soft-Core Processor with Hardware Accelerators</i>. 2022.","ama":"Tcheussi Ngayap VI. <i>FreeRTOS on a MicroBlaze Soft-Core Processor with Hardware Accelerators</i>.; 2022."},"date_updated":"2023-06-22T12:07:53Z","date_created":"2023-06-22T12:04:57Z","author":[{"first_name":"Vanessa Ingrid","last_name":"Tcheussi Ngayap","full_name":"Tcheussi Ngayap, Vanessa Ingrid"}],"supervisor":[{"full_name":"Clausing, Lennart","id":"74287","last_name":"Clausing","orcid":"0000-0003-3789-6034","first_name":"Lennart"},{"last_name":"Platzner","id":"398","full_name":"Platzner, Marco","first_name":"Marco"},{"first_name":"Sybille","orcid":"0000-0002-3717-3939","last_name":"Hellebrand","id":"209","full_name":"Hellebrand, Sybille"}],"title":"FreeRTOS on a MicroBlaze Soft-Core Processor with Hardware Accelerators"},{"project":[{"name":"SFB 901","_id":"1"},{"name":"SFB 901 - Project Area T","_id":"82"},{"name":"SFB 901 -Subproject T1","_id":"83"}],"_id":"20820","user_id":"74287","department":[{"_id":"78"}],"language":[{"iso":"eng"}],"type":"bachelorsthesis","status":"public","date_updated":"2022-01-06T06:54:40Z","date_created":"2020-12-21T13:59:55Z","supervisor":[{"orcid":"0000-0003-3789-6034","last_name":"Clausing","id":"74287","full_name":"Clausing, Lennart","first_name":"Lennart"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"},{"full_name":"Plessl, Christian","id":"16153","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian"}],"author":[{"last_name":"Thiele","full_name":"Thiele, Simon","first_name":"Simon"}],"title":"Implementing Machine Learning Functions as PYNQ FPGA Overlays","year":"2020","citation":{"ieee":"S. Thiele, <i>Implementing Machine Learning Functions as PYNQ FPGA Overlays</i>. 2020.","chicago":"Thiele, Simon. <i>Implementing Machine Learning Functions as PYNQ FPGA Overlays</i>, 2020.","ama":"Thiele S. <i>Implementing Machine Learning Functions as PYNQ FPGA Overlays</i>.; 2020.","apa":"Thiele, S. (2020). <i>Implementing Machine Learning Functions as PYNQ FPGA Overlays</i>.","mla":"Thiele, Simon. <i>Implementing Machine Learning Functions as PYNQ FPGA Overlays</i>. 2020.","short":"S. Thiele, Implementing Machine Learning Functions as PYNQ FPGA Overlays, 2020.","bibtex":"@book{Thiele_2020, title={Implementing Machine Learning Functions as PYNQ FPGA Overlays}, author={Thiele, Simon}, year={2020} }"}},{"project":[{"name":"SFB 901","_id":"1"},{"_id":"82","name":"SFB 901 - Project Area T"},{"name":"SFB 901 -Subproject T1","_id":"83"}],"_id":"20821","user_id":"74287","department":[{"_id":"78"}],"language":[{"iso":"eng"}],"type":"mastersthesis","status":"public","date_updated":"2022-01-06T06:54:40Z","date_created":"2020-12-21T14:02:42Z","supervisor":[{"id":"74287","full_name":"Clausing, Lennart","last_name":"Clausing","orcid":"0000-0003-3789-6034","first_name":"Lennart"},{"full_name":"Platzner, Marco","id":"398","last_name":"Platzner","first_name":"Marco"},{"last_name":"Plessl","orcid":"0000-0001-5728-9982","id":"16153","full_name":"Plessl, Christian","first_name":"Christian"}],"author":[{"full_name":"Jaganath, Vivek","last_name":"Jaganath","first_name":"Vivek"}],"title":"Extension and Evaluation of Python-based High-Level Synthesis Tool Flows","year":"2020","citation":{"chicago":"Jaganath, Vivek. <i>Extension and Evaluation of Python-Based High-Level Synthesis Tool Flows</i>, 2020.","ieee":"V. Jaganath, <i>Extension and Evaluation of Python-based High-Level Synthesis Tool Flows</i>. 2020.","ama":"Jaganath V. <i>Extension and Evaluation of Python-Based High-Level Synthesis Tool Flows</i>.; 2020.","apa":"Jaganath, V. (2020). <i>Extension and Evaluation of Python-based High-Level Synthesis Tool Flows</i>.","bibtex":"@book{Jaganath_2020, title={Extension and Evaluation of Python-based High-Level Synthesis Tool Flows}, author={Jaganath, Vivek}, year={2020} }","mla":"Jaganath, Vivek. <i>Extension and Evaluation of Python-Based High-Level Synthesis Tool Flows</i>. 2020.","short":"V. Jaganath, Extension and Evaluation of Python-Based High-Level Synthesis Tool Flows, 2020."}},{"date_updated":"2024-03-11T15:57:39Z","date_created":"2024-03-11T15:57:13Z","supervisor":[{"first_name":"Lennart","full_name":"Clausing, Lennart","id":"74287","orcid":"0000-0003-3789-6034","last_name":"Clausing"}],"author":[{"full_name":"Mehta, Jinay D","last_name":"Mehta","first_name":"Jinay D"}],"title":"Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Reconfigurable System-on-Chip","year":"2019","citation":{"ama":"Mehta JD. <i>Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS on a Reconfigurable System-on-Chip</i>.; 2019.","chicago":"Mehta, Jinay D. <i>Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS on a Reconfigurable System-on-Chip</i>, 2019.","ieee":"J. D. Mehta, <i>Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Reconfigurable System-on-Chip</i>. 2019.","apa":"Mehta, J. D. (2019). <i>Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Reconfigurable System-on-Chip</i>.","bibtex":"@book{Mehta_2019, title={Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Reconfigurable System-on-Chip}, author={Mehta, Jinay D}, year={2019} }","mla":"Mehta, Jinay D. <i>Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS on a Reconfigurable System-on-Chip</i>. 2019.","short":"J.D. Mehta, Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS on a Reconfigurable System-on-Chip, 2019."},"_id":"52478","department":[{"_id":"78"}],"user_id":"74287","language":[{"iso":"eng"}],"type":"mastersthesis","status":"public"},{"department":[{"_id":"78"}],"user_id":"60323","_id":"15874","project":[{"_id":"83","name":"SFB 901 - T1: SFB 901 -Subproject T1"},{"name":"SFB 901 - T: SFB 901 - Project Area T","_id":"82"},{"grant_number":"160364472","name":"SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen in dynamischen Märkten ","_id":"1"}],"file_date_updated":"2021-02-13T16:46:58Z","language":[{"iso":"eng"}],"ddc":["004"],"type":"mastersthesis","status":"public","file":[{"relation":"main_file","content_type":"application/pdf","file_id":"17351","file_name":"thesis_main.pdf","access_level":"open_access","file_size":5920668,"creator":"clienen","date_created":"2020-07-01T11:46:49Z","date_updated":"2021-02-13T16:46:58Z"}],"date_created":"2020-02-11T10:22:06Z","supervisor":[{"first_name":"Lennart","last_name":"Clausing","orcid":"0000-0003-3789-6034","id":"74287","full_name":"Clausing, Lennart"},{"full_name":"Platzner, Marco","id":"398","last_name":"Platzner","first_name":"Marco"},{"full_name":"Hellebrand, Sybille","id":"209","orcid":"0000-0002-3717-3939","last_name":"Hellebrand","first_name":"Sybille"}],"author":[{"last_name":"Lienen","full_name":"Lienen, Christian","id":"60323","first_name":"Christian"}],"oa":"1","publisher":"Universität Paderborn","date_updated":"2023-07-31T11:58:50Z","title":"Implementing a Real-time System on a Platform FPGA operated with ReconOS","has_accepted_license":"1","publication_status":"submitted","citation":{"ama":"Lienen C. <i>Implementing a Real-Time System on a Platform FPGA Operated with ReconOS</i>. Universität Paderborn","chicago":"Lienen, Christian. <i>Implementing a Real-Time System on a Platform FPGA Operated with ReconOS</i>. Universität Paderborn, n.d.","ieee":"C. Lienen, <i>Implementing a Real-time System on a Platform FPGA operated with ReconOS</i>. Universität Paderborn.","bibtex":"@book{Lienen, title={Implementing a Real-time System on a Platform FPGA operated with ReconOS}, publisher={Universität Paderborn}, author={Lienen, Christian} }","mla":"Lienen, Christian. <i>Implementing a Real-Time System on a Platform FPGA Operated with ReconOS</i>. Universität Paderborn.","short":"C. Lienen, Implementing a Real-Time System on a Platform FPGA Operated with ReconOS, Universität Paderborn, n.d.","apa":"Lienen, C. (n.d.). <i>Implementing a Real-time System on a Platform FPGA operated with ReconOS</i>. Universität Paderborn."},"year":"2019"}]