---
_id: '54246'
author:
- first_name: Robin
  full_name: Hamm, Robin
  last_name: Hamm
citation:
  ama: Hamm R. <i>Verarbeitung von Sensordaten auf eingebetteten heterogenen FPGA-Systemen</i>.
    Paderborn University; 2023.
  apa: Hamm, R. (2023). <i>Verarbeitung von Sensordaten auf eingebetteten heterogenen
    FPGA-Systemen</i>. Paderborn University.
  bibtex: '@book{Hamm_2023, title={Verarbeitung von Sensordaten auf eingebetteten
    heterogenen FPGA-Systemen}, publisher={Paderborn University}, author={Hamm, Robin},
    year={2023} }'
  chicago: Hamm, Robin. <i>Verarbeitung von Sensordaten auf eingebetteten heterogenen
    FPGA-Systemen</i>. Paderborn University, 2023.
  ieee: R. Hamm, <i>Verarbeitung von Sensordaten auf eingebetteten heterogenen FPGA-Systemen</i>.
    Paderborn University, 2023.
  mla: Hamm, Robin. <i>Verarbeitung von Sensordaten auf eingebetteten heterogenen
    FPGA-Systemen</i>. Paderborn University, 2023.
  short: R. Hamm, Verarbeitung von Sensordaten auf eingebetteten heterogenen FPGA-Systemen,
    Paderborn University, 2023.
date_created: 2024-05-13T14:01:01Z
date_updated: 2024-05-15T13:29:49Z
department:
- _id: '78'
language:
- iso: ger
publisher: Paderborn University
status: public
supervisor:
- first_name: Lennart
  full_name: Clausing, Lennart
  id: '74287'
  last_name: Clausing
  orcid: 0000-0003-3789-6034
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
title: Verarbeitung von Sensordaten auf eingebetteten heterogenen FPGA-Systemen
type: bachelorsthesis
user_id: '398'
year: '2023'
...
---
_id: '52480'
author:
- first_name: Alexander
  full_name: Klassen, Alexander
  last_name: Klassen
citation:
  ama: Klassen A. <i>Fast Partial Reconfiguration for ReconOS64 on Xilinx MPSoC Devices</i>.
    Paderborn University; 2023.
  apa: Klassen, A. (2023). <i>Fast Partial Reconfiguration for ReconOS64 on Xilinx
    MPSoC Devices</i>. Paderborn University.
  bibtex: '@book{Klassen_2023, title={Fast Partial Reconfiguration for ReconOS64 on
    Xilinx MPSoC Devices}, publisher={Paderborn University}, author={Klassen, Alexander},
    year={2023} }'
  chicago: Klassen, Alexander. <i>Fast Partial Reconfiguration for ReconOS64 on Xilinx
    MPSoC Devices</i>. Paderborn University, 2023.
  ieee: A. Klassen, <i>Fast Partial Reconfiguration for ReconOS64 on Xilinx MPSoC
    Devices</i>. Paderborn University, 2023.
  mla: Klassen, Alexander. <i>Fast Partial Reconfiguration for ReconOS64 on Xilinx
    MPSoC Devices</i>. Paderborn University, 2023.
  short: A. Klassen, Fast Partial Reconfiguration for ReconOS64 on Xilinx MPSoC Devices,
    Paderborn University, 2023.
date_created: 2024-03-11T16:06:00Z
date_updated: 2024-05-15T13:28:54Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Lennart
  full_name: Clausing, Lennart
  id: '74287'
  last_name: Clausing
  orcid: 0000-0003-3789-6034
title: Fast Partial Reconfiguration for ReconOS64 on Xilinx MPSoC Devices
type: bachelorsthesis
user_id: '398'
year: '2023'
...
---
_id: '54242'
author:
- first_name: Gerrit
  full_name: Evers, Gerrit
  last_name: Evers
citation:
  ama: Evers G. <i>Bewertung der Xilinx Runtime Library zur Hardware/Software-Kommunikation</i>.
    Paderborn University; 2023.
  apa: Evers, G. (2023). <i>Bewertung der Xilinx Runtime Library zur Hardware/Software-Kommunikation</i>.
    Paderborn University.
  bibtex: '@book{Evers_2023, title={Bewertung der Xilinx Runtime Library zur Hardware/Software-Kommunikation},
    publisher={Paderborn University}, author={Evers, Gerrit}, year={2023} }'
  chicago: Evers, Gerrit. <i>Bewertung der Xilinx Runtime Library zur Hardware/Software-Kommunikation</i>.
    Paderborn University, 2023.
  ieee: G. Evers, <i>Bewertung der Xilinx Runtime Library zur Hardware/Software-Kommunikation</i>.
    Paderborn University, 2023.
  mla: Evers, Gerrit. <i>Bewertung der Xilinx Runtime Library zur Hardware/Software-Kommunikation</i>.
    Paderborn University, 2023.
  short: G. Evers, Bewertung der Xilinx Runtime Library zur Hardware/Software-Kommunikation,
    Paderborn University, 2023.
date_created: 2024-05-13T13:59:09Z
date_updated: 2024-05-15T13:31:08Z
department:
- _id: '78'
language:
- iso: ger
publisher: Paderborn University
status: public
supervisor:
- first_name: Lennart
  full_name: Clausing, Lennart
  id: '74287'
  last_name: Clausing
  orcid: 0000-0003-3789-6034
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
title: Bewertung der Xilinx Runtime Library zur Hardware/Software-Kommunikation
type: bachelorsthesis
user_id: '398'
year: '2023'
...
---
_id: '46075'
author:
- first_name: Masood
  full_name: Raeisi Nafchi, Masood
  last_name: Raeisi Nafchi
citation:
  ama: Raeisi Nafchi M. <i>Reconfigurable Random Forest Implementation on FPGA</i>.
    Paderborn University; 2023.
  apa: Raeisi Nafchi, M. (2023). <i>Reconfigurable Random Forest Implementation on
    FPGA</i>. Paderborn University.
  bibtex: '@book{Raeisi Nafchi_2023, title={Reconfigurable Random Forest Implementation
    on FPGA}, publisher={Paderborn University}, author={Raeisi Nafchi, Masood}, year={2023}
    }'
  chicago: Raeisi Nafchi, Masood. <i>Reconfigurable Random Forest Implementation on
    FPGA</i>. Paderborn University, 2023.
  ieee: M. Raeisi Nafchi, <i>Reconfigurable Random Forest Implementation on FPGA</i>.
    Paderborn University, 2023.
  mla: Raeisi Nafchi, Masood. <i>Reconfigurable Random Forest Implementation on FPGA</i>.
    Paderborn University, 2023.
  short: M. Raeisi Nafchi, Reconfigurable Random Forest Implementation on FPGA, Paderborn
    University, 2023.
date_created: 2023-07-18T08:55:14Z
date_updated: 2024-05-15T13:32:14Z
department:
- _id: '78'
language:
- iso: eng
publisher: Paderborn University
status: public
supervisor:
- first_name: Lennart
  full_name: Clausing, Lennart
  id: '74287'
  last_name: Clausing
  orcid: 0000-0003-3789-6034
title: Reconfigurable Random Forest Implementation on FPGA
type: mastersthesis
user_id: '398'
year: '2023'
...
---
_id: '45715'
author:
- first_name: Vanessa Ingrid
  full_name: Tcheussi Ngayap, Vanessa Ingrid
  last_name: Tcheussi Ngayap
citation:
  ama: Tcheussi Ngayap VI. <i>FreeRTOS on a MicroBlaze Soft-Core Processor with Hardware
    Accelerators</i>.; 2022.
  apa: Tcheussi Ngayap, V. I. (2022). <i>FreeRTOS on a MicroBlaze Soft-Core Processor
    with Hardware Accelerators</i>.
  bibtex: '@book{Tcheussi Ngayap_2022, title={FreeRTOS on a MicroBlaze Soft-Core Processor
    with Hardware Accelerators}, author={Tcheussi Ngayap, Vanessa Ingrid}, year={2022}
    }'
  chicago: Tcheussi Ngayap, Vanessa Ingrid. <i>FreeRTOS on a MicroBlaze Soft-Core
    Processor with Hardware Accelerators</i>, 2022.
  ieee: V. I. Tcheussi Ngayap, <i>FreeRTOS on a MicroBlaze Soft-Core Processor with
    Hardware Accelerators</i>. 2022.
  mla: Tcheussi Ngayap, Vanessa Ingrid. <i>FreeRTOS on a MicroBlaze Soft-Core Processor
    with Hardware Accelerators</i>. 2022.
  short: V.I. Tcheussi Ngayap, FreeRTOS on a MicroBlaze Soft-Core Processor with Hardware
    Accelerators, 2022.
date_created: 2023-06-22T12:04:57Z
date_updated: 2023-06-22T12:07:53Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '83'
  name: 'SFB 901 - T1: SFB 901 -Subproject T1'
- _id: '82'
  name: 'SFB 901 - T: SFB 901 - Project Area T'
- _id: '1'
  grant_number: '160364472'
  name: 'SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen
    in dynamischen Märkten '
status: public
supervisor:
- first_name: Lennart
  full_name: Clausing, Lennart
  id: '74287'
  last_name: Clausing
  orcid: 0000-0003-3789-6034
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Sybille
  full_name: Hellebrand, Sybille
  id: '209'
  last_name: Hellebrand
  orcid: 0000-0002-3717-3939
title: FreeRTOS on a MicroBlaze Soft-Core Processor with Hardware Accelerators
type: mastersthesis
user_id: '74287'
year: '2022'
...
---
_id: '20820'
author:
- first_name: Simon
  full_name: Thiele, Simon
  last_name: Thiele
citation:
  ama: Thiele S. <i>Implementing Machine Learning Functions as PYNQ FPGA Overlays</i>.;
    2020.
  apa: Thiele, S. (2020). <i>Implementing Machine Learning Functions as PYNQ FPGA
    Overlays</i>.
  bibtex: '@book{Thiele_2020, title={Implementing Machine Learning Functions as PYNQ
    FPGA Overlays}, author={Thiele, Simon}, year={2020} }'
  chicago: Thiele, Simon. <i>Implementing Machine Learning Functions as PYNQ FPGA
    Overlays</i>, 2020.
  ieee: S. Thiele, <i>Implementing Machine Learning Functions as PYNQ FPGA Overlays</i>.
    2020.
  mla: Thiele, Simon. <i>Implementing Machine Learning Functions as PYNQ FPGA Overlays</i>.
    2020.
  short: S. Thiele, Implementing Machine Learning Functions as PYNQ FPGA Overlays,
    2020.
date_created: 2020-12-21T13:59:55Z
date_updated: 2022-01-06T06:54:40Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '1'
  name: SFB 901
- _id: '82'
  name: SFB 901 - Project Area T
- _id: '83'
  name: SFB 901 -Subproject T1
status: public
supervisor:
- first_name: Lennart
  full_name: Clausing, Lennart
  id: '74287'
  last_name: Clausing
  orcid: 0000-0003-3789-6034
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
title: Implementing Machine Learning Functions as PYNQ FPGA Overlays
type: bachelorsthesis
user_id: '74287'
year: '2020'
...
---
_id: '20821'
author:
- first_name: Vivek
  full_name: Jaganath, Vivek
  last_name: Jaganath
citation:
  ama: Jaganath V. <i>Extension and Evaluation of Python-Based High-Level Synthesis
    Tool Flows</i>.; 2020.
  apa: Jaganath, V. (2020). <i>Extension and Evaluation of Python-based High-Level
    Synthesis Tool Flows</i>.
  bibtex: '@book{Jaganath_2020, title={Extension and Evaluation of Python-based High-Level
    Synthesis Tool Flows}, author={Jaganath, Vivek}, year={2020} }'
  chicago: Jaganath, Vivek. <i>Extension and Evaluation of Python-Based High-Level
    Synthesis Tool Flows</i>, 2020.
  ieee: V. Jaganath, <i>Extension and Evaluation of Python-based High-Level Synthesis
    Tool Flows</i>. 2020.
  mla: Jaganath, Vivek. <i>Extension and Evaluation of Python-Based High-Level Synthesis
    Tool Flows</i>. 2020.
  short: V. Jaganath, Extension and Evaluation of Python-Based High-Level Synthesis
    Tool Flows, 2020.
date_created: 2020-12-21T14:02:42Z
date_updated: 2022-01-06T06:54:40Z
department:
- _id: '78'
language:
- iso: eng
project:
- _id: '1'
  name: SFB 901
- _id: '82'
  name: SFB 901 - Project Area T
- _id: '83'
  name: SFB 901 -Subproject T1
status: public
supervisor:
- first_name: Lennart
  full_name: Clausing, Lennart
  id: '74287'
  last_name: Clausing
  orcid: 0000-0003-3789-6034
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
title: Extension and Evaluation of Python-based High-Level Synthesis Tool Flows
type: mastersthesis
user_id: '74287'
year: '2020'
...
---
_id: '52478'
author:
- first_name: Jinay D
  full_name: Mehta, Jinay D
  last_name: Mehta
citation:
  ama: Mehta JD. <i>Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS
    on a Reconfigurable System-on-Chip</i>.; 2019.
  apa: Mehta, J. D. (2019). <i>Multithreaded Software/Hardware Programming with ReconOS/freeRTOS
    on a Reconfigurable System-on-Chip</i>.
  bibtex: '@book{Mehta_2019, title={Multithreaded Software/Hardware Programming with
    ReconOS/freeRTOS on a Reconfigurable System-on-Chip}, author={Mehta, Jinay D},
    year={2019} }'
  chicago: Mehta, Jinay D. <i>Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS
    on a Reconfigurable System-on-Chip</i>, 2019.
  ieee: J. D. Mehta, <i>Multithreaded Software/Hardware Programming with ReconOS/freeRTOS
    on a Reconfigurable System-on-Chip</i>. 2019.
  mla: Mehta, Jinay D. <i>Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS
    on a Reconfigurable System-on-Chip</i>. 2019.
  short: J.D. Mehta, Multithreaded Software/Hardware Programming with ReconOS/FreeRTOS
    on a Reconfigurable System-on-Chip, 2019.
date_created: 2024-03-11T15:57:13Z
date_updated: 2024-03-11T15:57:39Z
department:
- _id: '78'
language:
- iso: eng
status: public
supervisor:
- first_name: Lennart
  full_name: Clausing, Lennart
  id: '74287'
  last_name: Clausing
  orcid: 0000-0003-3789-6034
title: Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Reconfigurable
  System-on-Chip
type: mastersthesis
user_id: '74287'
year: '2019'
...
---
_id: '15874'
author:
- first_name: Christian
  full_name: Lienen, Christian
  id: '60323'
  last_name: Lienen
citation:
  ama: Lienen C. <i>Implementing a Real-Time System on a Platform FPGA Operated with
    ReconOS</i>. Universität Paderborn
  apa: Lienen, C. (n.d.). <i>Implementing a Real-time System on a Platform FPGA operated
    with ReconOS</i>. Universität Paderborn.
  bibtex: '@book{Lienen, title={Implementing a Real-time System on a Platform FPGA
    operated with ReconOS}, publisher={Universität Paderborn}, author={Lienen, Christian}
    }'
  chicago: Lienen, Christian. <i>Implementing a Real-Time System on a Platform FPGA
    Operated with ReconOS</i>. Universität Paderborn, n.d.
  ieee: C. Lienen, <i>Implementing a Real-time System on a Platform FPGA operated
    with ReconOS</i>. Universität Paderborn.
  mla: Lienen, Christian. <i>Implementing a Real-Time System on a Platform FPGA Operated
    with ReconOS</i>. Universität Paderborn.
  short: C. Lienen, Implementing a Real-Time System on a Platform FPGA Operated with
    ReconOS, Universität Paderborn, n.d.
date_created: 2020-02-11T10:22:06Z
date_updated: 2023-07-31T11:58:50Z
ddc:
- '004'
department:
- _id: '78'
file:
- access_level: open_access
  content_type: application/pdf
  creator: clienen
  date_created: 2020-07-01T11:46:49Z
  date_updated: 2021-02-13T16:46:58Z
  file_id: '17351'
  file_name: thesis_main.pdf
  file_size: 5920668
  relation: main_file
file_date_updated: 2021-02-13T16:46:58Z
has_accepted_license: '1'
language:
- iso: eng
oa: '1'
project:
- _id: '83'
  name: 'SFB 901 - T1: SFB 901 -Subproject T1'
- _id: '82'
  name: 'SFB 901 - T: SFB 901 - Project Area T'
- _id: '1'
  grant_number: '160364472'
  name: 'SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen
    in dynamischen Märkten '
publication_status: submitted
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Lennart
  full_name: Clausing, Lennart
  id: '74287'
  last_name: Clausing
  orcid: 0000-0003-3789-6034
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Sybille
  full_name: Hellebrand, Sybille
  id: '209'
  last_name: Hellebrand
  orcid: 0000-0002-3717-3939
title: Implementing a Real-time System on a Platform FPGA operated with ReconOS
type: mastersthesis
user_id: '60323'
year: '2019'
...