@inproceedings{16417,
  abstract     = {{The performance of High-Level Synthesis (HLS) applications with irregular data structures is limited by its imperative programming paradigm like C/C++. In this paper, we show that constructing concurrent data structures with channels, a programming construct derived from CSP (communicating sequential processes) paradigm, is an effective approach to improve the performance of these applications. We evaluate concurrent data structure for FPGA by synthesizing a K-means clustering algorithm on the Intel HARP2 platform. A fully pipelined KMC processing element can be synthesized from OpenCL with the help of a SPSC (single-producer-single-consumer) queue and stack built from channels, achieving 15.2x speedup over a sequential baseline. The number of processing element can be scaled up by leveraging a MPMC (multiple-producer-multiple-consumer) stack with work distribution for dynamic load balance. Evaluation shows that an additional 3.5x speedup can be achieved when 4 processing element is instantiated. These results show that the concurrent data structure built with channels has great potential for improving the parallelism of HLS applications. We hope that our study will stimulate further research into the potential of channel-based HLS.}},
  author       = {{Yan, Hui and Li, Zhaoshi and Liu, Leibo and Yin, Shouyi and Wei, Shaojun}},
  booktitle    = {{Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays}},
  isbn         = {{9781450361378}},
  keywords     = {{pc2-harp-ressources}},
  title        = {{{Constructing Concurrent Data Structures on FPGA with Channels}}},
  doi          = {{10.1145/3289602.3293921}},
  year         = {{2019}},
}

@article{16420,
  abstract     = {{<jats:p> Field-Programmable Gate Arrays (FPGAs) are widely used in the central signal processing design of the Square Kilometer Array (SKA) as hardware accelerators. The frequency domain acceleration search (FDAS) module is an important part of the SKA1-MID pulsar search engine. To develop for a yet to be finalized hardware, for cross-discipline interoperability and to achieve fast prototyping, OpenCL as a high-level FPGA synthesis approaches employed to create the sub-modules of FDAS. The FT convolution and the harmonic-summing plus some other minor sub-modules are elements in the FDAS module that have been well-optimized separately before. In this paper, we explore the design space of combining well-optimized designs, dealing with the ensuing need to trade-off and compromise. Pipeline computing is employed to handle multiple input arrays at high speed. The hardware target is to employ multiple high-end FPGAs to process the combined FDAS module. The results show interesting consequences, where the best individual solutions are not necessarily the best solutions for the speed of a pipeline where FPGA resources and memory bandwidth need to be shared. By proposing multiple buffering techniques to the pipeline, the combined FDAS module can achieve up to 2[Formula: see text] speedup over implementations without pipeline computing. We perform an extensive experimental evaluation on multiple high-end FPGA cards hosted in a workstation and compare to a technology comparable mid-range GPU. </jats:p>}},
  author       = {{Wang, Haomiao and Thiagaraj, Prabu and Sinnen, Oliver}},
  issn         = {{2251-1717}},
  journal      = {{Journal of Astronomical Instrumentation}},
  keywords     = {{pc2-harp-ressources}},
  title        = {{{Combining Multiple Optimized FPGA-based Pulsar Search Modules Using OpenCL}}},
  doi          = {{10.1142/s2251171719500089}},
  year         = {{2019}},
}

@article{16422,
  abstract     = {{<jats:p>Intel recently introduced the Heterogeneous Architecture Research Platform, HARP. In this platform, the Central Processing Unit and a Field-Programmable Gate Array are connected through a high-bandwidth, low-latency interconnect and both share DRAM memory. For this platform, Open Computing Language (OpenCL), a High-Level Synthesis (HLS) language, is made available. By making use of HLS, a faster design cycle can be achieved compared to programming in a traditional hardware description language. This, however, comes at the cost of having less control over the hardware implementation. We will investigate how OpenCL can be applied to implement a real-time guided image filter on the HARP platform. In the first phase, the performance-critical parameters of the OpenCL programming model are defined using several specialized benchmarks. In a second phase, the guided image filter algorithm is implemented using the insights gained in the first phase. Both a floating-point and a fixed-point implementation were developed for this algorithm, based on a sliding window implementation. This resulted in a maximum floating-point performance of 135 GFLOPS, a maximum fixed-point performance of 430 GOPS and a throughput of HD color images at 74 frames per second.</jats:p>}},
  author       = {{Faict, Thomas and D’Hollander, Erik H. and Goossens, Bart}},
  issn         = {{1999-4893}},
  journal      = {{Algorithms}},
  keywords     = {{pc2-harp-ressources}},
  title        = {{{Mapping a Guided Image Filter on the HARP Reconfigurable Architecture Using OpenCL}}},
  doi          = {{10.3390/a12080149}},
  year         = {{2019}},
}

@article{16423,
  abstract     = {{Heterogeneous computing that exploits simultaneous co-processing with different device types has been shown to be effective at both increasing performance and reducing energy consumption. In this paper, we extend a scheduling framework encapsulated in a high-level C++ template and previously developed for heterogeneous chips comprising CPU and GPU cores, to new high-performance platforms for the data center, which include a cache coherent FPGA fabric and many-core CPU resources. Our goal is to evaluate the suitability of our framework with these new FPGA-based platforms, identifying performance benefits and limitations.We target the state-of-the-art HARP processor that includes 14 high-end Xeon classes tightly coupled to a FPGA device located in the same package. We select eight benchmarks from the high-performance computing domain that have been ported and optimized for this heterogeneous platform. The results show that a dynamic and adaptive scheduler that exploits simultaneous processing among the devices can improve performance up to a factor of 8 × compared to the best alternative solutions that only use the CPU cores or the FPGA fabric. Moreover, our proposal achieves up to 15% and 37% of improvement compared to the best heterogeneous solutions found with a dynamic and static schedulers, respectively.}},
  author       = {{Rodríguez, Andrés and Navarro, Angeles and Asenjo, Rafael and Corbera, Francisco and Gran, Rubén and Suárez, Darío and Nunez-Yanez, Jose}},
  issn         = {{0920-8542}},
  journal      = {{The Journal of Supercomputing}},
  keywords     = {{pc2-harp-ressources}},
  title        = {{{Parallel multiprocessing and scheduling on the heterogeneous Xeon+FPGA platform}}},
  doi          = {{10.1007/s11227-019-02935-1}},
  year         = {{2019}},
}

@inproceedings{16427,
  abstract     = {{Transactional Memory (TM) has been considered as a promising alternative to existing synchronization operations, which are often the largest stumbling block to unleashing parallelism of applications. Efficient implementations of TM, however, are challenging due to the tension between lowering performance overhead and avoiding unnecessary aborts.

In this paper, we present Reachability-based Optimistic Concurrency Control for Transactional Memory (ROCoCoTM), a novel scheme which offloads concurrency control (CC) algorithms, the central building blocks of TM systems, to reconfigurable hardware. To reduce the abort rate, an innovative formalization of mainstream CC algorithms is developed to reveal a common restriction that leads to unnecessary aborts. This restriction is resolved by the ROCoCo algorithm with a centralized validation phase, which can be efficiently pipelined in hardware. Thanks to a high-performance offloading engine implemented in reconfigurable hardware, ROCoCo algorithm results in decreased abort rates and reduced performance overhead. The whole system is implemented on Intel's HARP2 platform and evaluated with the STAMP benchmark suite. Experiments show 1.55x and 8.05x geomean speedup over TinySTM and an HTM based on Intel TSX, respectively. Given the fast-growing deployment of commodity CPU-FPGA platforms, ROCoCoTM paves the way for software programmers to exploit heterogeneous computing resources with a high-level transactional abstraction to effectively extract the parallelism in modern applications.}},
  author       = {{Li, Zhaoshi and Liu, Leibo and Deng, Yangdong and Wang, Jiawei and Liu, Zhiwei and Yin, Shouyi and Wei, Shaojun}},
  booktitle    = {{Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture}},
  isbn         = {{9781450369381}},
  keywords     = {{pc2-harp-ressources}},
  title        = {{{FPGA-Accelerated Optimistic Concurrency Control for Transactional Memory}}},
  doi          = {{10.1145/3352460.3358270}},
  year         = {{2019}},
}

@inproceedings{16433,
  author       = {{Rehlaender, Philipp and Grote, Tobias and Tikhonov, Sergey and Niejende, Hugues and Schafmeister, Frank and Bocker, Joachim and Thiemann, Peter}},
  booktitle    = {{2019 21st European Conference on Power Electronics and Applications (EPE '19 ECCE Europe)}},
  isbn         = {{9789075815313}},
  title        = {{{A PCB Integrated Winding Using a Litz Structure for a Wireless Charging Coil}}},
  doi          = {{10.23919/epe.2019.8914900}},
  year         = {{2019}},
}

@inproceedings{16438,
  author       = {{Rehlaender, Philipp and Schafmeister, Frank and Bocker, Joachim and Grote, Tobias}},
  booktitle    = {{2019 IEEE 28th International Symposium on Industrial Electronics (ISIE)}},
  isbn         = {{9781728136660}},
  title        = {{{Analytical Topology Comparison for a Single Stage On-Board EV-Battery Converter}}},
  doi          = {{10.1109/isie.2019.8781222}},
  year         = {{2019}},
}

@inbook{16443,
  author       = {{Rehlaender, Philipp and Schroeer, Maik and Chadha, Gavneet and Schwung, Andreas}},
  booktitle    = {{Proceedings of the International Neural Networks Society}},
  isbn         = {{9783030168407}},
  issn         = {{2661-8141}},
  title        = {{{Traffic Sign Detection Using R-CNN}}},
  doi          = {{10.1007/978-3-030-16841-4_24}},
  year         = {{2019}},
}

@article{16709,
  author       = {{Sahai, Tuhin and Ziessler, Adrian and Klus, Stefan and Dellnitz, Michael}},
  issn         = {{0924-090X}},
  journal      = {{Nonlinear Dynamics}},
  title        = {{{Continuous relaxations for the traveling salesman problem}}},
  doi          = {{10.1007/s11071-019-05092-5}},
  year         = {{2019}},
}

@inproceedings{16793,
  author       = {{Pfeifer, Florian and Dietrich, André and Marten, Thorsten and Tröster, Thomas and Nacke, Bernard}},
  booktitle    = {{Proceedings of 7th International Conference on Hot Sheet Metal Forming of High-Performance Steel}},
  isbn         = {{978-3-95735-104-3}},
  location     = {{Luleå}},
  pages        = {{585--593}},
  title        = {{{Investigation on Inductive Heating of Sheet Metal for an Industrial Hot Stamping Process}}},
  year         = {{2019}},
}

@inproceedings{16794,
  author       = {{Striewe, Jan André and Thomas, Robert and Fischer, Fabian and Wiens, Timo and Tröster, Thomas}},
  location     = {{Neu-Ulm}},
  publisher    = {{DGM-Inventum GmbH }},
  title        = {{{Energieabsorptions- und Versagensverhalten eines automobilen Seitenschwellers mit lokaler Verstärkung aus kohlenstofffaserverstärktem Kunststoff nach Alterung}}},
  year         = {{2019}},
}

@misc{16825,
  author       = {{Ahlers, Dominik and Tröster, Thomas}},
  publisher    = {{EuroPM}},
  title        = {{{Performance Parameters and HIP Routes for additively manufactured titanium alloy Ti6Al4V}}},
  year         = {{2019}},
}

@inproceedings{16826,
  author       = {{Camberg, Alan Adam and Hielscher, Christian}},
  booktitle    = {{Aachen Body Engineering Days 2019}},
  location     = {{Aachen}},
  title        = {{{A holistic approach to the lightweight design of tailored structural components using the example of a hybrid A-pillar}}},
  year         = {{2019}},
}

@inproceedings{16827,
  author       = {{Camberg, Alan Adam and Tröster, Thomas}},
  booktitle    = {{26. Sächsische Fachtagung Umformtechnik}},
  location     = {{Dresden}},
  title        = {{{Challenges in fracture modeling under non-isothermal forming conditions using the example of a new forming process for aluminum blanks}}},
  year         = {{2019}},
}

@inproceedings{16831,
  author       = {{Tinkloh, Steffen Rainer and Wu, Tao and Tröster, Thomas and Niendorf, Thomas}},
  location     = {{Wuhan}},
  title        = {{{A micromechanical based finite element simulation of process induced residual stresses in metal-CFRP-hybrid structures}}},
  year         = {{2019}},
}

@techreport{16847,
  abstract     = {{In this work we describe our results achieved in the ProtestNews Lab at CLEF 2019. To tackle the problems of event sentence detection and event extraction we decided to use contextualized string embeddings. The models were trained on a data corpus collected from Indian news sources, but evaluated on data obtained from news sources from other countries as well, such as China. Our models have obtained competitive results and have scored 3rd in the event sentence detection task and 1st in the event extraction task based on average F1-scores for different test datasets.}},
  author       = {{Skitalinskaya, Gabriella and Klaff, Jonas and Spliethöver, Maximilian}},
  pages        = {{7}},
  title        = {{{CLEF ProtestNews Lab 2019: Contextualized Word Embeddings for Event Sentence Detection and Event Extraction}}},
  volume       = {{2380}},
  year         = {{2019}},
}

@unpublished{16853,
  abstract     = {{State-of-the-art frameworks for generating approximate circuits usually rely on information gained through circuit synthesis and/or verification to explore the search space and to find an optimal solution. Throughout the process, a large number of circuits may be subject to processing, leading to considerable runtimes. In this work, we propose a search which takes error bounds and pre-computed impact factors into account to reduce the number of invoked synthesis and verification processes. In our experimental results, we achieved speed-ups of up to 76x while area savings remain comparable to the reference search method, simulated annealing.}},
  author       = {{Witschen, Linus Matthias and Ghasemzadeh Mohammadi, Hassan and Artmann, Matthias and Platzner, Marco}},
  booktitle    = {{Fourth Workshop on Approximate Computing (AxC 2019)}},
  keywords     = {{Approximate computing, parameter selection, search space exploration, verification, circuit synthesis}},
  pages        = {{2}},
  title        = {{{Jump Search: A Fast Technique for the Synthesis of Approximate Circuits}}},
  year         = {{2019}},
}

@article{16882,
  author       = {{Atkins, Marc and Gilroy, Bernard Michael and Seiler, Volker}},
  journal      = {{Intereconomics}},
  number       = {{2}},
  pages        = {{120--126}},
  publisher    = {{Springer}},
  title        = {{{New Dimensions of Service Offshoring in World Trade}}},
  volume       = {{54}},
  year         = {{2019}},
}

@inbook{16883,
  author       = {{Gilroy, Bernard Michael and Golderbein, Alexander and Peitz, Christian and Stöckmann, Nico}},
  booktitle    = {{Operations Research Proceedings 2018}},
  editor       = {{Fortz, B. and Labbé, M.}},
  pages        = {{201--208}},
  publisher    = {{Springer}},
  title        = {{{The Impact of Monetary Policy on Investment Bank Profitability in Unequal Economies}}},
  year         = {{2019}},
}

@article{16884,
  author       = {{Krimphove, Dieter and Peitz, Christian}},
  journal      = {{Fintechs: Rechtliche Grundlagen moderner Finanztechnologien}},
  pages        = {{287}},
  publisher    = {{Sch{\"a}ffer-Poeschel}},
  title        = {{{Social-Trading und Copy-Trading}}},
  year         = {{2019}},
}