[{"author":[{"full_name":"Schuhbeck, Veronika","last_name":"Schuhbeck","first_name":"Veronika"},{"first_name":"Nils","full_name":"Siegfried, Nils","last_name":"Siegfried"},{"last_name":"Dorner","full_name":"Dorner, Verena","first_name":"Verena"},{"first_name":"Alexander","last_name":"Benlian","full_name":"Benlian, Alexander"},{"first_name":"Michael","full_name":"Scholz, Michael","last_name":"Scholz"},{"first_name":"Guido","last_name":"Schryen","full_name":"Schryen, Guido","id":"72850"}],"date_created":"2019-01-08T14:06:32Z","oa":"1","date_updated":"2022-01-06T07:03:09Z","conference":{"location":"Siegen, Germany","end_date":"2019-02-27","start_date":"2019-02-24","name":"14th International Conference on Wirtschaftsinformatik"},"title":"Walking the Middle Path: How Medium Trade-off Exposure Leads to Higher Consumer Satisfaction in Recommender Agents","has_accepted_license":"1","page":"55-64","citation":{"ama":"Schuhbeck V, Siegfried N, Dorner V, Benlian A, Scholz M, Schryen G. Walking the Middle Path: How Medium Trade-off Exposure Leads to Higher Consumer Satisfaction in Recommender Agents. In: <i>Proceedings of the 14. Internationale Tagung Wirtschaftsinformatik</i>. Siegen, Germany; 2019:55-64.","ieee":"V. Schuhbeck, N. Siegfried, V. Dorner, A. Benlian, M. Scholz, and G. Schryen, “Walking the Middle Path: How Medium Trade-off Exposure Leads to Higher Consumer Satisfaction in Recommender Agents,” in <i>Proceedings of the 14. Internationale Tagung Wirtschaftsinformatik</i>, Siegen, Germany, 2019, pp. 55–64.","chicago":"Schuhbeck, Veronika, Nils Siegfried, Verena Dorner, Alexander Benlian, Michael Scholz, and Guido Schryen. “Walking the Middle Path: How Medium Trade-off Exposure Leads to Higher Consumer Satisfaction in Recommender Agents.” In <i>Proceedings of the 14. Internationale Tagung Wirtschaftsinformatik</i>, 55–64. Siegen, Germany, 2019.","mla":"Schuhbeck, Veronika, et al. “Walking the Middle Path: How Medium Trade-off Exposure Leads to Higher Consumer Satisfaction in Recommender Agents.” <i>Proceedings of the 14. Internationale Tagung Wirtschaftsinformatik</i>, 2019, pp. 55–64.","bibtex":"@inproceedings{Schuhbeck_Siegfried_Dorner_Benlian_Scholz_Schryen_2019, place={Siegen, Germany}, title={Walking the Middle Path: How Medium Trade-off Exposure Leads to Higher Consumer Satisfaction in Recommender Agents}, booktitle={Proceedings of the 14. Internationale Tagung Wirtschaftsinformatik}, author={Schuhbeck, Veronika and Siegfried, Nils and Dorner, Verena and Benlian, Alexander and Scholz, Michael and Schryen, Guido}, year={2019}, pages={55–64} }","short":"V. Schuhbeck, N. Siegfried, V. Dorner, A. Benlian, M. Scholz, G. Schryen, in: Proceedings of the 14. Internationale Tagung Wirtschaftsinformatik, Siegen, Germany, 2019, pp. 55–64.","apa":"Schuhbeck, V., Siegfried, N., Dorner, V., Benlian, A., Scholz, M., &#38; Schryen, G. (2019). Walking the Middle Path: How Medium Trade-off Exposure Leads to Higher Consumer Satisfaction in Recommender Agents. In <i>Proceedings of the 14. Internationale Tagung Wirtschaftsinformatik</i> (pp. 55–64). Siegen, Germany."},"year":"2019","place":"Siegen, Germany","department":[{"_id":"277"}],"user_id":"61579","_id":"6514","language":[{"iso":"eng"}],"file_date_updated":"2021-08-13T13:26:11Z","keyword":["Recommender Agents","Preference Elicitation Method","Trade-off Exposure","Customer Satisfaction"],"ddc":["000"],"publication":"Proceedings of the 14. Internationale Tagung Wirtschaftsinformatik","type":"conference","status":"public","file":[{"relation":"main_file","content_type":"application/pdf","access_level":"closed","file_name":"WALKING THE MIDDLE PATH.pdf","file_id":"6515","file_size":371490,"creator":"hsiemes","date_created":"2019-01-08T14:07:17Z","date_updated":"2021-08-13T13:26:11Z"},{"date_updated":"2021-08-13T13:25:53Z","date_created":"2021-08-13T13:25:53Z","creator":"hsiemes","file_size":331001,"file_id":"23393","access_level":"open_access","file_name":"Walking the Middle Path_ How Medium Trade-Off Exposure Leads to H.pdf","content_type":"application/pdf","relation":"main_file"}],"abstract":[{"lang":"eng","text":"Recommender Agents (RAs) facilitate consumers’ online purchase decisions for complex, multi-attribute products. As not all combinations of attribute levels can be obtained, users are forced into trade-offs. The exposure of trade-offs in a RA has been found to affect consumers’ perceptions. However, little is known about how different preference elicitation methods in RAs affect consumers by varying degrees of trade-off exposure. We propose a research model that investigates how different levels of trade-off exposure cognitively and affectively influence consumers’ satisfaction with RAs. We operationalize these levels in three different RA types and test our hypotheses in a laboratory experiment with 116 participants. Our results indicate that with increasing tradeoff exposure, perceived enjoyment and perceived control follow an inverted Ushaped relationship. Hence, RAs using preference elicitation methods with medium trade-off exposure yield highest consumer satisfaction. This contributes to the understanding of trade-offs in RAs and provides valuable implications to e-commerce practitioners."}]},{"year":"2019","place":"Universität Paderborn","citation":{"chicago":"Seutter, Janina. <i>Bewertung von Maschinen-generierten Geschäftsmodell-Ideen: Eine experimentelle Untersuchung</i>. Universität Paderborn, 2019.","ieee":"J. Seutter, <i>Bewertung von Maschinen-generierten Geschäftsmodell-Ideen: Eine experimentelle Untersuchung</i>. Universität Paderborn, 2019.","ama":"Seutter J. <i>Bewertung von Maschinen-generierten Geschäftsmodell-Ideen: Eine experimentelle Untersuchung</i>. Universität Paderborn; 2019.","bibtex":"@book{Seutter_2019, place={Universität Paderborn}, title={Bewertung von Maschinen-generierten Geschäftsmodell-Ideen: Eine experimentelle Untersuchung}, author={Seutter, Janina}, year={2019} }","short":"J. Seutter, Bewertung von Maschinen-generierten Geschäftsmodell-Ideen: Eine experimentelle Untersuchung, Universität Paderborn, 2019.","mla":"Seutter, Janina. <i>Bewertung von Maschinen-generierten Geschäftsmodell-Ideen: Eine experimentelle Untersuchung</i>. 2019.","apa":"Seutter, J. (2019). <i>Bewertung von Maschinen-generierten Geschäftsmodell-Ideen: Eine experimentelle Untersuchung</i>. Universität Paderborn."},"date_updated":"2022-01-06T07:03:13Z","date_created":"2019-01-11T13:10:16Z","supervisor":[{"first_name":"Dennis","id":"21117","full_name":"Kundisch, Dennis","last_name":"Kundisch"}],"author":[{"first_name":"Janina","full_name":"Seutter, Janina","last_name":"Seutter"}],"title":"Bewertung von Maschinen-generierten Geschäftsmodell-Ideen: Eine experimentelle Untersuchung","type":"mastersthesis","status":"public","project":[{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"17","name":"SFB 901 - Subproject C5"}],"_id":"6628","user_id":"477","language":[{"iso":"ger"}]},{"_id":"6734","department":[{"_id":"19"},{"_id":"200"},{"_id":"475"},{"_id":"202"}],"user_id":"186","language":[{"iso":"eng"}],"publication":"Oxford Bulletin of Economics and Statistics","type":"journal_article","status":"public","date_updated":"2022-01-06T07:03:17Z","volume":81,"author":[{"first_name":"Thomas","full_name":"Gries, Thomas","id":"186","last_name":"Gries"},{"first_name":"Marlon","last_name":"Fritz","full_name":"Fritz, Marlon"},{"last_name":"Yuanhua","full_name":"Yuanhua, Feng","first_name":"Feng"}],"date_created":"2019-01-15T11:16:38Z","title":"Growth Trends and Systematic Patterns of Boom and Busts –Testing 200 Years of Business Cycle Dynamics","doi":"10.1111/obes.12267","issue":"1","year":"2019","page":"62-78","intvolume":"        81","citation":{"ama":"Gries T, Fritz M, Yuanhua F. Growth Trends and Systematic Patterns of Boom and Busts –Testing 200 Years of Business Cycle Dynamics. <i>Oxford Bulletin of Economics and Statistics</i>. 2019;81(1):62-78. doi:<a href=\"https://doi.org/10.1111/obes.12267\">10.1111/obes.12267</a>","ieee":"T. Gries, M. Fritz, and F. Yuanhua, “Growth Trends and Systematic Patterns of Boom and Busts –Testing 200 Years of Business Cycle Dynamics,” <i>Oxford Bulletin of Economics and Statistics</i>, vol. 81, no. 1, pp. 62–78, 2019.","chicago":"Gries, Thomas, Marlon Fritz, and Feng Yuanhua. “Growth Trends and Systematic Patterns of Boom and Busts –Testing 200 Years of Business Cycle Dynamics.” <i>Oxford Bulletin of Economics and Statistics</i> 81, no. 1 (2019): 62–78. <a href=\"https://doi.org/10.1111/obes.12267\">https://doi.org/10.1111/obes.12267</a>.","mla":"Gries, Thomas, et al. “Growth Trends and Systematic Patterns of Boom and Busts –Testing 200 Years of Business Cycle Dynamics.” <i>Oxford Bulletin of Economics and Statistics</i>, vol. 81, no. 1, 2019, pp. 62–78, doi:<a href=\"https://doi.org/10.1111/obes.12267\">10.1111/obes.12267</a>.","bibtex":"@article{Gries_Fritz_Yuanhua_2019, title={Growth Trends and Systematic Patterns of Boom and Busts –Testing 200 Years of Business Cycle Dynamics}, volume={81}, DOI={<a href=\"https://doi.org/10.1111/obes.12267\">10.1111/obes.12267</a>}, number={1}, journal={Oxford Bulletin of Economics and Statistics}, author={Gries, Thomas and Fritz, Marlon and Yuanhua, Feng}, year={2019}, pages={62–78} }","short":"T. Gries, M. Fritz, F. Yuanhua, Oxford Bulletin of Economics and Statistics 81 (2019) 62–78.","apa":"Gries, T., Fritz, M., &#38; Yuanhua, F. (2019). Growth Trends and Systematic Patterns of Boom and Busts –Testing 200 Years of Business Cycle Dynamics. <i>Oxford Bulletin of Economics and Statistics</i>, <i>81</i>(1), 62–78. <a href=\"https://doi.org/10.1111/obes.12267\">https://doi.org/10.1111/obes.12267</a>"}},{"language":[{"iso":"eng"}],"user_id":"16205","department":[{"_id":"276"}],"project":[{"name":"SFB 901","_id":"1"},{"name":"SFB 901 - Project Area A","_id":"2"},{"name":"SFB 901 - Subproject A4","_id":"8"}],"_id":"6856","status":"public","type":"conference","publication":"Wirtschaftsinformatik Proceedings 2019","conference":{"name":"Wirtschaftsinformatik","location":"Siegen, Germany"},"title":"Heart over Heels? An Empirical Analysis of the Relationship between Emotions and Review Helpfulness for Experience and Credence Goods","date_created":"2019-01-17T14:39:49Z","author":[{"first_name":"Michelle","full_name":"Müller, Michelle","last_name":"Müller"},{"last_name":"Gutt","id":"14368","full_name":"Gutt, Dominik","first_name":"Dominik"}],"date_updated":"2022-01-06T07:03:22Z","citation":{"ama":"Müller M, Gutt D. Heart over Heels? An Empirical Analysis of the Relationship between Emotions and Review Helpfulness for Experience and Credence Goods. In: <i>Wirtschaftsinformatik Proceedings 2019</i>. ; 2019.","chicago":"Müller, Michelle, and Dominik Gutt. “Heart over Heels? An Empirical Analysis of the Relationship between Emotions and Review Helpfulness for Experience and Credence Goods.” In <i>Wirtschaftsinformatik Proceedings 2019</i>, 2019.","ieee":"M. Müller and D. Gutt, “Heart over Heels? An Empirical Analysis of the Relationship between Emotions and Review Helpfulness for Experience and Credence Goods,” in <i>Wirtschaftsinformatik Proceedings 2019</i>, Siegen, Germany, 2019.","bibtex":"@inproceedings{Müller_Gutt_2019, title={Heart over Heels? An Empirical Analysis of the Relationship between Emotions and Review Helpfulness for Experience and Credence Goods}, booktitle={Wirtschaftsinformatik Proceedings 2019}, author={Müller, Michelle and Gutt, Dominik}, year={2019} }","mla":"Müller, Michelle, and Dominik Gutt. “Heart over Heels? An Empirical Analysis of the Relationship between Emotions and Review Helpfulness for Experience and Credence Goods.” <i>Wirtschaftsinformatik Proceedings 2019</i>, 2019.","short":"M. Müller, D. Gutt, in: Wirtschaftsinformatik Proceedings 2019, 2019.","apa":"Müller, M., &#38; Gutt, D. (2019). Heart over Heels? An Empirical Analysis of the Relationship between Emotions and Review Helpfulness for Experience and Credence Goods. In <i>Wirtschaftsinformatik Proceedings 2019</i>. Siegen, Germany."},"year":"2019"},{"date_updated":"2022-01-06T07:03:22Z","author":[{"id":"32441","full_name":"Poniatowski, Martin","last_name":"Poniatowski","first_name":"Martin"},{"id":"32456","full_name":"Neumann, Jürgen","last_name":"Neumann","first_name":"Jürgen"},{"first_name":"Thomas","full_name":"Görzen, Thomas","id":"47700","last_name":"Görzen"},{"last_name":"Kundisch","id":"21117","full_name":"Kundisch, Dennis","first_name":"Dennis"}],"date_created":"2019-01-17T14:46:50Z","title":"A Semi-Automated Approach for Generating Online Review Templates, ","conference":{"name":"Wirtschaftsinformatik","location":"Siegen, Germany"},"year":"2019","citation":{"ama":"Poniatowski M, Neumann J, Görzen T, Kundisch D. A Semi-Automated Approach for Generating Online Review Templates, . In: <i>Wirtschaftsinformatik Proceedings 2019</i>. ; 2019.","chicago":"Poniatowski, Martin, Jürgen Neumann, Thomas Görzen, and Dennis Kundisch. “A Semi-Automated Approach for Generating Online Review Templates, .” In <i>Wirtschaftsinformatik Proceedings 2019</i>, 2019.","ieee":"M. Poniatowski, J. Neumann, T. Görzen, and D. Kundisch, “A Semi-Automated Approach for Generating Online Review Templates, ,” in <i>Wirtschaftsinformatik Proceedings 2019</i>, Siegen, Germany, 2019.","short":"M. Poniatowski, J. Neumann, T. Görzen, D. Kundisch, in: Wirtschaftsinformatik Proceedings 2019, 2019.","bibtex":"@inproceedings{Poniatowski_Neumann_Görzen_Kundisch_2019, title={A Semi-Automated Approach for Generating Online Review Templates, }, booktitle={Wirtschaftsinformatik Proceedings 2019}, author={Poniatowski, Martin and Neumann, Jürgen and Görzen, Thomas and Kundisch, Dennis}, year={2019} }","mla":"Poniatowski, Martin, et al. “A Semi-Automated Approach for Generating Online Review Templates, .” <i>Wirtschaftsinformatik Proceedings 2019</i>, 2019.","apa":"Poniatowski, M., Neumann, J., Görzen, T., &#38; Kundisch, D. (2019). A Semi-Automated Approach for Generating Online Review Templates, . In <i>Wirtschaftsinformatik Proceedings 2019</i>. Siegen, Germany."},"_id":"6857","project":[{"_id":"1","name":"SFB 901"},{"name":"SFB 901 - Project Area A","_id":"2"},{"name":"SFB 901 - Subproject A4","_id":"8"}],"department":[{"_id":"276"}],"user_id":"477","language":[{"iso":"eng"}],"publication":"Wirtschaftsinformatik Proceedings 2019","type":"conference","status":"public"},{"file":[{"content_type":"application/pdf","relation":"main_file","date_created":"2019-01-17T15:49:37Z","creator":"hafifi","date_updated":"2019-01-17T15:49:37Z","access_level":"open_access","file_id":"6861","file_name":"globecom.pdf","file_size":320283}],"status":"public","type":"conference","publication":"2019 16th IEEE Annual Consumer Communications & Networking Conference (CCNC2019)","ddc":["000"],"file_date_updated":"2019-01-17T15:49:37Z","language":[{"iso":"eng"}],"project":[{"_id":"27","name":"Akustische Sensornetzwerke - Teilprojekt "},{"_id":"27","name":"Akustische Sensornetzwerke - Teilprojekt \"Verteilte akustische Signalverarbeitung über funkbasierte Sensornetzwerke"}],"_id":"6860","user_id":"65718","department":[{"_id":"75"}],"place":"Las Vegas","year":"2019","citation":{"chicago":"Afifi, Haitham, and Holger Karl. “Power Allocation with a Wireless Multi-Cast Aware Routing for Virtual Network Embedding.” In <i>2019 16th IEEE Annual Consumer Communications &#38; Networking Conference (CCNC2019)</i>. Las Vegas: IEEE, n.d.","ieee":"H. Afifi and H. Karl, “Power Allocation with a Wireless Multi-cast Aware Routing for Virtual Network Embedding,” in <i>2019 16th IEEE Annual Consumer Communications &#38; Networking Conference (CCNC2019)</i>.","ama":"Afifi H, Karl H. Power Allocation with a Wireless Multi-cast Aware Routing for Virtual Network Embedding. In: <i>2019 16th IEEE Annual Consumer Communications &#38; Networking Conference (CCNC2019)</i>. Las Vegas: IEEE.","apa":"Afifi, H., &#38; Karl, H. (n.d.). Power Allocation with a Wireless Multi-cast Aware Routing for Virtual Network Embedding. In <i>2019 16th IEEE Annual Consumer Communications &#38; Networking Conference (CCNC2019)</i>. Las Vegas: IEEE.","short":"H. Afifi, H. Karl, in: 2019 16th IEEE Annual Consumer Communications &#38; Networking Conference (CCNC2019), IEEE, Las Vegas, n.d.","bibtex":"@inproceedings{Afifi_Karl, place={Las Vegas}, title={Power Allocation with a Wireless Multi-cast Aware Routing for Virtual Network Embedding}, booktitle={2019 16th IEEE Annual Consumer Communications &#38; Networking Conference (CCNC2019)}, publisher={IEEE}, author={Afifi, Haitham and Karl, Holger} }","mla":"Afifi, Haitham, and Holger Karl. “Power Allocation with a Wireless Multi-Cast Aware Routing for Virtual Network Embedding.” <i>2019 16th IEEE Annual Consumer Communications &#38; Networking Conference (CCNC2019)</i>, IEEE."},"publication_status":"accepted","has_accepted_license":"1","title":"Power Allocation with a Wireless Multi-cast Aware Routing for Virtual Network Embedding","oa":"1","publisher":"IEEE","date_updated":"2022-01-06T07:03:22Z","author":[{"id":"65718","full_name":"Afifi, Haitham","last_name":"Afifi","first_name":"Haitham"},{"first_name":"Holger","last_name":"Karl","full_name":"Karl, Holger","id":"126"}],"date_created":"2019-01-17T15:51:34Z"},{"date_updated":"2022-01-06T07:03:25Z","author":[{"first_name":"Thorsten","last_name":"Götte","id":"34727","full_name":"Götte, Thorsten"},{"first_name":"Vipin Ravindran","last_name":"Vijayalakshmi","full_name":"Vijayalakshmi, Vipin Ravindran"},{"first_name":"Christian","id":"20792","full_name":"Scheideler, Christian","last_name":"Scheideler"}],"conference":{"end_date":"24.05.19","location":"Rio de Janeiro, Brazil","name":"2019 IEEE 33rd International Parallel  and Distributed Processing Symposium (IPDPS '19)","start_date":"20.05.19"},"has_accepted_license":"1","publication_status":"accepted","citation":{"ama":"Götte T, Vijayalakshmi VR, Scheideler C. Always be Two Steps Ahead of Your Enemy - Maintaining a Routable Overlay under Massive Churn with an Almost Up-to-date Adversary. In: <i>Proceedings of the 2019 IEEE 33rd International Parallel  and Distributed Processing Symposium (IPDPS ’19)</i>. IEEE.","chicago":"Götte, Thorsten, Vipin Ravindran Vijayalakshmi, and Christian Scheideler. “Always Be Two Steps Ahead of Your Enemy - Maintaining a Routable Overlay under Massive Churn with an Almost Up-to-Date Adversary.” In <i>Proceedings of the 2019 IEEE 33rd International Parallel  and Distributed Processing Symposium (IPDPS ’19)</i>. IEEE, n.d.","ieee":"T. Götte, V. R. Vijayalakshmi, and C. Scheideler, “Always be Two Steps Ahead of Your Enemy - Maintaining a Routable Overlay under Massive Churn with an Almost Up-to-date Adversary,” in <i>Proceedings of the 2019 IEEE 33rd International Parallel  and Distributed Processing Symposium (IPDPS ’19)</i>, Rio de Janeiro, Brazil.","apa":"Götte, T., Vijayalakshmi, V. R., &#38; Scheideler, C. (n.d.). Always be Two Steps Ahead of Your Enemy - Maintaining a Routable Overlay under Massive Churn with an Almost Up-to-date Adversary. In <i>Proceedings of the 2019 IEEE 33rd International Parallel  and Distributed Processing Symposium (IPDPS ’19)</i>. Rio de Janeiro, Brazil: IEEE.","short":"T. Götte, V.R. Vijayalakshmi, C. Scheideler, in: Proceedings of the 2019 IEEE 33rd International Parallel  and Distributed Processing Symposium (IPDPS ’19), IEEE, n.d.","bibtex":"@inproceedings{Götte_Vijayalakshmi_Scheideler, title={Always be Two Steps Ahead of Your Enemy - Maintaining a Routable Overlay under Massive Churn with an Almost Up-to-date Adversary}, booktitle={Proceedings of the 2019 IEEE 33rd International Parallel  and Distributed Processing Symposium (IPDPS ’19)}, publisher={IEEE}, author={Götte, Thorsten and Vijayalakshmi, Vipin Ravindran and Scheideler, Christian} }","mla":"Götte, Thorsten, et al. “Always Be Two Steps Ahead of Your Enemy - Maintaining a Routable Overlay under Massive Churn with an Almost Up-to-Date Adversary.” <i>Proceedings of the 2019 IEEE 33rd International Parallel  and Distributed Processing Symposium (IPDPS ’19)</i>, IEEE."},"_id":"6976","project":[{"_id":"1","name":"SFB 901"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"13","name":"SFB 901 - Subproject C1"}],"department":[{"_id":"79"}],"user_id":"34727","file_date_updated":"2019-01-26T16:09:08Z","type":"conference","status":"public","publisher":"IEEE","date_created":"2019-01-24T18:53:11Z","title":"Always be Two Steps Ahead of Your Enemy - Maintaining a Routable Overlay under Massive Churn with an Almost Up-to-date Adversary","year":"2019","ddc":["000"],"language":[{"iso":"eng"}],"publication":"Proceedings of the 2019 IEEE 33rd International Parallel  and Distributed Processing Symposium (IPDPS '19)","abstract":[{"lang":"eng","text":"We investigate the maintenance of overlay networks under massive churn, i.e.\r\nnodes joining and leaving the network. We assume an adversary that may churn a\r\nconstant fraction $\\alpha n$ of nodes over the course of $\\mathcal{O}(\\log n)$\r\nrounds. In particular, the adversary has an almost up-to-date information of\r\nthe network topology as it can observe an only slightly outdated topology that\r\nis at least $2$ rounds old. Other than that, we only have the provably minimal\r\nrestriction that new nodes can only join the network via nodes that have taken\r\npart in the network for at least one round.\r\n  Our contributions are as follows: First, we show that it is impossible to\r\nmaintain a connected topology if adversary has up-to-date information about the\r\nnodes' connections. Further, we show that our restriction concerning the join\r\nis also necessary. As our main result present an algorithm that constructs a\r\nnew overlay- completely independent of all previous overlays - every $2$\r\nrounds. Furthermore, each node sends and receives only $\\mathcal{O}(\\log^3 n)$\r\nmessages each round. As part of our solution we propose the Linearized DeBruijn\r\nSwarm (LDS), a highly churn resistant overlay, which will be maintained by the\r\nalgorithm. However, our approaches can be transferred to a variety of classical\r\nP2P Topologies where nodes are mapped into the $[0,1)$-interval."}],"file":[{"relation":"main_file","success":1,"content_type":"application/pdf","access_level":"closed","file_id":"7007","file_name":"Always_be_Two_Steps_Ahead_of_Your_Enemy.pdf","file_size":638020,"date_created":"2019-01-26T16:09:08Z","creator":"thgoette","date_updated":"2019-01-26T16:09:08Z"}]},{"doi":"10.1109/cahpc.2018.8645850","title":"Energy Efficient Parallel K-Means Clustering for an Intel® Hybrid Multi-Chip Package","author":[{"full_name":"Souza, Matheus A.","last_name":"Souza","first_name":"Matheus A."},{"full_name":"Maciel, Lucas A.","last_name":"Maciel","first_name":"Lucas A."},{"last_name":"Penna","full_name":"Penna, Pedro Henrique","first_name":"Pedro Henrique"},{"last_name":"Freitas","full_name":"Freitas, Henrique C.","first_name":"Henrique C."}],"date_created":"2020-04-06T09:41:41Z","date_updated":"2022-01-06T06:52:50Z","citation":{"mla":"Souza, Matheus A., et al. “Energy Efficient Parallel K-Means Clustering for an Intel® Hybrid Multi-Chip Package.” <i>2018 30th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)</i>, 2019, doi:<a href=\"https://doi.org/10.1109/cahpc.2018.8645850\">10.1109/cahpc.2018.8645850</a>.","bibtex":"@inproceedings{Souza_Maciel_Penna_Freitas_2019, title={Energy Efficient Parallel K-Means Clustering for an Intel® Hybrid Multi-Chip Package}, DOI={<a href=\"https://doi.org/10.1109/cahpc.2018.8645850\">10.1109/cahpc.2018.8645850</a>}, booktitle={2018 30th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)}, author={Souza, Matheus A. and Maciel, Lucas A. and Penna, Pedro Henrique and Freitas, Henrique C.}, year={2019} }","short":"M.A. Souza, L.A. Maciel, P.H. Penna, H.C. Freitas, in: 2018 30th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), 2019.","apa":"Souza, M. A., Maciel, L. A., Penna, P. H., &#38; Freitas, H. C. (2019). Energy Efficient Parallel K-Means Clustering for an Intel® Hybrid Multi-Chip Package. In <i>2018 30th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)</i>. <a href=\"https://doi.org/10.1109/cahpc.2018.8645850\">https://doi.org/10.1109/cahpc.2018.8645850</a>","ieee":"M. A. Souza, L. A. Maciel, P. H. Penna, and H. C. Freitas, “Energy Efficient Parallel K-Means Clustering for an Intel® Hybrid Multi-Chip Package,” in <i>2018 30th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)</i>, 2019.","chicago":"Souza, Matheus A., Lucas A. Maciel, Pedro Henrique Penna, and Henrique C. Freitas. “Energy Efficient Parallel K-Means Clustering for an Intel® Hybrid Multi-Chip Package.” In <i>2018 30th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)</i>, 2019. <a href=\"https://doi.org/10.1109/cahpc.2018.8645850\">https://doi.org/10.1109/cahpc.2018.8645850</a>.","ama":"Souza MA, Maciel LA, Penna PH, Freitas HC. Energy Efficient Parallel K-Means Clustering for an Intel® Hybrid Multi-Chip Package. In: <i>2018 30th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)</i>. ; 2019. doi:<a href=\"https://doi.org/10.1109/cahpc.2018.8645850\">10.1109/cahpc.2018.8645850</a>"},"year":"2019","publication_status":"published","publication_identifier":{"isbn":["9781538677698"]},"language":[{"iso":"eng"}],"keyword":["pc2-harp-ressources"],"user_id":"61189","_id":"16411","status":"public","abstract":[{"text":"FPGA devices have been proving to be good candidates to accelerate applications from different research topics. For instance, machine learning applications such as K-Means clustering usually relies on large amount of data to be processed, and, despite the performance offered by other architectures, FPGAs can offer better energy efficiency. With that in mind, Intel has launched a platform that integrates a multicore and an FPGA in the same package, enabling low latency and coherent fine-grained data offload. In this paper, we present a parallel implementation of the K-Means clustering algorithm, for this novel platform, using OpenCL language, and compared it against other platforms. We found that the CPU+FPGA platform was more energy efficient than the CPU-only approach from 70.71% to 85.92%, with Standard and Tiny input sizes respectively, and up to 68.21% of performance improvement was obtained with Tiny input size. Furthermore, it was up to 7.2×more energy efficient than an Intel® Xeon Phi ™, 21.5×than a cluster of Raspberry Pi boards, and 3.8×than the low-power MPPA-256 architecture, when the Standard input size was used.","lang":"eng"}],"type":"conference","publication":"2018 30th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)"},{"_id":"16413","user_id":"61189","keyword":["pc2-harp-ressources"],"language":[{"iso":"eng"}],"publication":"2018 IEEE 36th International Conference on Computer Design (ICCD)","type":"conference","abstract":[{"text":"In recent years, FPGAs have been successfully employed for the implementation of efficient, application-specific accelerators for a wide range of machine learning tasks. In this work, we consider probabilistic models, namely, (Mixed) Sum-Product Networks (SPN), a deep architecture that can provide tractable inference for multivariate distributions over mixed data-sources. We develop a fully pipelined FPGA accelerator architecture, including a pipelined interface to external memory, for the inference in (mixed) SPNs. To meet the precision constraints of SPNs, all computations are conducted using double-precision floating point arithmetic. Starting from an input description, the custom FPGA-accelerator is synthesized fully automatically by our tool flow. To the best of our knowledge, this work is the first approach to offload the SPN inference problem to FPGA-based accelerators. Our evaluation shows that the SPN inference problem benefits from offloading to our pipelined FPGA accelerator architecture.","lang":"eng"}],"status":"public","date_updated":"2022-01-06T06:52:50Z","date_created":"2020-04-06T10:33:58Z","author":[{"full_name":"Sommer, Lukas","last_name":"Sommer","first_name":"Lukas"},{"first_name":"Julian","full_name":"Oppermann, Julian","last_name":"Oppermann"},{"full_name":"Molina, Alejandro","last_name":"Molina","first_name":"Alejandro"},{"first_name":"Carsten","last_name":"Binnig","full_name":"Binnig, Carsten"},{"first_name":"Kristian","full_name":"Kersting, Kristian","last_name":"Kersting"},{"first_name":"Andreas","last_name":"Koch","full_name":"Koch, Andreas"}],"title":"Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-Based Accelerators","doi":"10.1109/iccd.2018.00060","publication_identifier":{"isbn":["9781538684771"]},"publication_status":"published","year":"2019","citation":{"bibtex":"@inproceedings{Sommer_Oppermann_Molina_Binnig_Kersting_Koch_2019, title={Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-Based Accelerators}, DOI={<a href=\"https://doi.org/10.1109/iccd.2018.00060\">10.1109/iccd.2018.00060</a>}, booktitle={2018 IEEE 36th International Conference on Computer Design (ICCD)}, author={Sommer, Lukas and Oppermann, Julian and Molina, Alejandro and Binnig, Carsten and Kersting, Kristian and Koch, Andreas}, year={2019} }","short":"L. Sommer, J. Oppermann, A. Molina, C. Binnig, K. Kersting, A. Koch, in: 2018 IEEE 36th International Conference on Computer Design (ICCD), 2019.","mla":"Sommer, Lukas, et al. “Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-Based Accelerators.” <i>2018 IEEE 36th International Conference on Computer Design (ICCD)</i>, 2019, doi:<a href=\"https://doi.org/10.1109/iccd.2018.00060\">10.1109/iccd.2018.00060</a>.","apa":"Sommer, L., Oppermann, J., Molina, A., Binnig, C., Kersting, K., &#38; Koch, A. (2019). Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-Based Accelerators. In <i>2018 IEEE 36th International Conference on Computer Design (ICCD)</i>. <a href=\"https://doi.org/10.1109/iccd.2018.00060\">https://doi.org/10.1109/iccd.2018.00060</a>","ama":"Sommer L, Oppermann J, Molina A, Binnig C, Kersting K, Koch A. Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-Based Accelerators. In: <i>2018 IEEE 36th International Conference on Computer Design (ICCD)</i>. ; 2019. doi:<a href=\"https://doi.org/10.1109/iccd.2018.00060\">10.1109/iccd.2018.00060</a>","ieee":"L. Sommer, J. Oppermann, A. Molina, C. Binnig, K. Kersting, and A. Koch, “Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-Based Accelerators,” in <i>2018 IEEE 36th International Conference on Computer Design (ICCD)</i>, 2019.","chicago":"Sommer, Lukas, Julian Oppermann, Alejandro Molina, Carsten Binnig, Kristian Kersting, and Andreas Koch. “Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-Based Accelerators.” In <i>2018 IEEE 36th International Conference on Computer Design (ICCD)</i>, 2019. <a href=\"https://doi.org/10.1109/iccd.2018.00060\">https://doi.org/10.1109/iccd.2018.00060</a>."}},{"type":"mastersthesis","year":"2019","status":"public","citation":{"bibtex":"@book{Lienen_2019, title={Automated Feature Engineering on Time Series Data}, author={Lienen, Julian}, year={2019} }","short":"J. Lienen, Automated Feature Engineering on Time Series Data, 2019.","mla":"Lienen, Julian. <i>Automated Feature Engineering on Time Series Data</i>. 2019.","apa":"Lienen, J. (2019). <i>Automated Feature Engineering on Time Series Data</i>.","ama":"Lienen J. <i>Automated Feature Engineering on Time Series Data</i>.; 2019.","chicago":"Lienen, Julian. <i>Automated Feature Engineering on Time Series Data</i>, 2019.","ieee":"J. Lienen, <i>Automated Feature Engineering on Time Series Data</i>. 2019."},"_id":"16415","date_updated":"2022-01-06T06:52:50Z","user_id":"44040","author":[{"first_name":"Julian","last_name":"Lienen","full_name":"Lienen, Julian","id":"44040"}],"date_created":"2020-04-06T11:44:17Z","title":"Automated Feature Engineering on Time Series Data","language":[{"iso":"eng"}]},{"_id":"16417","user_id":"61189","keyword":["pc2-harp-ressources"],"language":[{"iso":"eng"}],"publication":"Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays","type":"conference","abstract":[{"lang":"eng","text":"The performance of High-Level Synthesis (HLS) applications with irregular data structures is limited by its imperative programming paradigm like C/C++. In this paper, we show that constructing concurrent data structures with channels, a programming construct derived from CSP (communicating sequential processes) paradigm, is an effective approach to improve the performance of these applications. We evaluate concurrent data structure for FPGA by synthesizing a K-means clustering algorithm on the Intel HARP2 platform. A fully pipelined KMC processing element can be synthesized from OpenCL with the help of a SPSC (single-producer-single-consumer) queue and stack built from channels, achieving 15.2x speedup over a sequential baseline. The number of processing element can be scaled up by leveraging a MPMC (multiple-producer-multiple-consumer) stack with work distribution for dynamic load balance. Evaluation shows that an additional 3.5x speedup can be achieved when 4 processing element is instantiated. These results show that the concurrent data structure built with channels has great potential for improving the parallelism of HLS applications. We hope that our study will stimulate further research into the potential of channel-based HLS."}],"status":"public","date_updated":"2022-01-06T06:52:50Z","date_created":"2020-04-06T11:53:34Z","author":[{"last_name":"Yan","full_name":"Yan, Hui","first_name":"Hui"},{"first_name":"Zhaoshi","last_name":"Li","full_name":"Li, Zhaoshi"},{"last_name":"Liu","full_name":"Liu, Leibo","first_name":"Leibo"},{"full_name":"Yin, Shouyi","last_name":"Yin","first_name":"Shouyi"},{"first_name":"Shaojun","last_name":"Wei","full_name":"Wei, Shaojun"}],"title":"Constructing Concurrent Data Structures on FPGA with Channels","doi":"10.1145/3289602.3293921","publication_identifier":{"isbn":["9781450361378"]},"publication_status":"published","year":"2019","citation":{"apa":"Yan, H., Li, Z., Liu, L., Yin, S., &#38; Wei, S. (2019). Constructing Concurrent Data Structures on FPGA with Channels. In <i>Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays</i>. <a href=\"https://doi.org/10.1145/3289602.3293921\">https://doi.org/10.1145/3289602.3293921</a>","mla":"Yan, Hui, et al. “Constructing Concurrent Data Structures on FPGA with Channels.” <i>Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays</i>, 2019, doi:<a href=\"https://doi.org/10.1145/3289602.3293921\">10.1145/3289602.3293921</a>.","short":"H. Yan, Z. Li, L. Liu, S. Yin, S. Wei, in: Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019.","bibtex":"@inproceedings{Yan_Li_Liu_Yin_Wei_2019, title={Constructing Concurrent Data Structures on FPGA with Channels}, DOI={<a href=\"https://doi.org/10.1145/3289602.3293921\">10.1145/3289602.3293921</a>}, booktitle={Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays}, author={Yan, Hui and Li, Zhaoshi and Liu, Leibo and Yin, Shouyi and Wei, Shaojun}, year={2019} }","ama":"Yan H, Li Z, Liu L, Yin S, Wei S. Constructing Concurrent Data Structures on FPGA with Channels. In: <i>Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays</i>. ; 2019. doi:<a href=\"https://doi.org/10.1145/3289602.3293921\">10.1145/3289602.3293921</a>","chicago":"Yan, Hui, Zhaoshi Li, Leibo Liu, Shouyi Yin, and Shaojun Wei. “Constructing Concurrent Data Structures on FPGA with Channels.” In <i>Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays</i>, 2019. <a href=\"https://doi.org/10.1145/3289602.3293921\">https://doi.org/10.1145/3289602.3293921</a>.","ieee":"H. Yan, Z. Li, L. Liu, S. Yin, and S. Wei, “Constructing Concurrent Data Structures on FPGA with Channels,” in <i>Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays</i>, 2019."}},{"title":"Combining Multiple Optimized FPGA-based Pulsar Search Modules Using OpenCL","doi":"10.1142/s2251171719500089","date_updated":"2022-01-06T06:52:50Z","date_created":"2020-04-06T12:00:06Z","author":[{"last_name":"Wang","full_name":"Wang, Haomiao","first_name":"Haomiao"},{"last_name":"Thiagaraj","full_name":"Thiagaraj, Prabu","first_name":"Prabu"},{"full_name":"Sinnen, Oliver","last_name":"Sinnen","first_name":"Oliver"}],"year":"2019","citation":{"ama":"Wang H, Thiagaraj P, Sinnen O. Combining Multiple Optimized FPGA-based Pulsar Search Modules Using OpenCL. <i>Journal of Astronomical Instrumentation</i>. 2019. doi:<a href=\"https://doi.org/10.1142/s2251171719500089\">10.1142/s2251171719500089</a>","chicago":"Wang, Haomiao, Prabu Thiagaraj, and Oliver Sinnen. “Combining Multiple Optimized FPGA-Based Pulsar Search Modules Using OpenCL.” <i>Journal of Astronomical Instrumentation</i>, 2019. <a href=\"https://doi.org/10.1142/s2251171719500089\">https://doi.org/10.1142/s2251171719500089</a>.","ieee":"H. Wang, P. Thiagaraj, and O. Sinnen, “Combining Multiple Optimized FPGA-based Pulsar Search Modules Using OpenCL,” <i>Journal of Astronomical Instrumentation</i>, 2019.","bibtex":"@article{Wang_Thiagaraj_Sinnen_2019, title={Combining Multiple Optimized FPGA-based Pulsar Search Modules Using OpenCL}, DOI={<a href=\"https://doi.org/10.1142/s2251171719500089\">10.1142/s2251171719500089</a>}, number={1950008}, journal={Journal of Astronomical Instrumentation}, author={Wang, Haomiao and Thiagaraj, Prabu and Sinnen, Oliver}, year={2019} }","short":"H. Wang, P. Thiagaraj, O. Sinnen, Journal of Astronomical Instrumentation (2019).","mla":"Wang, Haomiao, et al. “Combining Multiple Optimized FPGA-Based Pulsar Search Modules Using OpenCL.” <i>Journal of Astronomical Instrumentation</i>, 1950008, 2019, doi:<a href=\"https://doi.org/10.1142/s2251171719500089\">10.1142/s2251171719500089</a>.","apa":"Wang, H., Thiagaraj, P., &#38; Sinnen, O. (2019). Combining Multiple Optimized FPGA-based Pulsar Search Modules Using OpenCL. <i>Journal of Astronomical Instrumentation</i>. <a href=\"https://doi.org/10.1142/s2251171719500089\">https://doi.org/10.1142/s2251171719500089</a>"},"publication_status":"published","publication_identifier":{"issn":["2251-1717","2251-1725"]},"article_number":"1950008","keyword":["pc2-harp-ressources"],"language":[{"iso":"eng"}],"_id":"16420","user_id":"61189","abstract":[{"lang":"eng","text":"<jats:p> Field-Programmable Gate Arrays (FPGAs) are widely used in the central signal processing design of the Square Kilometer Array (SKA) as hardware accelerators. The frequency domain acceleration search (FDAS) module is an important part of the SKA1-MID pulsar search engine. To develop for a yet to be finalized hardware, for cross-discipline interoperability and to achieve fast prototyping, OpenCL as a high-level FPGA synthesis approaches employed to create the sub-modules of FDAS. The FT convolution and the harmonic-summing plus some other minor sub-modules are elements in the FDAS module that have been well-optimized separately before. In this paper, we explore the design space of combining well-optimized designs, dealing with the ensuing need to trade-off and compromise. Pipeline computing is employed to handle multiple input arrays at high speed. The hardware target is to employ multiple high-end FPGAs to process the combined FDAS module. The results show interesting consequences, where the best individual solutions are not necessarily the best solutions for the speed of a pipeline where FPGA resources and memory bandwidth need to be shared. By proposing multiple buffering techniques to the pipeline, the combined FDAS module can achieve up to 2[Formula: see text] speedup over implementations without pipeline computing. We perform an extensive experimental evaluation on multiple high-end FPGA cards hosted in a workstation and compare to a technology comparable mid-range GPU. </jats:p>"}],"status":"public","type":"journal_article","publication":"Journal of Astronomical Instrumentation"},{"abstract":[{"lang":"eng","text":"<jats:p>Intel recently introduced the Heterogeneous Architecture Research Platform, HARP. In this platform, the Central Processing Unit and a Field-Programmable Gate Array are connected through a high-bandwidth, low-latency interconnect and both share DRAM memory. For this platform, Open Computing Language (OpenCL), a High-Level Synthesis (HLS) language, is made available. By making use of HLS, a faster design cycle can be achieved compared to programming in a traditional hardware description language. This, however, comes at the cost of having less control over the hardware implementation. We will investigate how OpenCL can be applied to implement a real-time guided image filter on the HARP platform. In the first phase, the performance-critical parameters of the OpenCL programming model are defined using several specialized benchmarks. In a second phase, the guided image filter algorithm is implemented using the insights gained in the first phase. Both a floating-point and a fixed-point implementation were developed for this algorithm, based on a sliding window implementation. This resulted in a maximum floating-point performance of 135 GFLOPS, a maximum fixed-point performance of 430 GOPS and a throughput of HD color images at 74 frames per second.</jats:p>"}],"status":"public","type":"journal_article","publication":"Algorithms","article_number":"149","keyword":["pc2-harp-ressources"],"language":[{"iso":"eng"}],"_id":"16422","user_id":"61189","year":"2019","citation":{"chicago":"Faict, Thomas, Erik H. D’Hollander, and Bart Goossens. “Mapping a Guided Image Filter on the HARP Reconfigurable Architecture Using OpenCL.” <i>Algorithms</i>, 2019. <a href=\"https://doi.org/10.3390/a12080149\">https://doi.org/10.3390/a12080149</a>.","ieee":"T. Faict, E. H. D’Hollander, and B. Goossens, “Mapping a Guided Image Filter on the HARP Reconfigurable Architecture Using OpenCL,” <i>Algorithms</i>, 2019.","ama":"Faict T, D’Hollander EH, Goossens B. Mapping a Guided Image Filter on the HARP Reconfigurable Architecture Using OpenCL. <i>Algorithms</i>. 2019. doi:<a href=\"https://doi.org/10.3390/a12080149\">10.3390/a12080149</a>","mla":"Faict, Thomas, et al. “Mapping a Guided Image Filter on the HARP Reconfigurable Architecture Using OpenCL.” <i>Algorithms</i>, 149, 2019, doi:<a href=\"https://doi.org/10.3390/a12080149\">10.3390/a12080149</a>.","short":"T. Faict, E.H. D’Hollander, B. Goossens, Algorithms (2019).","bibtex":"@article{Faict_D’Hollander_Goossens_2019, title={Mapping a Guided Image Filter on the HARP Reconfigurable Architecture Using OpenCL}, DOI={<a href=\"https://doi.org/10.3390/a12080149\">10.3390/a12080149</a>}, number={149}, journal={Algorithms}, author={Faict, Thomas and D’Hollander, Erik H. and Goossens, Bart}, year={2019} }","apa":"Faict, T., D’Hollander, E. H., &#38; Goossens, B. (2019). Mapping a Guided Image Filter on the HARP Reconfigurable Architecture Using OpenCL. <i>Algorithms</i>. <a href=\"https://doi.org/10.3390/a12080149\">https://doi.org/10.3390/a12080149</a>"},"publication_status":"published","publication_identifier":{"issn":["1999-4893"]},"title":"Mapping a Guided Image Filter on the HARP Reconfigurable Architecture Using OpenCL","doi":"10.3390/a12080149","date_updated":"2022-01-06T06:52:50Z","date_created":"2020-04-06T12:08:24Z","author":[{"full_name":"Faict, Thomas","last_name":"Faict","first_name":"Thomas"},{"last_name":"D’Hollander","full_name":"D’Hollander, Erik H.","first_name":"Erik H."},{"first_name":"Bart","full_name":"Goossens, Bart","last_name":"Goossens"}]},{"year":"2019","citation":{"chicago":"Rodríguez, Andrés, Angeles Navarro, Rafael Asenjo, Francisco Corbera, Rubén Gran, Darío Suárez, and Jose Nunez-Yanez. “Parallel Multiprocessing and Scheduling on the Heterogeneous Xeon+FPGA Platform.” <i>The Journal of Supercomputing</i>, 2019. <a href=\"https://doi.org/10.1007/s11227-019-02935-1\">https://doi.org/10.1007/s11227-019-02935-1</a>.","ieee":"A. Rodríguez <i>et al.</i>, “Parallel multiprocessing and scheduling on the heterogeneous Xeon+FPGA platform,” <i>The Journal of Supercomputing</i>, 2019.","ama":"Rodríguez A, Navarro A, Asenjo R, et al. Parallel multiprocessing and scheduling on the heterogeneous Xeon+FPGA platform. <i>The Journal of Supercomputing</i>. 2019. doi:<a href=\"https://doi.org/10.1007/s11227-019-02935-1\">10.1007/s11227-019-02935-1</a>","bibtex":"@article{Rodríguez_Navarro_Asenjo_Corbera_Gran_Suárez_Nunez-Yanez_2019, title={Parallel multiprocessing and scheduling on the heterogeneous Xeon+FPGA platform}, DOI={<a href=\"https://doi.org/10.1007/s11227-019-02935-1\">10.1007/s11227-019-02935-1</a>}, journal={The Journal of Supercomputing}, author={Rodríguez, Andrés and Navarro, Angeles and Asenjo, Rafael and Corbera, Francisco and Gran, Rubén and Suárez, Darío and Nunez-Yanez, Jose}, year={2019} }","short":"A. Rodríguez, A. Navarro, R. Asenjo, F. Corbera, R. Gran, D. Suárez, J. Nunez-Yanez, The Journal of Supercomputing (2019).","mla":"Rodríguez, Andrés, et al. “Parallel Multiprocessing and Scheduling on the Heterogeneous Xeon+FPGA Platform.” <i>The Journal of Supercomputing</i>, 2019, doi:<a href=\"https://doi.org/10.1007/s11227-019-02935-1\">10.1007/s11227-019-02935-1</a>.","apa":"Rodríguez, A., Navarro, A., Asenjo, R., Corbera, F., Gran, R., Suárez, D., &#38; Nunez-Yanez, J. (2019). Parallel multiprocessing and scheduling on the heterogeneous Xeon+FPGA platform. <i>The Journal of Supercomputing</i>. <a href=\"https://doi.org/10.1007/s11227-019-02935-1\">https://doi.org/10.1007/s11227-019-02935-1</a>"},"publication_identifier":{"issn":["0920-8542","1573-0484"]},"publication_status":"published","title":"Parallel multiprocessing and scheduling on the heterogeneous Xeon+FPGA platform","doi":"10.1007/s11227-019-02935-1","date_updated":"2022-01-06T06:52:50Z","date_created":"2020-04-06T12:09:25Z","author":[{"first_name":"Andrés","full_name":"Rodríguez, Andrés","last_name":"Rodríguez"},{"first_name":"Angeles","last_name":"Navarro","full_name":"Navarro, Angeles"},{"last_name":"Asenjo","full_name":"Asenjo, Rafael","first_name":"Rafael"},{"last_name":"Corbera","full_name":"Corbera, Francisco","first_name":"Francisco"},{"full_name":"Gran, Rubén","last_name":"Gran","first_name":"Rubén"},{"first_name":"Darío","full_name":"Suárez, Darío","last_name":"Suárez"},{"full_name":"Nunez-Yanez, Jose","last_name":"Nunez-Yanez","first_name":"Jose"}],"abstract":[{"text":"Heterogeneous computing that exploits simultaneous co-processing with different device types has been shown to be effective at both increasing performance and reducing energy consumption. In this paper, we extend a scheduling framework encapsulated in a high-level C++ template and previously developed for heterogeneous chips comprising CPU and GPU cores, to new high-performance platforms for the data center, which include a cache coherent FPGA fabric and many-core CPU resources. Our goal is to evaluate the suitability of our framework with these new FPGA-based platforms, identifying performance benefits and limitations.We target the state-of-the-art HARP processor that includes 14 high-end Xeon classes tightly coupled to a FPGA device located in the same package. We select eight benchmarks from the high-performance computing domain that have been ported and optimized for this heterogeneous platform. The results show that a dynamic and adaptive scheduler that exploits simultaneous processing among the devices can improve performance up to a factor of 8 × compared to the best alternative solutions that only use the CPU cores or the FPGA fabric. Moreover, our proposal achieves up to 15% and 37% of improvement compared to the best heterogeneous solutions found with a dynamic and static schedulers, respectively.","lang":"eng"}],"status":"public","publication":"The Journal of Supercomputing","type":"journal_article","keyword":["pc2-harp-ressources"],"language":[{"iso":"eng"}],"_id":"16423","user_id":"61189"},{"_id":"16427","user_id":"61189","keyword":["pc2-harp-ressources"],"language":[{"iso":"eng"}],"publication":"Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture","type":"conference","abstract":[{"text":"Transactional Memory (TM) has been considered as a promising alternative to existing synchronization operations, which are often the largest stumbling block to unleashing parallelism of applications. Efficient implementations of TM, however, are challenging due to the tension between lowering performance overhead and avoiding unnecessary aborts.\r\n\r\nIn this paper, we present Reachability-based Optimistic Concurrency Control for Transactional Memory (ROCoCoTM), a novel scheme which offloads concurrency control (CC) algorithms, the central building blocks of TM systems, to reconfigurable hardware. To reduce the abort rate, an innovative formalization of mainstream CC algorithms is developed to reveal a common restriction that leads to unnecessary aborts. This restriction is resolved by the ROCoCo algorithm with a centralized validation phase, which can be efficiently pipelined in hardware. Thanks to a high-performance offloading engine implemented in reconfigurable hardware, ROCoCo algorithm results in decreased abort rates and reduced performance overhead. The whole system is implemented on Intel's HARP2 platform and evaluated with the STAMP benchmark suite. Experiments show 1.55x and 8.05x geomean speedup over TinySTM and an HTM based on Intel TSX, respectively. Given the fast-growing deployment of commodity CPU-FPGA platforms, ROCoCoTM paves the way for software programmers to exploit heterogeneous computing resources with a high-level transactional abstraction to effectively extract the parallelism in modern applications.","lang":"eng"}],"status":"public","date_updated":"2022-01-06T06:52:50Z","date_created":"2020-04-06T12:49:40Z","author":[{"first_name":"Zhaoshi","full_name":"Li, Zhaoshi","last_name":"Li"},{"full_name":"Liu, Leibo","last_name":"Liu","first_name":"Leibo"},{"first_name":"Yangdong","full_name":"Deng, Yangdong","last_name":"Deng"},{"first_name":"Jiawei","last_name":"Wang","full_name":"Wang, Jiawei"},{"first_name":"Zhiwei","full_name":"Liu, Zhiwei","last_name":"Liu"},{"full_name":"Yin, Shouyi","last_name":"Yin","first_name":"Shouyi"},{"full_name":"Wei, Shaojun","last_name":"Wei","first_name":"Shaojun"}],"title":"FPGA-Accelerated Optimistic Concurrency Control for Transactional Memory","doi":"10.1145/3352460.3358270","publication_identifier":{"isbn":["9781450369381"]},"publication_status":"published","year":"2019","citation":{"chicago":"Li, Zhaoshi, Leibo Liu, Yangdong Deng, Jiawei Wang, Zhiwei Liu, Shouyi Yin, and Shaojun Wei. “FPGA-Accelerated Optimistic Concurrency Control for Transactional Memory.” In <i>Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture</i>, 2019. <a href=\"https://doi.org/10.1145/3352460.3358270\">https://doi.org/10.1145/3352460.3358270</a>.","ieee":"Z. Li <i>et al.</i>, “FPGA-Accelerated Optimistic Concurrency Control for Transactional Memory,” in <i>Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture</i>, 2019.","ama":"Li Z, Liu L, Deng Y, et al. FPGA-Accelerated Optimistic Concurrency Control for Transactional Memory. In: <i>Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture</i>. ; 2019. doi:<a href=\"https://doi.org/10.1145/3352460.3358270\">10.1145/3352460.3358270</a>","bibtex":"@inproceedings{Li_Liu_Deng_Wang_Liu_Yin_Wei_2019, title={FPGA-Accelerated Optimistic Concurrency Control for Transactional Memory}, DOI={<a href=\"https://doi.org/10.1145/3352460.3358270\">10.1145/3352460.3358270</a>}, booktitle={Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture}, author={Li, Zhaoshi and Liu, Leibo and Deng, Yangdong and Wang, Jiawei and Liu, Zhiwei and Yin, Shouyi and Wei, Shaojun}, year={2019} }","mla":"Li, Zhaoshi, et al. “FPGA-Accelerated Optimistic Concurrency Control for Transactional Memory.” <i>Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture</i>, 2019, doi:<a href=\"https://doi.org/10.1145/3352460.3358270\">10.1145/3352460.3358270</a>.","short":"Z. Li, L. Liu, Y. Deng, J. Wang, Z. Liu, S. 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