@inproceedings{2418, abstract = {{ This paper presents TKDM, a PC-based high-performance reconfigurable computing environment. The TKDM hardware consists of an FPGA module that uses the DIMM (dual inline memory module) bus for high-bandwidth and low-latency communication with the host CPU. The system's firmware is integrated with the Linux host operating system and offers functions for data communication and FPGA reconfiguration. The intended use of TKDM is that of a dynamically reconfigurable co-processor for data streaming applications. The system's firmware can be customized for specific application domains to facilitate simple and easy-to-use programming interfaces. }}, author = {{Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. Int. Conf. on Field Programmable Technology (ICFPT)}}, keywords = {{coprocessor, DIMM, memory bus, FPGA, high performance computing}}, pages = {{252--259}}, publisher = {{IEEE Computer Society}}, title = {{{TKDM – A Reconfigurable Co-processor in a PC's Memory Slot}}}, doi = {{10.1109/FPT.2003.1275755}}, year = {{2003}}, } @article{2419, abstract = {{Wearable computers are embedded into the mobile environment of their users. A design challenge for wearable systems is to combine the high performance required for tasks such as video decoding with the low energy consumption required to maximise battery runtimes and the flexibility demanded by the dynamics of the environment and the applications. In this paper, we demonstrate that reconfigurable hardware technology is able to answer this challenge. We present the concept and the prototype implementation of an autonomous wearable unit with reconfigurable modules (WURM). We discuss experiments that show the uses of reconfigurable hardware in WURM: ASICs-on-demand and adaptive interfaces. Finally, we present an experiment with an operating system layer for WURM.}}, author = {{Plessl, Christian and Enzler, Rolf and Walder, Herbert and Beutel, Jan and Platzner, Marco and Thiele, Lothar and Tröster, Gerhard}}, journal = {{Personal and Ubiquitous Computing}}, number = {{5}}, pages = {{299--308}}, publisher = {{Springer}}, title = {{{The Case for Reconfigurable Hardware in Wearable Computing}}}, doi = {{10.1007/s00779-003-0243-x}}, volume = {{7}}, year = {{2003}}, } @article{2420, abstract = {{ This paper presents the acceleration of minimum-cost covering problems by instance-specific hardware. First, we formulate the minimum-cost covering problem and discuss a branch \& bound algorithm to solve it. Then we describe instance-specific hardware architectures that implement branch \& bound in 3-valued logic and use reduction techniques similar to those found in software solvers. We further present prototypical accelerator implementations and a corresponding design tool flow. Our experiments reveal significant raw speedups up to five orders of magnitude for a set of smaller unate covering problems. Provided that hardware compilation times can be reduced, we conclude that instance-specific acceleration of hard minimum-cost covering problems will lead to substantial overall speedups. }}, author = {{Plessl, Christian and Platzner, Marco}}, issn = {{0920-8542}}, journal = {{Journal of Supercomputing}}, keywords = {{reconfigurable computing, instance-specific acceleration, minimum covering}}, number = {{2}}, pages = {{109--129}}, publisher = {{Kluwer Academic Publishers}}, title = {{{Instance-Specific Accelerators for Minimum Covering}}}, doi = {{10.1023/a:1024443416592}}, volume = {{26}}, year = {{2003}}, } @inproceedings{2421, abstract = {{In contrast to processors, current reconfigurable devices totally lack programming models that would allow for device independent compilation and forward compatibility. The key to overcome this limitation is hardware virtualization. In this paper, we resort to a macro-pipelined execution model to achieve hardware virtualization for data streaming applications. As a hardware implementation we present a hybrid multi-context architecture that attaches a coarse-grained reconfigurable array to a host CPU. A co-simulation framework enables cycle-accurate simulation of the complete architecture. As a case study we map an FIR filter to our virtualized hardware model and evaluate different designs. We discuss the impact of the number of contexts and the feature of context state on the speedup and the CPU load.}}, author = {{Enzler, Rolf and Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}}, keywords = {{Zippy, multi-context, FPGA}}, pages = {{151--160}}, publisher = {{Springer}}, title = {{{Virtualizing Hardware with Multi-Context Reconfigurable Arrays}}}, doi = {{10.1007/b12007}}, volume = {{2778}}, year = {{2003}}, } @inproceedings{2422, abstract = {{Reconfigurable computing architectures aim to dynamically adapt their hardware to the application at hand. As research shows, the time it takes to reconfigure the hardware forms an overhead that can significantly impair the benefits of hardware customization. Multi-context devices are one promising approach to overcome the limitations posed by long reconfiguration times. In contrast to more traditional reconfigurable architectures, multi-context devices hold several configurations on-chip. On demand, the device can quickly switch to another context. In this paper we present a co-simulation environment to investigate design trade-offs for hybrid multi-context architectures. Our architectural model comprises a reconfigurable unit closely coupled to a CPU core. As a case study, we discuss the implementation of a FIR filter partitioned into several contexts. We outline the mapping process and present simulation results for single- and multi-context reconfigurable units coupled with both embedded and high-end CPUs.}}, author = {{Enzler, Rolf and Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}, isbn = {{1-932415-05-X}}, keywords = {{Zippy, co-simulation}}, pages = {{174--180}}, publisher = {{CSREA Press}}, title = {{{Co-simulation of a Hybrid Multi-Context Architecture}}}, year = {{2003}}, } @inproceedings{24273, author = {{Terbahl, Martina and Krokowski, Jens}}, booktitle = {{Proceedings of 5. GI-Informatiktage 2003}}, title = {{{Verteiltes Rendern durch dynamische Bildaufteilung}}}, year = {{2003}}, } @phdthesis{24602, author = {{Schmidt, Marco}}, publisher = {{Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn}}, title = {{{Neuronale Assoziativspeicher im Information Retrieval}}}, volume = {{116}}, year = {{2003}}, } @phdthesis{24604, author = {{Pusch, Rainer}}, publisher = {{Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn}}, title = {{{Personalplanung und -entwicklung in einem integrierten Vorgehensmodell zur Einfühung von PDM-Systemen}}}, volume = {{118}}, year = {{2003}}, } @phdthesis{24605, author = {{Kespohl, Hans D.}}, publisher = {{Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn}}, title = {{{Dynamisches Matching - Ein agentenbasiertes Verfahren zur Unterstützung des Kooperativen Produktengineering durch Wissens- und Technologietransfer}}}, volume = {{120}}, year = {{2003}}, } @phdthesis{24606, author = {{Molt, Thorsten}}, publisher = {{Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn}}, title = {{{Eine domänenübergreifende Softwarespezifikationstechnik für automatisierte Fertigungsanlagen}}}, volume = {{121}}, year = {{2003}}, } @book{24607, author = {{Gausemeier, Jürgen and Lückel, Joachim and Wallaschek, Jörg}}, publisher = {{Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn}}, title = {{{1. Paderborner Workshop Intelligente mechatronische Systeme}}}, volume = {{122}}, year = {{2003}}, } @phdthesis{24608, author = {{Gausemeier, Jürgen and Grafe, Michael}}, publisher = {{Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn}}, title = {{{2. Paderborner Workshop Augumented & Virtual Reality in der Produktentstehung}}}, volume = {{123}}, year = {{2003}}, } @phdthesis{24609, author = {{Littmann, Walter}}, publisher = {{Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn}}, title = {{{Piezoelektrische, resonant betriebene Ultraschall-Leistungswandler mit nichtlinearen mechanischen Randbedingungen}}}, volume = {{124}}, year = {{2003}}, } @phdthesis{24610, author = {{Wickord, Wiro}}, publisher = {{Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn}}, title = {{{Zur Anwendung probabilistischer Methoden in den frühen Phasen des Systementwurfs}}}, volume = {{125}}, year = {{2003}}, } @phdthesis{24611, author = {{Heittmann, Arne}}, publisher = {{Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn}}, title = {{{Ressourceneffiziente Architekturen neuronaler Assoziativspeicher}}}, volume = {{126}}, year = {{2003}}, } @phdthesis{24612, author = {{Witkowski, Ulf}}, publisher = {{Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn}}, title = {{{Einbettung selbstorganisierender Karten in autonome Miniroboter}}}, volume = {{127}}, year = {{2003}}, } @phdthesis{24613, author = {{Bobda, Christophe}}, publisher = {{Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn}}, title = {{{Synthesis of Dataflow Graphs for Reconfigurable Systems using Temporal Partitioning and Temporal Placement}}}, volume = {{128}}, year = {{2003}}, } @phdthesis{24614, author = {{Heller, Frank}}, publisher = {{Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn}}, title = {{{Wissensbasiertes Online-Störungsmanagement flexibler, hoch automatisierter Montagesysteme}}}, volume = {{129}}, year = {{2003}}, } @phdthesis{24615, author = {{Kühn, Andreas}}, publisher = {{Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn}}, title = {{{Systematik des Ideenmanagements im Produktentstehungsprozess}}}, volume = {{130}}, year = {{2003}}, } @phdthesis{24618, author = {{Keil-Slawik, Reinhard and Brennecke, Andreas}}, publisher = {{Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn}}, title = {{{ISIS: Installationshandbuch für lernförderliche Infrastrukturen}}}, volume = {{131}}, year = {{2003}}, }