TKDM – A Reconfigurable Co-processor in a PC's Memory Slot - Plessl, Christian; Platzner, Marco (Proc. Int. Conf. on Field Programmable Technology (ICFPT))
This paper presents TKDM, a PC-based high-performance reconfigurable computing environment. The TKDM hardware consists of an FPGA module that uses the DIMM (dual inline memory module) bus for high-bandwidth and low-latency communication with the host CPU. The system's firmware is integrated with the Linux host operating system and offers functions for data communication and FPGA reconfiguration. The intended use of TKDM is that of a dynamically reconfigurable co-processor for data streaming applications. The system's firmware can be customized for specific application domains to facilitate simple and easy-to-use programming interfaces.
Keywords: coprocessor; DIMM; memory bus; FPGA; high performance computing

The Case for Reconfigurable Hardware in Wearable Computing - Plessl, Christian; Enzler, Rolf; Walder, Herbert; Beutel, Jan; Platzner, Marco; Thiele, Lothar; Tröster, Gerhard (Personal and Ubiquitous Computing)
Wearable computers are embedded into the mobile environment of their users. A design challenge for wearable systems is to combine the high performance required for tasks such as video decoding with the low energy consumption required to maximise battery runtimes and the flexibility demanded by the dynamics of the environment and the applications. In this paper, we demonstrate that reconfigurable hardware technology is able to answer this challenge. We present the concept and the prototype implementation of an autonomous wearable unit with reconfigurable modules (WURM). We discuss experiments that show the uses of reconfigurable hardware in WURM: ASICs-on-demand and adaptive interfaces. Finally, we present an experiment with an operating system layer for WURM.

Instance-Specific Accelerators for Minimum Covering - Plessl, Christian; Platzner, Marco (Journal of Supercomputing)
This paper presents the acceleration of minimum-cost covering problems by instance-specific hardware. First, we formulate the minimum-cost covering problem and discuss a branch & bound algorithm to solve it. Then we describe instance-specific hardware architectures that implement branch & bound in 3-valued logic and use reduction techniques similar to those found in software solvers. We further present prototypical accelerator implementations and a corresponding design tool flow. Our experiments reveal significant raw speedups up to five orders of magnitude for a set of smaller unate covering problems. Provided that hardware compilation times can be reduced, we conclude that instance-specific acceleration of hard minimum-cost covering problems will lead to substantial overall speedups.
Keywords: reconfigurable computing; instance-specific acceleration; minimum covering

Virtualizing Hardware with Multi-Context Reconfigurable Arrays - Enzler, Rolf; Plessl, Christian; Platzner, Marco (Proc. Int. Conf. on Field Programmable Logic and Applications (FPL))
In contrast to processors, current reconfigurable devices totally lack programming models that would allow for device independent compilation and forward compatibility. The key to overcome this limitation is hardware virtualization. In this paper, we resort to a macro-pipelined execution model to achieve hardware virtualization for data streaming applications. As a hardware implementation we present a hybrid multi-context architecture that attaches a coarse-grained reconfigurable array to a host CPU. A co-simulation framework enables cycle-accurate simulation of the complete architecture. As a case study we map an FIR filter to our virtualized hardware model and evaluate different designs. We discuss the impact of the number of contexts and the feature of context state on the speedup and the CPU load.
Keywords: Zippy; multi-context; FPGA

Co-simulation of a Hybrid Multi-Context Architecture - Enzler, Rolf; Plessl, Christian; Platzner, Marco (Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA))
Reconfigurable computing architectures aim to dynamically adapt their hardware to the application at hand. As research shows, the time it takes to reconfigure the hardware forms an overhead that can significantly impair the benefits of hardware customization. Multi-context devices are one promising approach to overcome the limitations posed by long reconfiguration times. In contrast to more traditional reconfigurable architectures, multi-context devices hold several configurations on-chip. On demand, the device can quickly switch to another context. In this paper we present a co-simulation environment to investigate design trade-offs for hybrid multi-context architectures. Our architectural model comprises a reconfigurable unit closely coupled to a CPU core. As a case study, we discuss the implementation of a FIR filter partitioned into several contexts. We outline the mapping process and present simulation results for single- and multi-context reconfigurable units coupled with both embedded and high-end CPUs.
Keywords: Zippy; co-simulation

Verteiltes Rendern durch dynamische Bildaufteilung - Terbahl, Martina; Krokowski, Jens (Proceedings of 5. GI-Informatiktage 2003)

Neuronale Assoziativspeicher im Information Retrieval - Schmidt, Marco

Personalplanung und -entwicklung in einem integrierten Vorgehensmodell zur Einfühung von PDM-Systemen - Pusch, Rainer

Dynamisches Matching - Ein agentenbasiertes Verfahren zur Unterstützung des Kooperativen Produktengineering durch Wissens- und Technologietransfer - Kespohl, Hans D.

Eine domänenübergreifende Softwarespezifikationstechnik für automatisierte Fertigungsanlagen - Molt, Thorsten