@book{55707, editor = {{Priesching, Nicole and Henkelmann, Andreas}}, title = {{{Widerstand? Forschungsperspektiven auf das Verhältnis von Katholizismus und Nationalsozialismus}}}, volume = {{2}}, year = {{2010}}, } @book{55813, author = {{Kepper, Johannes and Roland, Perry D.}}, title = {{{Music Encoding Initiative Tag Library, 2010-05 Release}}}, year = {{2010}}, } @article{40109, author = {{Schmitz, Sabine}}, journal = {{Archiv für das Studium der neueren Sprachen und Literaturen}}, pages = {{317--333}}, title = {{{Orte des Anderssagens auf der Bühne: Spielformen der allegorischen Personifikation in der Moralité des 15. und 16. Jahrhunderts}}}, volume = {{247}}, year = {{2010}}, } @article{36946, author = {{Weber, Jutta}}, journal = {{Poiesis and Praxis. International Journal of Ethics of Science and Technology Assessment 1/2010}}, number = {{1/2010}}, pages = {{17--36}}, title = {{{Making Worlds. Epistemological, Ontological and Political Dimensions of Technoscience}}}, volume = {{Vol. 7}}, year = {{2010}}, } @inbook{36957, author = {{Weber, Jutta}}, booktitle = {{GenderChange in Academia. Re-mapping the Fields of Work, Knowledge, and Politics from a Gender Perspective}}, editor = {{Riegraf, Birgit and Aulenbacher, Brigitte and Kirsch-Auwärter, Edit and Müller, Ursula}}, pages = {{217--230}}, publisher = {{Verlag für Sozialwissenschaften}}, title = {{{‘Security’ Architectures, New Ontologies and the Category of Gender. Contemporary Challenges in Feminist Technoscience Studies}}}, year = {{2010}}, } @inbook{36959, author = {{Weber, Jutta}}, booktitle = {{Roboterträume}}, pages = {{40--61}}, publisher = {{Kehrer Verlag}}, title = {{{Neue Roboterträume. Über Wunsch und Wirklichkeit der Dienstleistungsrobotik}}}, year = {{2010}}, } @inbook{36958, author = {{Weber, Jutta}}, booktitle = {{Roboterträume}}, pages = {{40--61}}, publisher = {{Kehrer Verlag}}, title = {{{New Robot Dreams. On Desire and Reality in Service Robotics}}}, year = {{2010}}, } @inbook{36963, author = {{Weber, Jutta}}, booktitle = {{Thinking Machines and the Philosophy of Computer Science: Concepts and Principles}}, editor = {{Vallverdú, Jordi}}, pages = {{206--222}}, publisher = {{IGI Global}}, title = {{{Armchair Warfare ‘on Terrorism’. On Robots, Targeted Assassinations and Strategic Violations of International Law}}}, year = {{2010}}, } @inbook{36964, author = {{Weber, Jutta and Crutzen, Cecile}}, booktitle = {{Festschrift for Christina Mörtberg}}, editor = {{Elovaara, Pirjo and Sefyrin, Johanna and Öhman, Maybritt and Björkman, Christina and Blomqvist, Martha}}, pages = {{245--268}}, publisher = {{Department of Informatics: Umeå Universität}}, title = {{{Gender, Diversity and a Competence Based Computer Science Curriculum}}}, year = {{2010}}, } @inbook{36967, author = {{Weber, Jutta}}, booktitle = {{Geschlecht und Innovation. Gender-Mainstreaming im Techno-Wissenschaftsbetrieb. Teilband 4. Internationale Frauen- und Geschlechterforschung in Niedersachsen}}, editor = {{Ernst, Waltraud}}, pages = {{49--62}}, publisher = {{LIT Verlag}}, title = {{{Situiertheit, Verkörperung, Gefühl: Unscharfe Begriffe als technowissenschaftliche Innovationsressource}}}, year = {{2010}}, } @inbook{36969, author = {{Weber, Jutta}}, booktitle = {{Der Wert des menschlichen Lebens im 21. Jahrhundert. Zu den Grenzen der menschlichen Verfügungsmacht. 13. Internationale Europakonferenz}}, editor = {{Badura, Hans}}, pages = {{245--260}}, publisher = {{Eigenverlag}}, title = {{{Flexibel, situiert & unberechenbar. Über Mensch und Maschine im Zeitalter der Technoscience}}}, year = {{2010}}, } @inproceedings{37007, abstract = {{UML is widely applied for the specification and modeling of software and some studies have demonstrated that it is applicable for HW/SW codesign. However, in this area there is still a big gap from UML modeling to SystemC-based verification and synthesis environments. This paper presents an efficient approach to bridge this gap in the context of Systems-on-a-Chip (SoC) design. We propose a framework for the seamless integration of a customized SysML entry with code generation for HW/SW cosimulation and high-level FPGA synthesis. For this, we extended the SysML UML profile by SystemC and synthesis capabilities. Two case studies demonstrate the applicability of our approach.}}, author = {{Mischkalla, Fabian and He, Da and Müller, Wolfgang}}, booktitle = {{Proceedings of DATE’10}}, keywords = {{Unified modeling language, Field programmable gate arrays, Bridges, Helium, Real time systems, Operating systems, Documentation, Application software, XML, Space exploration}}, location = {{Dresden}}, publisher = {{IEEE}}, title = {{{Closing the Gap between UML-based Modeling and Simulation of Combined HW/SW Systems}}}, doi = {{10.1109/DATE.2010.5456990}}, year = {{2010}}, } @inproceedings{37009, abstract = {{Today, mobile and embedded real time systems have to cope with the migration and allocation of multiple software tasks running on top of a real time operating system (RTOS) residing on one or several processors. For scaling of each task set and processor configuration, instruction set simulation and worst case timing analysis are typically applied. This paper presents a complementary approach for the verification of RTOS properties based on an abstract RTOS-Model in SystemC. We apply IEEE P1850 PSL for which we present an approach and first experiences for the assertion-based verification of RTOS properties.}}, author = {{Oliveira, Marcio F. S. and Zabel, Henning and Müller, Wolfgang}}, booktitle = {{Proceedings of DATE’10}}, keywords = {{Operating systems, Real time systems, Timing, Hardware, Analytical models, Embedded software, Software systems, Processor scheduling, Software performance, Performance analysis}}, location = {{Dresden}}, publisher = {{IEEE}}, title = {{{Assertion-Based Verification of RTOS Properties}}}, doi = {{10.1109/DATE.2010.5457130}}, year = {{2010}}, } @inproceedings{37011, abstract = {{Safety-critical automotive systems must fulfill hard real-time constraints for reliability and safety. This paper presents a case study for the application of an AUTOSAR-based language for timing modeling and analysis. We present and apply the Timing Augmented Description Language (TADL) and demonstrate a methodology for the development of a speed-adaptive steer-by-wire system. We examine the impact of TADL and the methodology on the development process and the suitability and interoperability of the applied tools with respect to the AUTOSAR-based tool chain in the context of our case study.}}, author = {{Klobedanz, Kay and Kuznik, Christoph and Thuy, Andre and Müller, Wolfgang}}, booktitle = {{Proceedings of DATE’10, Dresden}}, keywords = {{Timing, Programming, Automotive engineering, Application software, Hardware, Computer architecture, Communication system software, Software architecture, Delay, Software standards}}, location = {{Dresden}}, publisher = {{IEEE}}, title = {{{Timing Modeling and Analysis for AUTOSAR-Based Software Development - A Case Study}}}, doi = {{10.1109/DATE.2010.5457125}}, year = {{2010}}, } @inproceedings{37037, abstract = {{Today we can identify a big gap between requirement specification and the generation of test environments. This article extends the Classification Tree Method for Embedded Systems (CTM/ES) to fill this gap by new concepts for the precise specification of stimuli for operational ranges of continuous control systems. It introduces novel means for continuous acceptance criteria definition and for functional coverage definition.}}, author = {{Krupp, Alexander and Müller, Wolfgang}}, booktitle = {{Proceedings of DATE’10}}, keywords = {{System testing, Automatic testing, Object oriented modeling, Classification tree analysis, Automotive engineering, Mathematical model, Embedded system, Control systems, Electronic equipment testing, Software testing}}, location = {{Dresden}}, publisher = {{IEEE}}, title = {{{A Systematic Approach to Combined HW/SW System Test}}}, doi = {{10.1109/DATE.2010.5457186}}, year = {{2010}}, } @inproceedings{37040, abstract = {{Refinement of untimed TLM models into a timed HW/SW platform is a step by step design process which is a trade-off between timing accuracy of the used models and correct estimation of the final timing performance. The use of an RTOS on the target platform is mandatory in the case real-time properties must be guaranteed. Thus, the question is when the RTOS must be introduced in this step by step refinement process. This paper proposes a four-level RTOS-aware refinement methodology that, starting from an untimed TLM SystemC description of the whole system, progressively introduce HW/SW partitioning, timing, device driver and RTOS functionalities, till to obtain an accurate model of the final platform, where SW tasks run upon an RTOS hosted by QEMU and HW components are modeled by cycle accurate TLM descriptions. Each refinement level allows the designer to estimate more and more accurate timing properties, thus anticipating design decisions without being constrained to leave timing analysis to the final step of the refinement. The effectiveness of the methodology has been evaluated in the design of two complex platforms.}}, author = {{Becker, Markus and Di Guglielmo, Giuseppe and Fummi, Franco and Müller, Wolfgang and Pravadelli, Graziano and Xie, Tao}}, booktitle = {{Proceedings of DATE’10}}, keywords = {{Timing, Hardware, Operating systems, Process design, Accuracy, Standards development, Context modeling, Real time systems, Communication channels, Microprogramming}}, location = {{Dresden}}, publisher = {{IEEE}}, title = {{{RTOS-Aware Refinement for TLM2.0-based HW/SW Design}}}, doi = {{10.1109/DATE.2010.5456965}}, year = {{2010}}, } @inproceedings{37046, abstract = {{In this article, we present a flexible simulation environment for embedded real-time software refinement by a mixed level cosimulation. For this, we combine the native speed of an abstract real-time operating system (RTOS) model in SystemC with dynamic binary translation for fast Instruction Set Simulation (ISS) by QEMU. In order to support stepwise RTOS software refinement from system level to the target software, each task can be separately migrated between the native execution and the ISS. By adapting the dynamic binary translation approach to an efficient but yet very accurate synchronization scheme the overhead of QEMU user mode execution is only factor two compared to native SystemC. Furthermore, the simulation speed increases almost linearly according to the utilization of the task set abstracted by the native execution. Hereby, the simulation time can be considerably reduced by cosimulating just a subset of tasks on QEMU.}}, author = {{Becker, Markus and Zabel, Henning and Müller, Wolfgang}}, editor = {{Kleinjohann, L. and Kleinjohann, B.}}, isbn = {{978-3-642-15233-7}}, keywords = {{Application Programming Interface User Mode Kernel Space System Level Design Mixed Level}}, publisher = {{Springer Verlag}}, title = {{{A Mixed Level Simulation Environment for Stepwise RTOS Software Refinement}}}, doi = {{10.1007/978-3-642-15234-4_15}}, year = {{2010}}, } @inproceedings{37044, abstract = {{In this paper we present new concepts to resolve ECU (Electronic Control Unit) failures in FlexRay networks. Our approach extends the FlexRay bus schedule by redundant slots with modifications in the communication and slot assignment. We introduce additional backup nodes to replace faulty nodes. To reduce the required memory resources of the backup nodes, we distribute redundant tasks over different nodes and propose the migration of tasks to the backup node at runtime. We investigate different solutions to migrate the redundant tasks to the backup node by time-triggered and event-triggered transmissions.}}, author = {{Klobedanz, Kay and Defo, Gilles B. and Zabel, Henning and Müller, Wolfgang and Zhi, Yuan}}, editor = {{Kleinjohann, L. and Kleinjohann, B.}}, isbn = {{978-3-642-15233-7}}, keywords = {{Faulty Node Static Segment Slot Assignment Task Migration Communication Controller}}, publisher = {{Springer Verlag}}, title = {{{Task Migration for Fault-Tolerant FlexRay Networks}}}, doi = {{10.1007/978-3-642-15234-4_7}}, year = {{2010}}, } @inproceedings{37042, abstract = {{It's wide application in the area of software engineering, UML is still not fully accepted for other engineering domains like for electronic systems design. The main obstacle is due to a major gap in the design flow between UML-based modeling and verification. To overcome this gap, we introduce a UML profile for synthesizable SystemC and C and present its implementation in the context of the advanced SysML modeling environment of ARTiSAN Studio. We demonstrate how to customize Studio for SystemC/C comodeling so that it can serve as a verification and synthesis front-end.}}, author = {{Mischkalla, Fabian and Müller, Wolfgang and He, Da}}, booktitle = {{Proceedings of the M-BED Workshop}}, title = {{{A UML Profile for SysML-Based Comodeling for Embedded Systems Simulation and Synthesis}}}, year = {{2010}}, } @inproceedings{37043, author = {{Bol, Alexander and Müller, Wolfgang and Krupp, Alexander}}, booktitle = {{Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)}}, title = {{{Eine strukturierte Methode zur Generierung von SystemVerilog-Testumgebungen aus textuellen Anforderungsbeschreibungen}}}, year = {{2010}}, }