[{"language":[{"iso":"eng"}],"keyword":["Communicate Sequential Process     Virtual Platform     Smart Camera     Synchronous Data Flow     Artisan Studio"],"department":[{"_id":"672"}],"series_title":"Lecture Notes in Electrical Engineering","user_id":"5786","_id":"37050","status":"public","abstract":[{"text":"The main obstacle for the wide acceptance of UML and SysML in the design of electronic systems is due to a major gap in the design flow between UML-based modeling and SystemC-based verification. To overcome this gap, we present an approach developed in the SATURN project which introduces UML profiles for the co-modeling of SystemC and C with code generation support in the context of the SysML tool suite ARTiSAN Studio®. We finally discuss the evaluation of the approach by two case studies.","lang":"eng"}],"publication":"Proceedings of the IEEE Computer Society Annual Symposium on VLSI","type":"conference","doi":"10.1007/978-94-007-1488-5_9","title":"The SATURN Approach to SysML-based HW/SW Codesign","date_created":"2023-01-17T11:19:45Z","author":[{"first_name":"Wolfgang","last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang"},{"last_name":"He","full_name":"He, Da","first_name":"Da"},{"last_name":"Mischkalla","full_name":"Mischkalla, Fabian","first_name":"Fabian"},{"last_name":"Wegele","full_name":"Wegele, Arthur","first_name":"Arthur"},{"first_name":"Adrian","last_name":"Larkham","full_name":"Larkham, Adrian"},{"first_name":"Paul","last_name":"Whiston","full_name":"Whiston, Paul"},{"last_name":"Penil","full_name":"Penil, Pablo","first_name":"Pablo"},{"first_name":"Eugenio","last_name":"Villar","full_name":"Villar, Eugenio"},{"first_name":"Nikolaos","last_name":"Mitas","full_name":"Mitas, Nikolaos"},{"full_name":"Kritharidis, Dimitros","last_name":"Kritharidis","first_name":"Dimitros"},{"first_name":"Florent","last_name":"Azcarate","full_name":"Azcarate, Florent"},{"first_name":"Manuel","last_name":"Carballeda","full_name":"Carballeda, Manuel"}],"date_updated":"2023-01-17T11:19:53Z","citation":{"apa":"Müller, W., He, D., Mischkalla, F., Wegele, A., Larkham, A., Whiston, P., Penil, P., Villar, E., Mitas, N., Kritharidis, D., Azcarate, F., &#38; Carballeda, M. (2010). The SATURN Approach to SysML-based HW/SW Codesign. <i>Proceedings of the IEEE Computer Society Annual Symposium on VLSI</i>. <a href=\"https://doi.org/10.1007/978-94-007-1488-5_9\">https://doi.org/10.1007/978-94-007-1488-5_9</a>","bibtex":"@inproceedings{Müller_He_Mischkalla_Wegele_Larkham_Whiston_Penil_Villar_Mitas_Kritharidis_et al._2010, series={Lecture Notes in Electrical Engineering}, title={The SATURN Approach to SysML-based HW/SW Codesign}, DOI={<a href=\"https://doi.org/10.1007/978-94-007-1488-5_9\">10.1007/978-94-007-1488-5_9</a>}, booktitle={Proceedings of the IEEE Computer Society Annual Symposium on VLSI}, author={Müller, Wolfgang and He, Da and Mischkalla, Fabian and Wegele, Arthur and Larkham, Adrian and Whiston, Paul and Penil, Pablo and Villar, Eugenio and Mitas, Nikolaos and Kritharidis, Dimitros and et al.}, year={2010}, collection={Lecture Notes in Electrical Engineering} }","short":"W. Müller, D. He, F. Mischkalla, A. Wegele, A. Larkham, P. Whiston, P. Penil, E. Villar, N. Mitas, D. Kritharidis, F. Azcarate, M. Carballeda, in: Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010.","mla":"Müller, Wolfgang, et al. “The SATURN Approach to SysML-Based HW/SW Codesign.” <i>Proceedings of the IEEE Computer Society Annual Symposium on VLSI</i>, 2010, doi:<a href=\"https://doi.org/10.1007/978-94-007-1488-5_9\">10.1007/978-94-007-1488-5_9</a>.","ieee":"W. Müller <i>et al.</i>, “The SATURN Approach to SysML-based HW/SW Codesign,” 2010, doi: <a href=\"https://doi.org/10.1007/978-94-007-1488-5_9\">10.1007/978-94-007-1488-5_9</a>.","chicago":"Müller, Wolfgang, Da He, Fabian Mischkalla, Arthur Wegele, Adrian Larkham, Paul Whiston, Pablo Penil, et al. “The SATURN Approach to SysML-Based HW/SW Codesign.” In <i>Proceedings of the IEEE Computer Society Annual Symposium on VLSI</i>. Lecture Notes in Electrical Engineering, 2010. <a href=\"https://doi.org/10.1007/978-94-007-1488-5_9\">https://doi.org/10.1007/978-94-007-1488-5_9</a>.","ama":"Müller W, He D, Mischkalla F, et al. The SATURN Approach to SysML-based HW/SW Codesign. In: <i>Proceedings of the IEEE Computer Society Annual Symposium on VLSI</i>. Lecture Notes in Electrical Engineering. ; 2010. doi:<a href=\"https://doi.org/10.1007/978-94-007-1488-5_9\">10.1007/978-94-007-1488-5_9</a>"},"year":"2010","publication_identifier":{"eisbn":["978-94-007-1488-5"]}},{"title":"Generation of Executable Testbenches from Natural Language Requirement Specifications for Embedded Real-Time Systems","conference":{"name":"IFIP Working Conference on Distributed and Parallel Embedded Systems (DIPES 2010)"},"doi":"10.1007/978-3-642-15234-4_9","publisher":"Springer Verlag","date_updated":"2023-01-17T11:09:54Z","author":[{"first_name":"Wolfgang","id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller"},{"first_name":"Alexander","full_name":"Bol, Alexander","last_name":"Bol"},{"last_name":"Krupp","full_name":"Krupp, Alexander","first_name":"Alexander"},{"first_name":"Ola","full_name":"Lundkvist, Ola","last_name":"Lundkvist"}],"date_created":"2023-01-17T11:09:48Z","place":"Dordrecht","year":"2010","citation":{"ama":"Müller W, Bol A, Krupp A, Lundkvist O. Generation of Executable Testbenches from Natural Language Requirement Specifications for Embedded Real-Time Systems. In: Kleinjohann L, Kleinjohann B, eds. Springer Verlag; 2010. doi:<a href=\"https://doi.org/10.1007/978-3-642-15234-4_9\">10.1007/978-3-642-15234-4_9</a>","ieee":"W. Müller, A. Bol, A. Krupp, and O. Lundkvist, “Generation of Executable Testbenches from Natural Language Requirement Specifications for Embedded Real-Time Systems,” 2010, doi: <a href=\"https://doi.org/10.1007/978-3-642-15234-4_9\">10.1007/978-3-642-15234-4_9</a>.","chicago":"Müller, Wolfgang, Alexander Bol, Alexander Krupp, and Ola Lundkvist. “Generation of Executable Testbenches from Natural Language Requirement Specifications for Embedded Real-Time Systems.” edited by L. Kleinjohann and B. Kleinjohann. Dordrecht: Springer Verlag, 2010. <a href=\"https://doi.org/10.1007/978-3-642-15234-4_9\">https://doi.org/10.1007/978-3-642-15234-4_9</a>.","short":"W. Müller, A. Bol, A. Krupp, O. Lundkvist, in: L. Kleinjohann, B. Kleinjohann (Eds.), Springer Verlag, Dordrecht, 2010.","mla":"Müller, Wolfgang, et al. <i>Generation of Executable Testbenches from Natural Language Requirement Specifications for Embedded Real-Time Systems</i>. Edited by L. Kleinjohann and B. Kleinjohann, Springer Verlag, 2010, doi:<a href=\"https://doi.org/10.1007/978-3-642-15234-4_9\">10.1007/978-3-642-15234-4_9</a>.","bibtex":"@inproceedings{Müller_Bol_Krupp_Lundkvist_2010, place={Dordrecht}, title={Generation of Executable Testbenches from Natural Language Requirement Specifications for Embedded Real-Time Systems}, DOI={<a href=\"https://doi.org/10.1007/978-3-642-15234-4_9\">10.1007/978-3-642-15234-4_9</a>}, publisher={Springer Verlag}, author={Müller, Wolfgang and Bol, Alexander and Krupp, Alexander and Lundkvist, Ola}, editor={Kleinjohann, L. and Kleinjohann, B.}, year={2010} }","apa":"Müller, W., Bol, A., Krupp, A., &#38; Lundkvist, O. (2010). <i>Generation of Executable Testbenches from Natural Language Requirement Specifications for Embedded Real-Time Systems</i> (L. Kleinjohann &#38; B. Kleinjohann, Eds.). Springer Verlag. <a href=\"https://doi.org/10.1007/978-3-642-15234-4_9\">https://doi.org/10.1007/978-3-642-15234-4_9</a>"},"publication_identifier":{"isbn":["978-3-642-15233-7"]},"keyword":["Natural Language     UML     SystemVerilog     Testbenches"],"language":[{"iso":"eng"}],"_id":"37048","department":[{"_id":"672"}],"user_id":"5786","editor":[{"last_name":"Kleinjohann","full_name":"Kleinjohann, L.","first_name":"L."},{"first_name":"B.","full_name":"Kleinjohann, B.","last_name":"Kleinjohann"}],"abstract":[{"lang":"eng","text":"We introduce a structured methodology for the generation of executable test environments from textual requirement specifications via UML class diagrams and the application of the classification tree methodology for embedded systems. The first phase is a stepwise transformation from unstructured English text into a textual normal form (TNF), which is automatically translated into UML class diagrams. After annotations of the class diagrams and the definition of test cases by sequence diagrams, both are converted into classification trees. From the classification trees we can finally generate SystemVerilog code. The methodology is introduced and evaluated by the example of an Adaptive Cruise Controller."}],"status":"public","type":"conference"},{"type":"conference","status":"public","editor":[{"last_name":"Kleinjohann","full_name":"Kleinjohann, L.","first_name":"L."},{"last_name":"Kleinjohann","full_name":"Kleinjohann, B.","first_name":"B."}],"user_id":"5786","department":[{"_id":"672"}],"_id":"37049","language":[{"iso":"eng"}],"citation":{"short":"T. Xie, F. Letombe, W. Müller, in: L. Kleinjohann, B. Kleinjohann (Eds.), Springer Verlag, Dordrecht, 2010.","mla":"Xie, Tao, et al. <i>Mutation-Analysis Directed Constrained Random Verification</i>. Edited by L. Kleinjohann and B. Kleinjohann, Springer Verlag, 2010.","bibtex":"@inproceedings{Xie_Letombe_Müller_2010, place={Dordrecht}, title={Mutation-Analysis Directed Constrained Random Verification}, publisher={Springer Verlag}, author={Xie, Tao and Letombe, Florian and Müller, Wolfgang}, editor={Kleinjohann, L. and Kleinjohann, B.}, year={2010} }","apa":"Xie, T., Letombe, F., &#38; Müller, W. (2010). <i>Mutation-Analysis Directed Constrained Random Verification</i> (L. Kleinjohann &#38; B. Kleinjohann, Eds.). Springer Verlag.","chicago":"Xie, Tao, Florian Letombe, and Wolfgang Müller. “Mutation-Analysis Directed Constrained Random Verification.” edited by L. Kleinjohann and B. Kleinjohann. Dordrecht: Springer Verlag, 2010.","ieee":"T. Xie, F. Letombe, and W. Müller, “Mutation-Analysis Directed Constrained Random Verification,” 2010.","ama":"Xie T, Letombe F, Müller W. Mutation-Analysis Directed Constrained Random Verification. In: Kleinjohann L, Kleinjohann B, eds. Springer Verlag; 2010."},"place":"Dordrecht","year":"2010","date_created":"2023-01-17T11:11:51Z","author":[{"first_name":"Tao","last_name":"Xie","full_name":"Xie, Tao"},{"first_name":"Florian","last_name":"Letombe","full_name":"Letombe, Florian"},{"first_name":"Wolfgang","last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang"}],"publisher":"Springer Verlag","date_updated":"2023-01-17T11:12:52Z","conference":{"name":"IFIP Working Conference on Distributed and Parallel Embedded Systems (DIPES 2010)"},"title":"Mutation-Analysis Directed Constrained Random Verification"},{"status":"public","type":"conference","language":[{"iso":"eng"}],"_id":"37051","department":[{"_id":"672"}],"user_id":"5786","place":"Paris","year":"2010","citation":{"chicago":"Xie, Tao, Gilles B. Defo, and Wolfgang Müller. “An Eclipse-Based Framework for the IP-XACT-Enabled Assembly of Mixed-Level IPs.” Paris, 2010.","ieee":"T. Xie, G. B. Defo, and W. Müller, “An Eclipse-based Framework for the IP-XACT-enabled Assembly of Mixed-Level IPs,” presented at the First Workshop on Hands-on Platforms and tools for model-based engineering of Embedded Systems (HoPES 2010), Paris, 2010.","ama":"Xie T, Defo GB, Müller W. An Eclipse-based Framework for the IP-XACT-enabled Assembly of Mixed-Level IPs. In: ; 2010.","apa":"Xie, T., Defo, G. B., &#38; Müller, W. (2010). <i>An Eclipse-based Framework for the IP-XACT-enabled Assembly of Mixed-Level IPs</i>. First Workshop on Hands-on Platforms and tools for model-based engineering of Embedded Systems (HoPES 2010), Paris.","mla":"Xie, Tao, et al. <i>An Eclipse-Based Framework for the IP-XACT-Enabled Assembly of Mixed-Level IPs</i>. 2010.","short":"T. Xie, G.B. Defo, W. Müller, in: Paris, 2010.","bibtex":"@inproceedings{Xie_Defo_Müller_2010, place={Paris}, title={An Eclipse-based Framework for the IP-XACT-enabled Assembly of Mixed-Level IPs}, author={Xie, Tao and Defo, Gilles B. and Müller, Wolfgang}, year={2010} }"},"title":"An Eclipse-based Framework for the IP-XACT-enabled Assembly of Mixed-Level IPs","conference":{"name":"First Workshop on Hands-on Platforms and tools for model-based engineering of Embedded Systems (HoPES 2010)","location":"Paris"},"date_updated":"2023-01-17T11:22:16Z","date_created":"2023-01-17T11:22:10Z","author":[{"first_name":"Tao","full_name":"Xie, Tao","last_name":"Xie"},{"first_name":"Gilles B.","full_name":"Defo, Gilles B.","last_name":"Defo"},{"first_name":"Wolfgang","last_name":"Müller","full_name":"Müller, Wolfgang","id":"16243"}]},{"author":[{"full_name":"Defo, Gilles B.","last_name":"Defo","first_name":"Gilles B."},{"first_name":"Wolfgang","full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller"},{"full_name":"Kuznik, Christoph","last_name":"Kuznik","first_name":"Christoph"}],"date_created":"2023-01-17T11:34:56Z","publisher":"IEEE","date_updated":"2023-01-17T11:35:03Z","conference":{"name":"International Symposium on Industrial Embedded System (SIES)","location":" Trento, Italy"},"doi":"10.1109/SIES.2010.5551379","title":"Verification of a CAN Bus Model in SystemC with Functional Coverage","publication_identifier":{"eisbn":["978-1-4244-5841-7"]},"citation":{"mla":"Defo, Gilles B., et al. “Verification of a CAN Bus Model in SystemC with Functional Coverage.” <i>Proceedings of SIES 2010</i>, IEEE, 2010, doi:<a href=\"https://doi.org/10.1109/SIES.2010.5551379\">10.1109/SIES.2010.5551379</a>.","bibtex":"@inproceedings{Defo_Müller_Kuznik_2010, place={ Trento, Italy}, title={Verification of a CAN Bus Model in SystemC with Functional Coverage}, DOI={<a href=\"https://doi.org/10.1109/SIES.2010.5551379\">10.1109/SIES.2010.5551379</a>}, booktitle={Proceedings of SIES 2010}, publisher={IEEE}, author={Defo, Gilles B. and Müller, Wolfgang and Kuznik, Christoph}, year={2010} }","short":"G.B. Defo, W. Müller, C. Kuznik, in: Proceedings of SIES 2010, IEEE,  Trento, Italy, 2010.","apa":"Defo, G. B., Müller, W., &#38; Kuznik, C. (2010). Verification of a CAN Bus Model in SystemC with Functional Coverage. <i>Proceedings of SIES 2010</i>. International Symposium on Industrial Embedded System (SIES),  Trento, Italy. <a href=\"https://doi.org/10.1109/SIES.2010.5551379\">https://doi.org/10.1109/SIES.2010.5551379</a>","ama":"Defo GB, Müller W, Kuznik C. Verification of a CAN Bus Model in SystemC with Functional Coverage. In: <i>Proceedings of SIES 2010</i>. IEEE; 2010. doi:<a href=\"https://doi.org/10.1109/SIES.2010.5551379\">10.1109/SIES.2010.5551379</a>","chicago":"Defo, Gilles B., Wolfgang Müller, and Christoph Kuznik. “Verification of a CAN Bus Model in SystemC with Functional Coverage.” In <i>Proceedings of SIES 2010</i>.  Trento, Italy: IEEE, 2010. <a href=\"https://doi.org/10.1109/SIES.2010.5551379\">https://doi.org/10.1109/SIES.2010.5551379</a>.","ieee":"G. B. Defo, W. Müller, and C. Kuznik, “Verification of a CAN Bus Model in SystemC with Functional Coverage,” presented at the International Symposium on Industrial Embedded System (SIES),  Trento, Italy, 2010, doi: <a href=\"https://doi.org/10.1109/SIES.2010.5551379\">10.1109/SIES.2010.5551379</a>."},"year":"2010","place":" Trento, Italy","department":[{"_id":"672"}],"user_id":"5786","_id":"37057","language":[{"iso":"eng"}],"keyword":["Libraries","Generators","Transfer functions","Monitoring","Computational modeling","Driver circuits","Adaptation model"],"publication":"Proceedings of SIES 2010","type":"conference","status":"public","abstract":[{"text":"Many heterogeneous embedded systems, for example industrial automation and automotive applications, require hard-real time constraints to be exhaustively verified - which is a challenging task for the verification engineer. To cope with complexity, verification techniques working on different abstraction levels are best practice. SystemC is a versatile C++ based design and verification language, offering various mechanisms and constructs required for embedded systems modeling. Using the add-on SystemC Verification Library (SCV) elemental constrained-random stimuli techniques may be used for verification. However, SCV has several drawbacks such as lack of functional coverage. In this paper we present a functional coverage library that implements parts of the IEEE 1800-2005 SystemVerilog standard and allows capturing functional coverage throughout the design and verification process with SystemC. Moreover, we will demonstrate the usability of the approach with a case study working on a CAN bus model written in SystemC.","lang":"eng"}]},{"date_updated":"2023-01-17T11:31:47Z","author":[{"first_name":"Kay","full_name":"Klobedanz, Kay","last_name":"Klobedanz"},{"full_name":"Defo, Gilles B.","last_name":"Defo","first_name":"Gilles B."},{"first_name":"Wolfgang","last_name":"Müller","full_name":"Müller, Wolfgang","id":"16243"},{"last_name":"Kerstan","full_name":"Kerstan, Timo","first_name":"Timo"}],"date_created":"2023-01-17T11:31:38Z","title":"Distributed Coordination of Task Migration for Fault-Tolerant FlexRay Networks","doi":"10.1109/SIES.2010.5551384","conference":{"name":"International Symposium on Industrial Embedded System (SIES)"},"publication_identifier":{"eisbn":["978-1-4244-5841-7"]},"place":"Trento, Italien","year":"2010","citation":{"ieee":"K. Klobedanz, G. B. Defo, W. Müller, and T. Kerstan, “Distributed Coordination of Task Migration for Fault-Tolerant FlexRay Networks,” presented at the International Symposium on Industrial Embedded System (SIES), 2010, doi: <a href=\"https://doi.org/10.1109/SIES.2010.5551384\">10.1109/SIES.2010.5551384</a>.","chicago":"Klobedanz, Kay, Gilles B. Defo, Wolfgang Müller, and Timo Kerstan. “Distributed Coordination of Task Migration for Fault-Tolerant FlexRay Networks.” In <i>Proceedings of SIES 2010</i>. Trento, Italien, 2010. <a href=\"https://doi.org/10.1109/SIES.2010.5551384\">https://doi.org/10.1109/SIES.2010.5551384</a>.","short":"K. Klobedanz, G.B. Defo, W. Müller, T. Kerstan, in: Proceedings of SIES 2010, Trento, Italien, 2010.","bibtex":"@inproceedings{Klobedanz_Defo_Müller_Kerstan_2010, place={Trento, Italien}, title={Distributed Coordination of Task Migration for Fault-Tolerant FlexRay Networks}, DOI={<a href=\"https://doi.org/10.1109/SIES.2010.5551384\">10.1109/SIES.2010.5551384</a>}, booktitle={Proceedings of SIES 2010}, author={Klobedanz, Kay and Defo, Gilles B. and Müller, Wolfgang and Kerstan, Timo}, year={2010} }","mla":"Klobedanz, Kay, et al. “Distributed Coordination of Task Migration for Fault-Tolerant FlexRay Networks.” <i>Proceedings of SIES 2010</i>, 2010, doi:<a href=\"https://doi.org/10.1109/SIES.2010.5551384\">10.1109/SIES.2010.5551384</a>.","ama":"Klobedanz K, Defo GB, Müller W, Kerstan T. Distributed Coordination of Task Migration for Fault-Tolerant FlexRay Networks. In: <i>Proceedings of SIES 2010</i>. ; 2010. doi:<a href=\"https://doi.org/10.1109/SIES.2010.5551384\">10.1109/SIES.2010.5551384</a>","apa":"Klobedanz, K., Defo, G. B., Müller, W., &#38; Kerstan, T. (2010). Distributed Coordination of Task Migration for Fault-Tolerant FlexRay Networks. <i>Proceedings of SIES 2010</i>. International Symposium on Industrial Embedded System (SIES). <a href=\"https://doi.org/10.1109/SIES.2010.5551384\">https://doi.org/10.1109/SIES.2010.5551384</a>"},"_id":"37056","user_id":"5786","department":[{"_id":"672"}],"keyword":["Fault tolerant systems","Protocols","Redundancy","Runtime","Payloads","Schedules"],"language":[{"iso":"eng"}],"type":"conference","publication":"Proceedings of SIES 2010","abstract":[{"lang":"eng","text":"In this paper we present an approach to increase the fault tolerance in FlexRay networks by introducing backup nodes to replace defect ECUs (Electronic Control Units). In order to reduce the memory requirements of such backup nodes, we distribute redundant tasks over different nodes and propose the distributed coordinated migration of tasks of the defect ECU to the backup node at runtime. This approach enhances our former work in, where we extended the FlexRay bus schedule by redundant slots to consider changes in the communication/slot assignment and investigated and evaluated different solutions to migrate the redundant tasks to the backup node using the static and/or dynamic segment of the communication cycle for transmissions. We present the approach of distributed coordination for migration and communication instead of additional dedicated coordinator nodes to further increase the fault tolerance. With this approach we improve the safety of FlexRay networks by avoiding a possible single point of failure due to a dedicated coordinator node also minimizing the necessary time needed for a reconfiguration after an ECU failure. Furthermore, we reduce the overhead within the communication and the demand for additional hardware components."}],"status":"public"},{"user_id":"5786","department":[{"_id":"672"}],"_id":"37053","language":[{"iso":"eng"}],"keyword":["Hardware","Microprogramming","Application software","Timing","Protocols","Virtual prototyping","Real time systems","Sampling methods","Operating systems","Emulation"],"type":"conference","publication":"Proceedings of HLDVT2010","status":"public","abstract":[{"lang":"eng","text":"Seamless HW/SW codesign flows support early verification of hardware and Hardware-dependent Software (HdS) like drivers, operating systems, and firmware. For early estimation and verification, the application of SystemC in combination with Instruction Set Simulators and Software Emulators like QEMU is widely accepted. In this article, we present an advanced design flow for HW, (RT)OS and HdS refinement and verification with focus on the transition from abstract RTOS verification to full system RTOS/HdS emulation. In the context of assertion-based verification, we introduce a set of generic real-time properties which can be reused and verified at different abstraction levels and discuss their application. The properties are presented by the means of IEEE standard PSL assertions which are applied for mixed SystemC/HdS models."}],"author":[{"full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller","first_name":"Wolfgang"},{"full_name":"da S. Oliveira, Marcio F.","last_name":"da S. Oliveira","first_name":"Marcio F."},{"first_name":"Henning","last_name":"Zabel","full_name":"Zabel, Henning"},{"full_name":"Becker, Markus","last_name":"Becker","first_name":"Markus"}],"date_created":"2023-01-17T11:28:26Z","publisher":"IEEE","date_updated":"2023-01-17T11:28:30Z","conference":{"location":"Anaheim, FL, USA","name":"IEEE International High Level Design Validation and Test Workshop (HLDVT)"},"title":"Verification of Real-Time Properties for Hardware-Dependant Software","publication_identifier":{"eisbn":["978-1-4244-7806-4"]},"citation":{"chicago":"Müller, Wolfgang, Marcio F. da S. Oliveira, Henning Zabel, and Markus Becker. “Verification of Real-Time Properties for Hardware-Dependant Software.” In <i>Proceedings of HLDVT2010</i>. IEEE, 2010.","ieee":"W. Müller, M. F. da S. Oliveira, H. Zabel, and M. Becker, “Verification of Real-Time Properties for Hardware-Dependant Software,” presented at the IEEE International High Level Design Validation and Test Workshop (HLDVT), Anaheim, FL, USA, 2010.","ama":"Müller W, da S. Oliveira MF, Zabel H, Becker M. Verification of Real-Time Properties for Hardware-Dependant Software. In: <i>Proceedings of HLDVT2010</i>. IEEE; 2010.","apa":"Müller, W., da S. Oliveira, M. F., Zabel, H., &#38; Becker, M. (2010). Verification of Real-Time Properties for Hardware-Dependant Software. <i>Proceedings of HLDVT2010</i>. IEEE International High Level Design Validation and Test Workshop (HLDVT), Anaheim, FL, USA.","mla":"Müller, Wolfgang, et al. “Verification of Real-Time Properties for Hardware-Dependant Software.” <i>Proceedings of HLDVT2010</i>, IEEE, 2010.","bibtex":"@inproceedings{Müller_da S. Oliveira_Zabel_Becker_2010, title={Verification of Real-Time Properties for Hardware-Dependant Software}, booktitle={Proceedings of HLDVT2010}, publisher={IEEE}, author={Müller, Wolfgang and da S. Oliveira, Marcio F. and Zabel, Henning and Becker, Markus}, year={2010} }","short":"W. Müller, M.F. da S. Oliveira, H. Zabel, M. Becker, in: Proceedings of HLDVT2010, IEEE, 2010."},"year":"2010"},{"citation":{"chicago":"Oliveira, Marcio F. S., Francisco Assis M. do Nascimento, and Wolfgang Müller. “Design Space Abstraction and Metamodeling for Embedded Systems Design Space Exploration.” In <i>Proceedings of MoMPES 2010</i>. Antwerp, Belgium, 2010.","ieee":"M. F. S. Oliveira, F. A. M. do Nascimento, and W. Müller, “Design Space Abstraction and Metamodeling for Embedded Systems Design Space Exploration,” 2010.","ama":"Oliveira MFS, do Nascimento FAM, Müller W. Design Space Abstraction and Metamodeling for Embedded Systems Design Space Exploration. In: <i>Proceedings of MoMPES 2010</i>. ; 2010.","apa":"Oliveira, M. F. S., do Nascimento, F. A. M., &#38; Müller, W. (2010). Design Space Abstraction and Metamodeling for Embedded Systems Design Space Exploration. <i>Proceedings of MoMPES 2010</i>.","mla":"Oliveira, Marcio F. S., et al. “Design Space Abstraction and Metamodeling for Embedded Systems Design Space Exploration.” <i>Proceedings of MoMPES 2010</i>, 2010.","bibtex":"@inproceedings{Oliveira_do Nascimento_Müller_2010, place={Antwerp, Belgium}, title={Design Space Abstraction and Metamodeling for Embedded Systems Design Space Exploration}, booktitle={Proceedings of MoMPES 2010}, author={Oliveira, Marcio F. S. and do Nascimento, Francisco Assis M. and Müller, Wolfgang}, year={2010} }","short":"M.F.S. Oliveira, F.A.M. do Nascimento, W. Müller, in: Proceedings of MoMPES 2010, Antwerp, Belgium, 2010."},"year":"2010","place":"Antwerp, Belgium","author":[{"full_name":"Oliveira, Marcio F. S.","last_name":"Oliveira","first_name":"Marcio F. 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