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Effekte einer Jonglierintervention auf die kognitive Leistung und die Gehirnaktivität von Grundschülern. In: <i>Kreativität - Innovation - Leistung</i>. ; 2011.","chicago":"Koutsandreou, F, K Reinecke, J Schade, M Cordes, M Schubert, Miriam Kehne, A Kämpfe, and Jochen Baumeister. “Effekte Einer Jonglierintervention Auf Die Kognitive Leistung Und Die Gehirnaktivität von Grundschülern.” In <i>Kreativität - Innovation - Leistung</i>, 2011.","ieee":"F. Koutsandreou <i>et al.</i>, “Effekte einer Jonglierintervention auf die kognitive Leistung und die Gehirnaktivität von Grundschülern,” 2011.","short":"F. Koutsandreou, K. Reinecke, J. Schade, M. Cordes, M. Schubert, M. Kehne, A. Kämpfe, J. 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Effekte einer Jonglierintervention auf die kognitive Leistung und die Gehirnaktivität von Grundschülern. <i>Kreativität - Innovation - Leistung</i>."},"year":"2011"},{"status":"public","type":"conference","language":[{"iso":"ger"}],"_id":"44654","user_id":"14931","department":[{"_id":"318"}],"year":"2011","citation":{"apa":"Brandl-Bredenbeck, H.-P., Köster, C., &#38; Kämpfe, A. (2011). <i>Studium heute: gesundheitsfördernd oder -gefährdend?: eine Lebensstilanalyse. Dokumentation 16. bundesweiter Kongress Armut und Gesundheit: 3./4. Dezember 2010 in Berlin</i>. 1–10.","bibtex":"@inproceedings{Brandl-Bredenbeck_Köster_Kämpfe_2011, title={Studium heute: gesundheitsfördernd oder -gefährdend?: eine Lebensstilanalyse. Dokumentation 16. bundesweiter Kongress Armut und Gesundheit: 3./4. Dezember 2010 in Berlin}, author={Brandl-Bredenbeck, Hans-Peter and Köster, Carolin and Kämpfe, Astrid}, year={2011}, pages={1–10} }","mla":"Brandl-Bredenbeck, Hans-Peter, et al. <i>Studium heute: gesundheitsfördernd oder -gefährdend?: eine Lebensstilanalyse. Dokumentation 16. bundesweiter Kongress Armut und Gesundheit: 3./4. Dezember 2010 in Berlin</i>. 2011, pp. 1–10.","short":"H.-P. Brandl-Bredenbeck, C. Köster, A. Kämpfe, in: 2011, pp. 1–10.","ama":"Brandl-Bredenbeck H-P, Köster C, Kämpfe A. Studium heute: gesundheitsfördernd oder -gefährdend?: eine Lebensstilanalyse. Dokumentation 16. bundesweiter Kongress Armut und Gesundheit: 3./4. Dezember 2010 in Berlin. In: ; 2011:1-10.","chicago":"Brandl-Bredenbeck, Hans-Peter, Carolin Köster, and Astrid Kämpfe. “Studium heute: gesundheitsfördernd oder -gefährdend?: eine Lebensstilanalyse. Dokumentation 16. bundesweiter Kongress Armut und Gesundheit: 3./4. Dezember 2010 in Berlin,” 1–10, 2011.","ieee":"H.-P. Brandl-Bredenbeck, C. Köster, and A. Kämpfe, “Studium heute: gesundheitsfördernd oder -gefährdend?: eine Lebensstilanalyse. Dokumentation 16. bundesweiter Kongress Armut und Gesundheit: 3./4. Dezember 2010 in Berlin,” 2011, pp. 1–10."},"page":"1-10","title":"Studium heute: gesundheitsfördernd oder -gefährdend?: eine Lebensstilanalyse. Dokumentation 16. bundesweiter Kongress Armut und Gesundheit: 3./4. Dezember 2010 in Berlin","date_updated":"2023-09-19T10:15:40Z","date_created":"2023-05-08T18:28:33Z","author":[{"first_name":"Hans-Peter","last_name":"Brandl-Bredenbeck","full_name":"Brandl-Bredenbeck, Hans-Peter"},{"first_name":"Carolin","last_name":"Köster","full_name":"Köster, Carolin","id":"676"},{"first_name":"Astrid","last_name":"Kämpfe","full_name":"Kämpfe, Astrid"}]},{"quality_controlled":"1","page":"60-63","citation":{"ieee":"B. Meyer, C. Plessl, and J. Förstner, “Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend,” in <i>Symp. on Application Accelerators in High Performance Computing (SAAHPC)</i>, 2011, pp. 60–63, doi: <a href=\"https://doi.org/10.1109/SAAHPC.2011.12\">10.1109/SAAHPC.2011.12</a>.","chicago":"Meyer, Björn, Christian Plessl, and Jens Förstner. “Transformation of Scientific Algorithms to Parallel Computing Code: Subdomain Support in a MPI-Multi-GPU Backend.” In <i>Symp. on Application Accelerators in High Performance Computing (SAAHPC)</i>, 60–63. IEEE Computer Society, 2011. <a href=\"https://doi.org/10.1109/SAAHPC.2011.12\">https://doi.org/10.1109/SAAHPC.2011.12</a>.","ama":"Meyer B, Plessl C, Förstner J. Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend. In: <i>Symp. on Application Accelerators in High Performance Computing (SAAHPC)</i>. IEEE Computer Society; 2011:60-63. doi:<a href=\"https://doi.org/10.1109/SAAHPC.2011.12\">10.1109/SAAHPC.2011.12</a>","mla":"Meyer, Björn, et al. “Transformation of Scientific Algorithms to Parallel Computing Code: Subdomain Support in a MPI-Multi-GPU Backend.” <i>Symp. on Application Accelerators in High Performance Computing (SAAHPC)</i>, IEEE Computer Society, 2011, pp. 60–63, doi:<a href=\"https://doi.org/10.1109/SAAHPC.2011.12\">10.1109/SAAHPC.2011.12</a>.","short":"B. Meyer, C. Plessl, J. Förstner, in: Symp. on Application Accelerators in High Performance Computing (SAAHPC), IEEE Computer Society, 2011, pp. 60–63.","bibtex":"@inproceedings{Meyer_Plessl_Förstner_2011, title={Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend}, DOI={<a href=\"https://doi.org/10.1109/SAAHPC.2011.12\">10.1109/SAAHPC.2011.12</a>}, booktitle={Symp. on Application Accelerators in High Performance Computing (SAAHPC)}, publisher={IEEE Computer Society}, author={Meyer, Björn and Plessl, Christian and Förstner, Jens}, year={2011}, pages={60–63} }","apa":"Meyer, B., Plessl, C., &#38; Förstner, J. (2011). Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend. <i>Symp. on Application Accelerators in High Performance Computing (SAAHPC)</i>, 60–63. <a href=\"https://doi.org/10.1109/SAAHPC.2011.12\">https://doi.org/10.1109/SAAHPC.2011.12</a>"},"year":"2011","author":[{"first_name":"Björn","full_name":"Meyer, Björn","last_name":"Meyer"},{"first_name":"Christian","full_name":"Plessl, Christian","id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982"},{"first_name":"Jens","id":"158","full_name":"Förstner, Jens","orcid":"0000-0001-7059-9862","last_name":"Förstner"}],"date_created":"2018-04-03T14:55:57Z","date_updated":"2023-09-26T13:44:11Z","publisher":"IEEE Computer Society","doi":"10.1109/SAAHPC.2011.12","title":"Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend","publication":"Symp. on Application Accelerators in High Performance Computing (SAAHPC)","type":"conference","status":"public","department":[{"_id":"27"},{"_id":"518"},{"_id":"15"},{"_id":"78"}],"user_id":"15278","_id":"2194","project":[{"grant_number":"01|H11004A","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","_id":"30"}],"language":[{"iso":"eng"}],"keyword":["tet_topic_hpc"]},{"status":"public","type":"conference","publication":"Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)","language":[{"iso":"eng"}],"user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"30","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","grant_number":"01|H11004A"}],"_id":"2193","citation":{"apa":"Beisel, T., Wiersema, T., Plessl, C., &#38; Brinkmann, A. (2011). Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler. <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)</i>, 223–226. <a href=\"https://doi.org/10.1109/ASAP.2011.6043273\">https://doi.org/10.1109/ASAP.2011.6043273</a>","bibtex":"@inproceedings{Beisel_Wiersema_Plessl_Brinkmann_2011, title={Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler}, DOI={<a href=\"https://doi.org/10.1109/ASAP.2011.6043273\">10.1109/ASAP.2011.6043273</a>}, booktitle={Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)}, publisher={IEEE Computer Society}, author={Beisel, Tobias and Wiersema, Tobias and Plessl, Christian and Brinkmann, André}, year={2011}, pages={223–226} }","mla":"Beisel, Tobias, et al. “Cooperative Multitasking for Heterogeneous Accelerators in the Linux Completely Fair Scheduler.” <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)</i>, IEEE Computer Society, 2011, pp. 223–26, doi:<a href=\"https://doi.org/10.1109/ASAP.2011.6043273\">10.1109/ASAP.2011.6043273</a>.","short":"T. Beisel, T. Wiersema, C. Plessl, A. Brinkmann, in: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2011, pp. 223–226.","ama":"Beisel T, Wiersema T, Plessl C, Brinkmann A. Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler. In: <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)</i>. IEEE Computer Society; 2011:223-226. doi:<a href=\"https://doi.org/10.1109/ASAP.2011.6043273\">10.1109/ASAP.2011.6043273</a>","ieee":"T. Beisel, T. Wiersema, C. Plessl, and A. Brinkmann, “Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler,” in <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)</i>, 2011, pp. 223–226, doi: <a href=\"https://doi.org/10.1109/ASAP.2011.6043273\">10.1109/ASAP.2011.6043273</a>.","chicago":"Beisel, Tobias, Tobias Wiersema, Christian Plessl, and André Brinkmann. “Cooperative Multitasking for Heterogeneous Accelerators in the Linux Completely Fair Scheduler.” In <i>Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)</i>, 223–26. IEEE Computer Society, 2011. <a href=\"https://doi.org/10.1109/ASAP.2011.6043273\">https://doi.org/10.1109/ASAP.2011.6043273</a>."},"page":"223-226","year":"2011","quality_controlled":"1","doi":"10.1109/ASAP.2011.6043273","title":"Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler","date_created":"2018-04-03T14:37:14Z","author":[{"first_name":"Tobias","last_name":"Beisel","full_name":"Beisel, Tobias"},{"id":"3118","full_name":"Wiersema, Tobias","last_name":"Wiersema","first_name":"Tobias"},{"first_name":"Christian","full_name":"Plessl, Christian","id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982"},{"last_name":"Brinkmann","full_name":"Brinkmann, André","first_name":"André"}],"publisher":"IEEE Computer Society","date_updated":"2023-09-26T13:43:48Z"},{"type":"conference","publication":"Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)","abstract":[{"lang":"eng","text":"In the next decades, hybrid multi-cores will be the predominant architecture for reconfigurable FPGA-based systems. Temperature-aware thread mapping strategies are key for providing dependability in such systems. These strategies rely on measuring the temperature distribution and redicting the thermal behavior of the system when there are changes to the hardware and software running on the FPGA. While there are a number of tools that use thermal models to predict temperature distributions at design time, these tools lack the flexibility to autonomously adjust to changing FPGA configurations. To address this problem we propose a temperature-aware system that empowers FPGA-based reconfigurable multi-cores to autonomously predict the on-chip temperature distribution for pro-active thread remapping. Our system obtains temperature measurements through a self-calibrating grid of sensors and uses area constrained heat-generating circuits in order to generate spatial and temporal temperature gradients. The generated temperature variations are then used to learn the free parameters of the system's thermal model. The system thus acquires an understanding of its own thermal characteristics. We implemented an FPGA system containing a net of 144 temperature sensors on a Xilinx Virtex-6 LX240T FPGA that is aware of its thermal model. Finally, we show that the temperature predictions vary less than 0.72 degree C on average compared to the measured temperature distributions at run-time."}],"file":[{"content_type":"application/pdf","success":1,"relation":"main_file","date_updated":"2018-03-14T13:49:39Z","date_created":"2018-03-14T13:49:39Z","creator":"florida","file_size":502244,"file_name":"656-2011_happe_reconfig.pdf","file_id":"1220","access_level":"closed"}],"status":"public","project":[{"grant_number":"160364472","_id":"1","name":"SFB 901"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"257906","name":"Engineering Proprioception in Computing Systems","_id":"31"}],"_id":"656","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"ddc":["040"],"file_date_updated":"2018-03-14T13:49:39Z","language":[{"iso":"eng"}],"has_accepted_license":"1","quality_controlled":"1","year":"2011","citation":{"ama":"Happe M, Agne A, Plessl C. Measuring and Predicting Temperature Distributions on FPGAs at Run-Time. In: <i>Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>. IEEE; 2011:55-60. doi:<a href=\"https://doi.org/10.1109/ReConFig.2011.59\">10.1109/ReConFig.2011.59</a>","chicago":"Happe, Markus, Andreas Agne, and Christian Plessl. “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time.” In <i>Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, 55–60. IEEE, 2011. <a href=\"https://doi.org/10.1109/ReConFig.2011.59\">https://doi.org/10.1109/ReConFig.2011.59</a>.","ieee":"M. Happe, A. Agne, and C. Plessl, “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time,” in <i>Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, 2011, pp. 55–60, doi: <a href=\"https://doi.org/10.1109/ReConFig.2011.59\">10.1109/ReConFig.2011.59</a>.","bibtex":"@inproceedings{Happe_Agne_Plessl_2011, title={Measuring and Predicting Temperature Distributions on FPGAs at Run-Time}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2011.59\">10.1109/ReConFig.2011.59</a>}, booktitle={Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Happe, Markus and Agne, Andreas and Plessl, Christian}, year={2011}, pages={55–60} }","short":"M. Happe, A. Agne, C. Plessl, in: Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2011, pp. 55–60.","mla":"Happe, Markus, et al. “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time.” <i>Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, IEEE, 2011, pp. 55–60, doi:<a href=\"https://doi.org/10.1109/ReConFig.2011.59\">10.1109/ReConFig.2011.59</a>.","apa":"Happe, M., Agne, A., &#38; Plessl, C. (2011). Measuring and Predicting Temperature Distributions on FPGAs at Run-Time. <i>Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, 55–60. <a href=\"https://doi.org/10.1109/ReConFig.2011.59\">https://doi.org/10.1109/ReConFig.2011.59</a>"},"page":"55-60","publisher":"IEEE","date_updated":"2023-09-26T13:46:08Z","author":[{"first_name":"Markus","full_name":"Happe, Markus","last_name":"Happe"},{"first_name":"Andreas","last_name":"Agne","full_name":"Agne, Andreas"},{"first_name":"Christian","id":"16153","full_name":"Plessl, Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982"}],"date_created":"2017-10-17T12:42:59Z","title":"Measuring and Predicting Temperature Distributions on FPGAs at Run-Time","doi":"10.1109/ReConFig.2011.59"},{"title":"Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures","doi":"10.1145/1950413.1950448","date_updated":"2023-09-26T13:45:04Z","publisher":"ACM","author":[{"last_name":"Kenter","id":"3145","full_name":"Kenter, Tobias","first_name":"Tobias"},{"first_name":"Marco","full_name":"Platzner, Marco","id":"398","last_name":"Platzner"},{"orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153","full_name":"Plessl, Christian","first_name":"Christian"},{"first_name":"Michael","full_name":"Kauschke, Michael","last_name":"Kauschke"}],"date_created":"2018-04-03T15:08:13Z","place":"New York, NY, USA","year":"2011","citation":{"apa":"Kenter, T., Platzner, M., Plessl, C., &#38; Kauschke, M. (2011). Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures. <i>Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)</i>, 177–180. <a href=\"https://doi.org/10.1145/1950413.1950448\">https://doi.org/10.1145/1950413.1950448</a>","bibtex":"@inproceedings{Kenter_Platzner_Plessl_Kauschke_2011, place={New York, NY, USA}, title={Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures}, DOI={<a href=\"https://doi.org/10.1145/1950413.1950448\">10.1145/1950413.1950448</a>}, booktitle={Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)}, publisher={ACM}, author={Kenter, Tobias and Platzner, Marco and Plessl, Christian and Kauschke, Michael}, year={2011}, pages={177–180} }","mla":"Kenter, Tobias, et al. “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures.” <i>Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)</i>, ACM, 2011, pp. 177–80, doi:<a href=\"https://doi.org/10.1145/1950413.1950448\">10.1145/1950413.1950448</a>.","short":"T. Kenter, M. Platzner, C. Plessl, M. Kauschke, in: Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), ACM, New York, NY, USA, 2011, pp. 177–180.","ama":"Kenter T, Platzner M, Plessl C, Kauschke M. Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures. In: <i>Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)</i>. ACM; 2011:177-180. doi:<a href=\"https://doi.org/10.1145/1950413.1950448\">10.1145/1950413.1950448</a>","chicago":"Kenter, Tobias, Marco Platzner, Christian Plessl, and Michael Kauschke. “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures.” In <i>Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)</i>, 177–80. New York, NY, USA: ACM, 2011. <a href=\"https://doi.org/10.1145/1950413.1950448\">https://doi.org/10.1145/1950413.1950448</a>.","ieee":"T. Kenter, M. Platzner, C. Plessl, and M. Kauschke, “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures,” in <i>Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)</i>, 2011, pp. 177–180, doi: <a href=\"https://doi.org/10.1145/1950413.1950448\">10.1145/1950413.1950448</a>."},"page":"177-180","publication_identifier":{"isbn":["978-1-4503-0554-9"]},"quality_controlled":"1","keyword":["design space exploration","LLVM","partitioning","performance","estimation","funding-intel"],"language":[{"iso":"eng"}],"_id":"2200","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"status":"public","type":"conference","publication":"Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)"},{"year":"2011","citation":{"ama":"Schumacher T, Süß T, Plessl C, Platzner M. FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study. <i>Int Journal of Recon- figurable Computing (IJRC)</i>. Published online 2011. doi:<a href=\"https://doi.org/10.1155/2011/760954\">10.1155/2011/760954</a>","chicago":"Schumacher, Tobias, Tim Süß, Christian Plessl, and Marco Platzner. “FPGA Acceleration of Communication-Bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study.” <i>Int. Journal of Recon- Figurable Computing (IJRC)</i>, 2011. <a href=\"https://doi.org/10.1155/2011/760954\">https://doi.org/10.1155/2011/760954</a>.","ieee":"T. Schumacher, T. Süß, C. Plessl, and M. Platzner, “FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study,” <i>Int. Journal of Recon- figurable Computing (IJRC)</i>, 2011, doi: <a href=\"https://doi.org/10.1155/2011/760954\">10.1155/2011/760954</a>.","apa":"Schumacher, T., Süß, T., Plessl, C., &#38; Platzner, M. (2011). FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study. <i>Int. Journal of Recon- Figurable Computing (IJRC)</i>. <a href=\"https://doi.org/10.1155/2011/760954\">https://doi.org/10.1155/2011/760954</a>","short":"T. Schumacher, T. Süß, C. Plessl, M. Platzner, Int. Journal of Recon- Figurable Computing (IJRC) (2011).","bibtex":"@article{Schumacher_Süß_Plessl_Platzner_2011, title={FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study}, DOI={<a href=\"https://doi.org/10.1155/2011/760954\">10.1155/2011/760954</a>}, journal={Int. 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