@inproceedings{46890, author = {{Koester, Dirk and Güldenpenning, Iris and Schack, Thomas}}, booktitle = {{Neuromotion - Aufmerksamkeit, Automatisierung, Adaption. 9. gemeinsames dvs-Symposium der Sektionen Biomechanik, Sportmotorik und Trainingswissenschaft}}, editor = {{Wagner, H. and Bohn, C. and Eden, N.}}, location = {{Leipzig}}, pages = {{130}}, publisher = {{Uni Print}}, title = {{{Elektrophysiologische Korrelate der Wahrnehmung sportlicher Handlungen und die Rolle motorischer Expertise}}}, year = {{2012}}, } @inproceedings{46877, author = {{Schack, Thomas and Güldenpenning, Iris and Koester, Dirk}}, booktitle = {{Abstracts of the 54. Conference of Experimental Psychologists (TeaP 2012)}}, editor = {{Bröder, A and Erdfelder, E. and Hilbig, B. and Meiser, T. and Pohl, R. and Stahlberg, D.}}, location = {{Mannheim}}, pages = {{330}}, publisher = {{Pabst Science Publishers}}, title = {{{Die Rolle motorischer Expertise bei der Wahrnehmung komplexer Handlungen}}}, doi = {{https://doi.org/10.23668/psycharchives.881}}, year = {{2012}}, } @article{46724, author = {{Güldenpenning, Iris and Kunde, Wilfried and Weigelt, Matthias and Schack, Thomas}}, issn = {{2190-5142}}, journal = {{Experimental Psychology}}, number = {{5}}, pages = {{286--294}}, publisher = {{Hogrefe Publishing}}, title = {{{Priming of future states in complex motor skills}}}, doi = {{https://doi.org/10.1027/1618-3169/a000156}}, volume = {{59}}, year = {{2012}}, } @inproceedings{46909, author = {{Güldenpenning, Iris and Spiegel, Marnie Ann and Schack, Thomas}}, booktitle = {{Abstracts of the 54. Conference of Experimental Psychologists (TeaP 2012)}}, editor = {{Bröder, A. and Erdfelder, E. and Hilbig, B. and Meiser, T. and Pohl, R. and Stahlberg, D.}}, location = {{Lengerich}}, pages = {{46}}, publisher = {{Pabst Science Publishers}}, title = {{{That’s how we roll - Learning the Kayak Roll improves the ability to mentally rotate objects}}}, doi = {{https://doi.org/10.23668/psycharchives.881}}, year = {{2012}}, } @inproceedings{47037, author = {{Güldenpenning, Iris and Braun, J. and Schack, T.}}, booktitle = {{Kongress der Deutschen Gesellschaft für Psychologie (DGPs)}}, editor = {{Riemann, R.}}, pages = {{391--392}}, publisher = {{Pabst Science Publishers}}, title = {{{Unconscious processing of feint and non-feint actions}}}, year = {{2012}}, } @inproceedings{47038, author = {{Koester, D. and Güldenpenning, Iris and Schack, T.}}, booktitle = {{48. Kongress der Deutschen Gesellschaft für Psychologie (DGPs)}}, editor = {{Riemann, R.}}, pages = {{169}}, publisher = {{Pabst Science Publishers}}, title = {{{Zur Funktion motorischer Expertise in der Bewegungswahrnehmung: Eine EEG-Studie}}}, year = {{2012}}, } @article{44652, author = {{Brandl-Bredenbeck, Hans-Peter and Kämpfe, Astrid and Köster, Carolin}}, journal = {{ForschungsForum Paderborn}}, pages = {{40--46}}, title = {{{Gesund und erfolgreich in Paderborn studieren (GriPs): Analyse studentischer Lebensstile}}}, volume = {{15}}, year = {{2012}}, } @inproceedings{44653, author = {{Köster, Carolin and Brandl-Bredenbeck, Hans-Peter and Kämpfe, Astrid}}, pages = {{1--6}}, title = {{{„Hol dir deinen beneFIT“ : Einführung eines Gesundheitspasses für Studierende an der Universität Paderborn. Dokumentation 17. bundesweiter Kongress Armut und Gesundheit: 9./10. März 2012 in Berlin.}}}, year = {{2012}}, } @inproceedings{46920, author = {{Koester, Dirk and Güldenpenning, Iris and Schack, Thomas}}, booktitle = {{Tagungsband des 48. Kongress der Deutschen Gesellschaft für Psychologie (DGPs)}}, title = {{{Zur Funktion motorischer Expertisen in der Bewegungswahrnehmung: Eine EEG-Studie}}}, year = {{2012}}, } @inproceedings{46919, author = {{Koester, Dirk and Güldenpenning, Iris and Schack, Thomas}}, booktitle = {{48. Kongress der Deutschen Gesellschaft für Psychologie (DGPs)}}, editor = {{Riemann, R.}}, location = {{Bielefeld}}, pages = {{169}}, publisher = {{Pabst Science Publishers}}, title = {{{Zur Funktion motorischer Expertise in der Bewegungswahrnehmung: Eine EEG-Studie}}}, year = {{2012}}, } @inproceedings{46918, author = {{Güldenpenning, Iris and Braun, Jelena and Schack, Thomas}}, booktitle = {{48. Kongress der Deutschen Gesellschaft für Psychologie (DGPS)}}, editor = {{Riemann, R.}}, location = {{Bielefeld}}, pages = {{391--392}}, publisher = {{Pabst Science Publishers}}, title = {{{Unconscious processing of feint and non-feint actions}}}, year = {{2012}}, } @inproceedings{2106, abstract = {{Although the benefits of FPGAs for accelerating scientific codes are widely acknowledged, the use of FPGA accelerators in scientific computing is not widespread because reaping these benefits requires knowledge of hardware design methods and tools that is typically not available with domain scientists. A promising but hardly investigated approach is to develop tool flows that keep the common languages for scientific code (C,C++, and Fortran) and allow the developer to augment the source code with OpenMPlike directives for instructing the compiler which parts of the application shall be offloaded the FPGA accelerator. In this work we study whether the promise of effective FPGA acceleration with an OpenMP-like programming effort can actually be held. Our target system is the Convey HC-1 reconfigurable computer for which an OpenMP-like programming environment exists. As case study we use an application from computational nanophotonics. Our results show that a developer without previous FPGA experience could create an FPGA-accelerated application that is competitive to an optimized OpenMP-parallelized CPU version running on a two socket quad-core server. Finally, we discuss our experiences with this tool flow and the Convey HC-1 from a productivity and economic point of view.}}, author = {{Meyer, Björn and Schumacher, Jörn and Plessl, Christian and Förstner, Jens}}, booktitle = {{Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}}, keywords = {{funding-upb-forschungspreis, funding-maxup, tet_topic_hpc}}, pages = {{189--196}}, publisher = {{IEEE}}, title = {{{Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?}}}, doi = {{10.1109/FPL.2012.6339370}}, year = {{2012}}, } @article{2108, author = {{Schumacher, Tobias and Plessl, Christian and Platzner, Marco}}, issn = {{0141-9331}}, journal = {{Microprocessors and Microsystems}}, keywords = {{funding-altera}}, number = {{2}}, pages = {{110--126}}, title = {{{IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators}}}, doi = {{10.1016/j.micpro.2011.04.002}}, volume = {{36}}, year = {{2012}}, } @inproceedings{615, abstract = {{Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, the accuracy of the simulations is to some extent questionable and they require a high computational effort if a detailed thermal model is used.For experimental evaluation of real-world temperature management methods, often synthetic heat sources are employed. Therefore, in this paper we investigated the question if we can create significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments in contrast to simulations. Therefore, we have developed eight different heat-generating cores that use different subsets of the FPGA resources. Our experimental results show that, according to the built-in thermal diode of our Xilinx Virtex-5 FPGA, we can increase the chip temperature by 134 degree C in less than 12 minutes by only utilizing about 21% of the slices.}}, author = {{Happe, Markus and Hangmann, Hendrik and Agne, Andreas and Plessl, Christian}}, booktitle = {{Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)}}, pages = {{1--8}}, publisher = {{IEEE}}, title = {{{Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators}}}, doi = {{10.1109/ReConFig.2012.6416745}}, year = {{2012}}, } @inproceedings{591, abstract = {{One major obstacle for a wide spread FPGA usage in general-purpose computing is the development tool flow that requires much higher effort than for pure software solutions. Convey Computer promises a solution to this problem for their HC-1 platform, where the FPGAs are configured to run as a vector processor and the software source code can be annotated with pragmas that guide an automated vectorization process. We investigate this approach for a stereo matching algorithm that has abundant parallelism and a number of different computational patterns. We note that for this case study the automated vectorization in its current state doesn’t hold its productivity promise. However, we also show that using the Vector Personality can yield a significant speedups compared to CPU implementations in two of three investigated phases of the algorithm. Those speedups don’t match custom FPGA implementations, but can come with much reduced development effort.}}, author = {{Kenter, Tobias and Plessl, Christian and Schmitz, Henning}}, booktitle = {{Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}}, pages = {{1--8}}, publisher = {{IEEE}}, title = {{{Pragma based parallelization - Trading hardware efficiency for ease of use?}}}, doi = {{10.1109/ReConFig.2012.6416773}}, year = {{2012}}, } @inproceedings{609, abstract = {{Today's design and operation principles and methods do not scale well with future reconfigurable computing systems due to an increased complexity in system architectures and applications, run-time dynamics and corresponding requirements. Hence, novel design and operation principles and methods are needed that possibly break drastically with the static ones we have built into our systems and the fixed abstraction layers we have cherished over the last decades. Thus, we propose a HW/SW platform that collects and maintains information about its state and progress which enables the system to reason about its behavior (self-awareness) and utilizes its knowledge to effectively and autonomously adapt its behavior to changing requirements (self-expression).To enable self-awareness, our compute nodes collect information using a variety of sensors, i.e. performance counters and thermal diodes, and use internal self-awareness models that process these information. For self-awareness, on-line learning is crucial such that the node learns and continuously updates its models at run-time to react to changing conditions. To enable self-expression, we break with the classic design-time abstraction layers of hardware, operating system and software. In contrast, our system is able to vertically migrate functionalities between the layers at run-time to exploit trade-offs between abstraction and optimization.This paper presents a heterogeneous multi-core architecture, that enables self-awareness and self-expression, an operating system for our proposed hardware/software platform and a novel self-expression method.}}, author = {{Happe, Markus and Agne, Andreas and Plessl, Christian and Platzner, Marco}}, booktitle = {{Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)}}, pages = {{8--9}}, title = {{{Hardware/Software Platform for Self-aware Compute Nodes}}}, year = {{2012}}, } @inproceedings{567, abstract = {{Heterogeneous machines are gaining momentum in the High Performance Computing field, due to the theoretical speedups and power consumption. In practice, while some applications meet the performance expectations, heterogeneous architectures still require a tremendous effort from the application developers. This work presents a code generation method to port codes into heterogeneous platforms, based on transformations of the control flow into function calls. The results show that the cost of the function-call mechanism is affordable for the tested HPC kernels. The complete toolchain, based on the LLVM compiler infrastructure, is fully automated once the sequential specification is provided.}}, author = {{Barrio, Pablo and Carreras, Carlos and Sierra, Roberto and Kenter, Tobias and Plessl, Christian}}, booktitle = {{Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)}}, pages = {{559--565}}, publisher = {{IEEE}}, title = {{{Turning control flow graphs into function calls: Code generation for heterogeneous architectures}}}, doi = {{10.1109/HPCSim.2012.6266973}}, year = {{2012}}, } @inproceedings{612, abstract = {{While numerous publications have presented ring oscillator designs for temperature measurements a detailed study of the ring oscillator's design space is still missing. In this work, we introduce metrics for comparing the performance and area efficiency of ring oscillators and a methodology for determining these metrics. As a result, we present a systematic study of the design space for ring oscillators for a Xilinx Virtex-5 platform FPGA.}}, author = {{Rüthing, Christoph and Happe, Markus and Agne, Andreas and Plessl, Christian}}, booktitle = {{Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)}}, pages = {{559--562}}, publisher = {{IEEE}}, title = {{{Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs}}}, doi = {{10.1109/FPL.2012.6339370}}, year = {{2012}}, } @inproceedings{2180, author = {{Beisel, Tobias and Wiersema, Tobias and Plessl, Christian and Brinkmann, André}}, booktitle = {{Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS)}}, keywords = {{funding-enhance}}, title = {{{Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux}}}, year = {{2012}}, } @article{2177, author = {{Grad, Mariusz and Plessl, Christian}}, journal = {{Int. Journal of Reconfigurable Computing (IJRC)}}, publisher = {{Hindawi Publishing Corp.}}, title = {{{On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors}}}, doi = {{10.1155/2012/418315}}, year = {{2012}}, }