[{"has_accepted_license":"1","status":"public","ddc":["040"],"user_id":"15278","_id":"591","publisher":"IEEE","page":"1-8","project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"Engineering Proprioception in Computing Systems","grant_number":"257906","_id":"31"}],"quality_controlled":"1","citation":{"short":"T. Kenter, C. Plessl, H. Schmitz, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8.","chicago":"Kenter, Tobias, Christian Plessl, and Henning Schmitz. “Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?” In <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 1–8. IEEE, 2012. <a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">https://doi.org/10.1109/ReConFig.2012.6416773</a>.","apa":"Kenter, T., Plessl, C., &#38; Schmitz, H. (2012). Pragma based parallelization - Trading hardware efficiency for ease of use? <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 1–8. <a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">https://doi.org/10.1109/ReConFig.2012.6416773</a>","ieee":"T. Kenter, C. Plessl, and H. Schmitz, “Pragma based parallelization - Trading hardware efficiency for ease of use?,” in <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 2012, pp. 1–8, doi: <a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">10.1109/ReConFig.2012.6416773</a>.","ama":"Kenter T, Plessl C, Schmitz H. Pragma based parallelization - Trading hardware efficiency for ease of use? In: <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>. IEEE; 2012:1-8. doi:<a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">10.1109/ReConFig.2012.6416773</a>","bibtex":"@inproceedings{Kenter_Plessl_Schmitz_2012, title={Pragma based parallelization - Trading hardware efficiency for ease of use?}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">10.1109/ReConFig.2012.6416773</a>}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Plessl, Christian and Schmitz, Henning}, year={2012}, pages={1–8} }","mla":"Kenter, Tobias, et al. “Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?” <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, IEEE, 2012, pp. 1–8, doi:<a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">10.1109/ReConFig.2012.6416773</a>."},"file_date_updated":"2018-03-15T08:33:18Z","date_updated":"2023-09-26T13:41:08Z","author":[{"id":"3145","full_name":"Kenter, Tobias","first_name":"Tobias","last_name":"Kenter"},{"full_name":"Plessl, Christian","last_name":"Plessl","first_name":"Christian","orcid":"0000-0001-5728-9982","id":"16153"},{"first_name":"Henning","last_name":"Schmitz","full_name":"Schmitz, Henning"}],"title":"Pragma based parallelization - Trading hardware efficiency for ease of use?","year":"2012","doi":"10.1109/ReConFig.2012.6416773","language":[{"iso":"eng"}],"abstract":[{"text":"One major obstacle for a wide spread FPGA usage in general-purpose computing is the development tool flow that requires much higher effort than for pure software solutions. Convey Computer promises a solution to this problem for their HC-1 platform, where the FPGAs are configured to run as a vector processor and the software source code can be annotated with pragmas that guide an automated vectorization process. We investigate this approach for a stereo matching algorithm that has abundant parallelism and a number of different computational patterns. We note that for this case study the automated vectorization in its current state doesn’t hold its productivity promise. However, we also show that using the Vector Personality can yield a significant speedups compared to CPU implementations in two of three investigated phases of the algorithm. Those speedups don’t match custom FPGA implementations, but can come with much reduced development effort.","lang":"eng"}],"publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"type":"conference","date_created":"2017-10-17T12:42:47Z","file":[{"file_id":"1257","success":1,"content_type":"application/pdf","file_name":"591-ReConFig2012Kenter_Schmitz_Plessl.pdf","file_size":371235,"access_level":"closed","relation":"main_file","date_updated":"2018-03-15T08:33:18Z","date_created":"2018-03-15T08:33:18Z","creator":"florida"}]},{"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"type":"conference","date_created":"2017-10-17T12:42:50Z","file":[{"date_created":"2018-03-15T08:14:17Z","creator":"florida","file_id":"1249","success":1,"content_type":"application/pdf","file_name":"609-happe12_fpl_awareness.pdf","access_level":"closed","file_size":146789,"relation":"main_file","date_updated":"2018-03-15T08:14:17Z"}],"abstract":[{"lang":"eng","text":"Today's design and operation principles and methods do not scale well with future reconfigurable computing systems due to an increased complexity in system architectures and applications, run-time dynamics and corresponding requirements. Hence, novel design and operation principles and methods are needed that possibly break drastically with the static ones we have built into our systems and the fixed abstraction layers we have cherished over the last decades. Thus, we propose a HW/SW platform that collects and maintains information about its state and progress which enables the system to reason about its behavior (self-awareness) and utilizes its knowledge to effectively and autonomously adapt its behavior to changing requirements (self-expression).To enable self-awareness, our compute nodes collect information using a variety of sensors, i.e. performance counters and thermal diodes, and use internal self-awareness models that process these information. For self-awareness, on-line learning is crucial such that the node learns and continuously updates its models at run-time to react to changing conditions. To enable self-expression, we break with the classic design-time abstraction layers of hardware, operating system and software. In contrast, our system is able to vertically migrate functionalities between the layers at run-time to exploit trade-offs between abstraction and optimization.This paper presents a heterogeneous multi-core architecture, that enables self-awareness and self-expression, an operating system for our proposed hardware/software platform and a novel self-expression method."}],"publication":"Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:41:36Z","author":[{"full_name":"Happe, Markus","first_name":"Markus","last_name":"Happe"},{"full_name":"Agne, Andreas","last_name":"Agne","first_name":"Andreas"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian","id":"16153"},{"full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco","id":"398"}],"year":"2012","title":"Hardware/Software Platform for Self-aware Compute Nodes","project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"name":"SFB 901 - Subprojekt C2","_id":"14","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"Engineering Proprioception in Computing Systems","_id":"31","grant_number":"257906"}],"quality_controlled":"1","citation":{"bibtex":"@inproceedings{Happe_Agne_Plessl_Platzner_2012, title={Hardware/Software Platform for Self-aware Compute Nodes}, booktitle={Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)}, author={Happe, Markus and Agne, Andreas and Plessl, Christian and Platzner, Marco}, year={2012}, pages={8–9} }","chicago":"Happe, Markus, Andreas Agne, Christian Plessl, and Marco Platzner. “Hardware/Software Platform for Self-Aware Compute Nodes.” In <i>Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)</i>, 8–9, 2012.","ama":"Happe M, Agne A, Plessl C, Platzner M. Hardware/Software Platform for Self-aware Compute Nodes. In: <i>Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)</i>. ; 2012:8-9.","short":"M. Happe, A. Agne, C. Plessl, M. Platzner, in: Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9.","ieee":"M. Happe, A. Agne, C. Plessl, and M. Platzner, “Hardware/Software Platform for Self-aware Compute Nodes,” in <i>Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)</i>, 2012, pp. 8–9.","mla":"Happe, Markus, et al. “Hardware/Software Platform for Self-Aware Compute Nodes.” <i>Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)</i>, 2012, pp. 8–9.","apa":"Happe, M., Agne, A., Plessl, C., &#38; Platzner, M. (2012). Hardware/Software Platform for Self-aware Compute Nodes. <i>Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)</i>, 8–9."},"file_date_updated":"2018-03-15T08:14:17Z","ddc":["040"],"user_id":"15278","_id":"609","page":"8-9","has_accepted_license":"1","status":"public"},{"date_updated":"2023-09-26T13:42:54Z","author":[{"last_name":"Barrio","first_name":"Pablo","full_name":"Barrio, Pablo"},{"last_name":"Carreras","first_name":"Carlos","full_name":"Carreras, Carlos"},{"full_name":"Sierra, Roberto","last_name":"Sierra","first_name":"Roberto"},{"id":"3145","last_name":"Kenter","first_name":"Tobias","full_name":"Kenter, Tobias"},{"full_name":"Plessl, Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153"}],"title":"Turning control flow graphs into function calls: Code generation for heterogeneous architectures","year":"2012","doi":"10.1109/HPCSim.2012.6266973","language":[{"iso":"eng"}],"abstract":[{"text":"Heterogeneous machines are gaining momentum in the High Performance Computing field, due to the theoretical speedups and power consumption. In practice, while some applications meet the performance expectations, heterogeneous architectures still require a tremendous effort from the application developers. This work presents a code generation method to port codes into heterogeneous platforms, based on transformations of the control flow into function calls. The results show that the cost of the function-call mechanism is affordable for the tested HPC kernels. The complete toolchain, based on the LLVM compiler infrastructure, is fully automated once the sequential specification is provided.","lang":"eng"}],"publication":"Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"type":"conference","date_created":"2017-10-17T12:42:42Z","file":[{"file_id":"1275","content_type":"application/pdf","success":1,"relation":"main_file","date_updated":"2018-03-15T10:20:24Z","file_name":"567-ba-ca-12a.pdf","file_size":288508,"access_level":"closed","date_created":"2018-03-15T10:20:24Z","creator":"florida"}],"has_accepted_license":"1","status":"public","ddc":["040"],"user_id":"15278","publisher":"IEEE","_id":"567","page":"559-565","project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"name":"SFB 901 - Subprojekt C2","_id":"14","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"}],"quality_controlled":"1","citation":{"mla":"Barrio, Pablo, et al. “Turning Control Flow Graphs into Function Calls: Code Generation for Heterogeneous Architectures.” <i>Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)</i>, IEEE, 2012, pp. 559–65, doi:<a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">10.1109/HPCSim.2012.6266973</a>.","ama":"Barrio P, Carreras C, Sierra R, Kenter T, Plessl C. Turning control flow graphs into function calls: Code generation for heterogeneous architectures. In: <i>Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)</i>. IEEE; 2012:559-565. doi:<a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">10.1109/HPCSim.2012.6266973</a>","bibtex":"@inproceedings{Barrio_Carreras_Sierra_Kenter_Plessl_2012, title={Turning control flow graphs into function calls: Code generation for heterogeneous architectures}, DOI={<a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">10.1109/HPCSim.2012.6266973</a>}, booktitle={Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)}, publisher={IEEE}, author={Barrio, Pablo and Carreras, Carlos and Sierra, Roberto and Kenter, Tobias and Plessl, Christian}, year={2012}, pages={559–565} }","apa":"Barrio, P., Carreras, C., Sierra, R., Kenter, T., &#38; Plessl, C. (2012). Turning control flow graphs into function calls: Code generation for heterogeneous architectures. <i>Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)</i>, 559–565. <a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">https://doi.org/10.1109/HPCSim.2012.6266973</a>","ieee":"P. Barrio, C. Carreras, R. Sierra, T. Kenter, and C. Plessl, “Turning control flow graphs into function calls: Code generation for heterogeneous architectures,” in <i>Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)</i>, 2012, pp. 559–565, doi: <a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">10.1109/HPCSim.2012.6266973</a>.","short":"P. Barrio, C. Carreras, R. Sierra, T. Kenter, C. Plessl, in: Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), IEEE, 2012, pp. 559–565.","chicago":"Barrio, Pablo, Carlos Carreras, Roberto Sierra, Tobias Kenter, and Christian Plessl. “Turning Control Flow Graphs into Function Calls: Code Generation for Heterogeneous Architectures.” In <i>Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)</i>, 559–65. IEEE, 2012. <a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">https://doi.org/10.1109/HPCSim.2012.6266973</a>."},"file_date_updated":"2018-03-15T10:20:24Z"},{"date_created":"2017-10-17T12:42:51Z","file":[{"date_created":"2018-03-15T06:49:03Z","creator":"florida","content_type":"application/pdf","success":1,"file_id":"1247","file_size":202923,"access_level":"closed","file_name":"612-ruething_fpl12.pdf","date_updated":"2018-03-15T06:49:03Z","relation":"main_file"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"type":"conference","publication":"Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)","abstract":[{"lang":"eng","text":"While numerous publications have presented ring oscillator designs for temperature measurements a detailed study of the ring oscillator's design space is still missing. In this work, we introduce metrics for comparing the performance and area efficiency of ring oscillators and a methodology for determining these metrics. As a result, we present a systematic study of the design space for ring oscillators for a Xilinx Virtex-5 platform FPGA."}],"language":[{"iso":"eng"}],"doi":"10.1109/FPL.2012.6339370","author":[{"full_name":"Rüthing, Christoph","first_name":"Christoph","last_name":"Rüthing"},{"first_name":"Markus","last_name":"Happe","full_name":"Happe, Markus"},{"last_name":"Agne","first_name":"Andreas","full_name":"Agne, Andreas"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian","id":"16153"}],"year":"2012","title":"Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs","date_updated":"2023-09-26T13:42:03Z","citation":{"ama":"Rüthing C, Happe M, Agne A, Plessl C. Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs. In: <i>Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)</i>. IEEE; 2012:559-562. doi:<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>","bibtex":"@inproceedings{Rüthing_Happe_Agne_Plessl_2012, title={Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs}, DOI={<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>}, booktitle={Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Rüthing, Christoph and Happe, Markus and Agne, Andreas and Plessl, Christian}, year={2012}, pages={559–562} }","mla":"Rüthing, Christoph, et al. “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs.” <i>Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)</i>, IEEE, 2012, pp. 559–62, doi:<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>.","chicago":"Rüthing, Christoph, Markus Happe, Andreas Agne, and Christian Plessl. “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs.” In <i>Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)</i>, 559–62. IEEE, 2012. <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">https://doi.org/10.1109/FPL.2012.6339370</a>.","short":"C. Rüthing, M. Happe, A. Agne, C. Plessl, in: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 559–562.","apa":"Rüthing, C., Happe, M., Agne, A., &#38; Plessl, C. (2012). Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs. <i>Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)</i>, 559–562. <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">https://doi.org/10.1109/FPL.2012.6339370</a>","ieee":"C. Rüthing, M. Happe, A. Agne, and C. Plessl, “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs,” in <i>Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)</i>, 2012, pp. 559–562, doi: <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>."},"file_date_updated":"2018-03-15T06:49:03Z","project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Engineering Proprioception in Computing Systems","grant_number":"257906","_id":"31"}],"quality_controlled":"1","_id":"612","publisher":"IEEE","page":"559-562","user_id":"15278","ddc":["040"],"status":"public","has_accepted_license":"1"},{"author":[{"last_name":"Beisel","first_name":"Tobias","full_name":"Beisel, Tobias"},{"id":"3118","full_name":"Wiersema, Tobias","first_name":"Tobias","last_name":"Wiersema"},{"id":"16153","full_name":"Plessl, Christian","last_name":"Plessl","first_name":"Christian","orcid":"0000-0001-5728-9982"},{"full_name":"Brinkmann, André","first_name":"André","last_name":"Brinkmann"}],"title":"Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux","year":"2012","status":"public","date_updated":"2023-09-26T13:40:17Z","_id":"2180","language":[{"iso":"eng"}],"user_id":"15278","citation":{"mla":"Beisel, Tobias, et al. “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux.” <i>Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS)</i>, 2012.","bibtex":"@inproceedings{Beisel_Wiersema_Plessl_Brinkmann_2012, title={Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux}, booktitle={Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS)}, author={Beisel, Tobias and Wiersema, Tobias and Plessl, Christian and Brinkmann, André}, year={2012} }","ama":"Beisel T, Wiersema T, Plessl C, Brinkmann A. Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux. In: <i>Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS)</i>. ; 2012.","ieee":"T. Beisel, T. Wiersema, C. Plessl, and A. Brinkmann, “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux,” 2012.","apa":"Beisel, T., Wiersema, T., Plessl, C., &#38; Brinkmann, A. (2012). Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux. <i>Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS)</i>.","short":"T. Beisel, T. Wiersema, C. Plessl, A. Brinkmann, in: Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS), 2012.","chicago":"Beisel, Tobias, Tobias Wiersema, Christian Plessl, and André Brinkmann. “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux.” In <i>Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS)</i>, 2012."},"publication":"Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS)","project":[{"name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","grant_number":"01|H11004A","_id":"30"}],"quality_controlled":"1","date_created":"2018-04-03T09:18:33Z","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"keyword":["funding-enhance"],"type":"conference"},{"language":[{"iso":"eng"}],"_id":"2177","publisher":"Hindawi Publishing Corp.","doi":"10.1155/2012/418315","user_id":"15278","author":[{"full_name":"Grad, Mariusz","first_name":"Mariusz","last_name":"Grad"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian","full_name":"Plessl, Christian"}],"status":"public","year":"2012","title":"On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors","date_updated":"2023-09-26T13:39:48Z","date_created":"2018-04-03T09:13:22Z","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"type":"journal_article","citation":{"ieee":"M. Grad and C. Plessl, “On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors,” <i>Int. Journal of Reconfigurable Computing (IJRC)</i>, 2012, doi: <a href=\"https://doi.org/10.1155/2012/418315\">10.1155/2012/418315</a>.","apa":"Grad, M., &#38; Plessl, C. (2012). On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors. <i>Int. Journal of Reconfigurable Computing (IJRC)</i>. <a href=\"https://doi.org/10.1155/2012/418315\">https://doi.org/10.1155/2012/418315</a>","mla":"Grad, Mariusz, and Christian Plessl. “On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors.” <i>Int. Journal of Reconfigurable Computing (IJRC)</i>, Hindawi Publishing Corp., 2012, doi:<a href=\"https://doi.org/10.1155/2012/418315\">10.1155/2012/418315</a>.","bibtex":"@article{Grad_Plessl_2012, title={On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors}, DOI={<a href=\"https://doi.org/10.1155/2012/418315\">10.1155/2012/418315</a>}, journal={Int. Journal of Reconfigurable Computing (IJRC)}, publisher={Hindawi Publishing Corp.}, author={Grad, Mariusz and Plessl, Christian}, year={2012} }","short":"M. Grad, C. Plessl, Int. Journal of Reconfigurable Computing (IJRC) (2012).","ama":"Grad M, Plessl C. On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors. <i>Int Journal of Reconfigurable Computing (IJRC)</i>. Published online 2012. doi:<a href=\"https://doi.org/10.1155/2012/418315\">10.1155/2012/418315</a>","chicago":"Grad, Mariusz, and Christian Plessl. “On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors.” <i>Int. Journal of Reconfigurable Computing (IJRC)</i>, 2012. <a href=\"https://doi.org/10.1155/2012/418315\">https://doi.org/10.1155/2012/418315</a>."},"publication":"Int. Journal of Reconfigurable Computing (IJRC)","quality_controlled":"1"},{"date_created":"2024-10-07T18:01:43Z","type":"book_chapter","publication":"The Internet & Surveillance","citation":{"ama":"Sandoval M. Consumer surveillance on web 2.0. In: Fuchs C, Boersma K, Albrechtslund A, Sandoval M, eds. <i>The Internet &#38; Surveillance</i>. Routledge; 2012.","bibtex":"@inbook{Sandoval_2012, title={Consumer surveillance on web 2.0}, booktitle={The Internet &#38; Surveillance}, publisher={Routledge}, author={Sandoval, Marisol}, editor={Fuchs, Christian and Boersma, Kees and Albrechtslund, Anders and Sandoval, Marisol}, year={2012} }","mla":"Sandoval, Marisol. “Consumer Surveillance on Web 2.0.” <i>The Internet &#38; Surveillance</i>, edited by Christian Fuchs et al., Routledge, 2012.","short":"M. Sandoval, in: C. Fuchs, K. Boersma, A. Albrechtslund, M. Sandoval (Eds.), The Internet &#38; Surveillance, Routledge, 2012.","chicago":"Sandoval, Marisol. “Consumer Surveillance on Web 2.0.” In <i>The Internet &#38; Surveillance</i>, edited by Christian Fuchs, Kees Boersma, Anders Albrechtslund, and Marisol Sandoval. Routledge, 2012.","apa":"Sandoval, M. (2012). Consumer surveillance on web 2.0. In C. Fuchs, K. Boersma, A. Albrechtslund, &#38; M. Sandoval (Eds.), <i>The Internet &#38; Surveillance</i>. Routledge.","ieee":"M. Sandoval, “Consumer surveillance on web 2.0,” in <i>The Internet &#38; Surveillance</i>, C. Fuchs, K. Boersma, A. Albrechtslund, and M. Sandoval, Eds. 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