[{"year":"2014","citation":{"short":"J. vom Brocke, S. Debortoli, O. Müller, N. Reuter, Communications of the Association for Information Systems 34 (2014) 7.","bibtex":"@article{vom Brocke_Debortoli_Müller_Reuter_2014, title={How In-memory Technology Can Create Business Value: Insights from the Hilti Case}, volume={34}, DOI={<a href=\"https://doi.org/10.17705/1cais.03407\">10.17705/1cais.03407</a>}, number={1}, journal={Communications of the Association for Information Systems}, author={vom Brocke, Jan and Debortoli, Stefan and Müller, Oliver and Reuter, Nadine}, year={2014}, pages={7} }","mla":"vom Brocke, Jan, et al. “How In-Memory Technology Can Create Business Value: Insights from the Hilti Case.” <i>Communications of the Association for Information Systems</i>, vol. 34, no. 1, 2014, p. 7, doi:<a href=\"https://doi.org/10.17705/1cais.03407\">10.17705/1cais.03407</a>.","apa":"vom Brocke, J., Debortoli, S., Müller, O., &#38; Reuter, N. (2014). How In-memory Technology Can Create Business Value: Insights from the Hilti Case. <i>Communications of the Association for Information Systems</i>, <i>34</i>(1), 7. <a href=\"https://doi.org/10.17705/1cais.03407\">https://doi.org/10.17705/1cais.03407</a>","ieee":"J. vom Brocke, S. Debortoli, O. Müller, and N. Reuter, “How In-memory Technology Can Create Business Value: Insights from the Hilti Case,” <i>Communications of the Association for Information Systems</i>, vol. 34, no. 1, p. 7, 2014.","chicago":"Brocke, Jan vom, Stefan Debortoli, Oliver Müller, and Nadine Reuter. “How In-Memory Technology Can Create Business Value: Insights from the Hilti Case.” <i>Communications of the Association for Information Systems</i> 34, no. 1 (2014): 7. <a href=\"https://doi.org/10.17705/1cais.03407\">https://doi.org/10.17705/1cais.03407</a>.","ama":"vom Brocke J, Debortoli S, Müller O, Reuter N. How In-memory Technology Can Create Business Value: Insights from the Hilti Case. <i>Communications of the Association for Information Systems</i>. 2014;34(1):7. doi:<a href=\"https://doi.org/10.17705/1cais.03407\">10.17705/1cais.03407</a>"},"page":"7","intvolume":"        34","publication_status":"published","publication_identifier":{"issn":["1529-3181"]},"issue":"1","title":"How In-memory Technology Can Create Business Value: Insights from the Hilti Case","doi":"10.17705/1cais.03407","date_updated":"2022-01-06T06:53:05Z","author":[{"first_name":"Jan","last_name":"vom Brocke","full_name":"vom Brocke, Jan"},{"first_name":"Stefan","full_name":"Debortoli, Stefan","last_name":"Debortoli"},{"id":"72849","full_name":"Müller, Oliver","last_name":"Müller","first_name":"Oliver"},{"first_name":"Nadine","full_name":"Reuter, Nadine","last_name":"Reuter"}],"date_created":"2020-06-23T07:25:51Z","volume":34,"status":"public","type":"journal_article","publication":"Communications of the Association for Information Systems","language":[{"iso":"eng"}],"extern":"1","_id":"17118","user_id":"71922","department":[{"_id":"196"}]},{"doi":"10.1109/TCIAIG.2014.2346997","title":"A Novel Technique and its Application to Computer Go","date_created":"2019-07-10T09:22:43Z","author":[{"first_name":"Lars","full_name":"Schaefers, Lars","last_name":"Schaefers"},{"last_name":"Platzner","full_name":"Platzner, Marco","id":"398","first_name":"Marco"}],"volume":6,"date_updated":"2022-01-06T06:50:47Z","citation":{"chicago":"Schaefers, Lars, and Marco Platzner. “A Novel Technique and Its Application to Computer Go.” <i>IEEE Transactions on Computational Intelligence and AI in Games</i> 6, no. 3 (2014): 361–74. <a href=\"https://doi.org/10.1109/TCIAIG.2014.2346997\">https://doi.org/10.1109/TCIAIG.2014.2346997</a>.","ieee":"L. Schaefers and M. Platzner, “A Novel Technique and its Application to Computer Go,” <i>IEEE Transactions on Computational Intelligence and AI in Games</i>, vol. 6, no. 3, pp. 361–374, 2014.","ama":"Schaefers L, Platzner M. A Novel Technique and its Application to Computer Go. <i>IEEE Transactions on Computational Intelligence and AI in Games</i>. 2014;6(3):361-374. doi:<a href=\"https://doi.org/10.1109/TCIAIG.2014.2346997\">10.1109/TCIAIG.2014.2346997</a>","short":"L. Schaefers, M. Platzner, IEEE Transactions on Computational Intelligence and AI in Games 6 (2014) 361–374.","bibtex":"@article{Schaefers_Platzner_2014, title={A Novel Technique and its Application to Computer Go}, volume={6}, DOI={<a href=\"https://doi.org/10.1109/TCIAIG.2014.2346997\">10.1109/TCIAIG.2014.2346997</a>}, number={3}, journal={IEEE Transactions on Computational Intelligence and AI in Games}, author={Schaefers, Lars and Platzner, Marco}, year={2014}, pages={361–374} }","mla":"Schaefers, Lars, and Marco Platzner. “A Novel Technique and Its Application to Computer Go.” <i>IEEE Transactions on Computational Intelligence and AI in Games</i>, vol. 6, no. 3, 2014, pp. 361–74, doi:<a href=\"https://doi.org/10.1109/TCIAIG.2014.2346997\">10.1109/TCIAIG.2014.2346997</a>.","apa":"Schaefers, L., &#38; Platzner, M. (2014). A Novel Technique and its Application to Computer Go. <i>IEEE Transactions on Computational Intelligence and AI in Games</i>, <i>6</i>(3), 361–374. <a href=\"https://doi.org/10.1109/TCIAIG.2014.2346997\">https://doi.org/10.1109/TCIAIG.2014.2346997</a>"},"page":"361-374","intvolume":"         6","year":"2014","issue":"3","language":[{"iso":"eng"}],"user_id":"3118","department":[{"_id":"78"}],"_id":"10602","status":"public","type":"journal_article","publication":"IEEE Transactions on Computational Intelligence and AI in Games"},{"status":"public","publication":"IEEE Transactions on Computers","type":"journal_article","language":[{"iso":"eng"}],"_id":"10603","department":[{"_id":"78"}],"user_id":"398","year":"2014","page":"2919 - 2932","intvolume":"        63","citation":{"chicago":"Giefers, Heiner, and Marco Platzner. “An FPGA-Based Reconfigurable Mesh Many-Core.” <i>IEEE Transactions on Computers</i> 63, no. 12 (2014): 2919–32. <a href=\"https://doi.org/10.1109/TC.2013.174\">https://doi.org/10.1109/TC.2013.174</a>.","ieee":"H. Giefers and M. Platzner, “An FPGA-based Reconfigurable Mesh Many-Core,” <i>IEEE Transactions on Computers</i>, vol. 63, no. 12, pp. 2919–2932, 2014.","ama":"Giefers H, Platzner M. An FPGA-based Reconfigurable Mesh Many-Core. <i>IEEE Transactions on Computers</i>. 2014;63(12):2919-2932. doi:<a href=\"https://doi.org/10.1109/TC.2013.174\">10.1109/TC.2013.174</a>","apa":"Giefers, H., &#38; Platzner, M. (2014). An FPGA-based Reconfigurable Mesh Many-Core. <i>IEEE Transactions on Computers</i>, <i>63</i>(12), 2919–2932. <a href=\"https://doi.org/10.1109/TC.2013.174\">https://doi.org/10.1109/TC.2013.174</a>","short":"H. Giefers, M. Platzner, IEEE Transactions on Computers 63 (2014) 2919–2932.","mla":"Giefers, Heiner, and Marco Platzner. “An FPGA-Based Reconfigurable Mesh Many-Core.” <i>IEEE Transactions on Computers</i>, vol. 63, no. 12, 2014, pp. 2919–32, doi:<a href=\"https://doi.org/10.1109/TC.2013.174\">10.1109/TC.2013.174</a>.","bibtex":"@article{Giefers_Platzner_2014, title={An FPGA-based Reconfigurable Mesh Many-Core}, volume={63}, DOI={<a href=\"https://doi.org/10.1109/TC.2013.174\">10.1109/TC.2013.174</a>}, number={12}, journal={IEEE Transactions on Computers}, author={Giefers, Heiner and Platzner, Marco}, year={2014}, pages={2919–2932} }"},"issue":"12","title":"An FPGA-based Reconfigurable Mesh Many-Core","doi":"10.1109/TC.2013.174","date_updated":"2022-01-06T06:50:47Z","volume":63,"author":[{"first_name":"Heiner","last_name":"Giefers","full_name":"Giefers, Heiner"},{"full_name":"Platzner, Marco","id":"398","last_name":"Platzner","first_name":"Marco"}],"date_created":"2019-07-10T09:22:44Z"},{"language":[{"iso":"eng"}],"department":[{"_id":"78"}],"user_id":"3118","series_title":"RAW","_id":"10621","status":"public","publication":"Reconfigurable Architectures Workshop (RAW)","type":"conference","doi":"10.1109/IPDPSW.2014.37","title":"FPGA Redundancy Configurations: An Automated Design Space Exploration","author":[{"first_name":"Jahanzeb","full_name":"Anwer, Jahanzeb","last_name":"Anwer"},{"full_name":"Platzner, Marco","id":"398","last_name":"Platzner","first_name":"Marco"},{"last_name":"Meisner","full_name":"Meisner, Sebastian","first_name":"Sebastian"}],"date_created":"2019-07-10T09:32:58Z","date_updated":"2022-01-06T06:50:48Z","citation":{"apa":"Anwer, J., Platzner, M., &#38; Meisner, S. (2014). FPGA Redundancy Configurations: An Automated Design Space Exploration. In <i>Reconfigurable Architectures Workshop (RAW)</i>. <a href=\"https://doi.org/10.1109/IPDPSW.2014.37\">https://doi.org/10.1109/IPDPSW.2014.37</a>","bibtex":"@inproceedings{Anwer_Platzner_Meisner_2014, series={RAW}, title={FPGA Redundancy Configurations: An Automated Design Space Exploration}, DOI={<a href=\"https://doi.org/10.1109/IPDPSW.2014.37\">10.1109/IPDPSW.2014.37</a>}, booktitle={Reconfigurable Architectures Workshop (RAW)}, author={Anwer, Jahanzeb and Platzner, Marco and Meisner, Sebastian}, year={2014}, collection={RAW} }","short":"J. Anwer, M. Platzner, S. Meisner, in: Reconfigurable Architectures Workshop (RAW), 2014.","mla":"Anwer, Jahanzeb, et al. “FPGA Redundancy Configurations: An Automated Design Space Exploration.” <i>Reconfigurable Architectures Workshop (RAW)</i>, 2014, doi:<a href=\"https://doi.org/10.1109/IPDPSW.2014.37\">10.1109/IPDPSW.2014.37</a>.","ieee":"J. Anwer, M. Platzner, and S. Meisner, “FPGA Redundancy Configurations: An Automated Design Space Exploration,” in <i>Reconfigurable Architectures Workshop (RAW)</i>, 2014.","chicago":"Anwer, Jahanzeb, Marco Platzner, and Sebastian Meisner. “FPGA Redundancy Configurations: An Automated Design Space Exploration.” In <i>Reconfigurable Architectures Workshop (RAW)</i>. RAW, 2014. <a href=\"https://doi.org/10.1109/IPDPSW.2014.37\">https://doi.org/10.1109/IPDPSW.2014.37</a>.","ama":"Anwer J, Platzner M, Meisner S. FPGA Redundancy Configurations: An Automated Design Space Exploration. In: <i>Reconfigurable Architectures Workshop (RAW)</i>. RAW. ; 2014. doi:<a href=\"https://doi.org/10.1109/IPDPSW.2014.37\">10.1109/IPDPSW.2014.37</a>"},"year":"2014"},{"year":"2014","citation":{"ama":"Bockhorn A. <i>Echtzeit Klassifikation von SEMG Signalen Mit Einem Low-Cost DSP Evaluation Board</i>. Paderborn University; 2014.","ieee":"A. Bockhorn, <i>Echtzeit Klassifikation von sEMG Signalen mit einem low-cost DSP Evaluation Board</i>. Paderborn University, 2014.","chicago":"Bockhorn, Arne. <i>Echtzeit Klassifikation von SEMG Signalen Mit Einem Low-Cost DSP Evaluation Board</i>. Paderborn University, 2014.","apa":"Bockhorn, A. (2014). <i>Echtzeit Klassifikation von sEMG Signalen mit einem low-cost DSP Evaluation Board</i>. Paderborn University.","mla":"Bockhorn, Arne. <i>Echtzeit Klassifikation von SEMG Signalen Mit Einem Low-Cost DSP Evaluation Board</i>. Paderborn University, 2014.","bibtex":"@book{Bockhorn_2014, title={Echtzeit Klassifikation von sEMG Signalen mit einem low-cost DSP Evaluation Board}, publisher={Paderborn University}, author={Bockhorn, Arne}, year={2014} }","short":"A. Bockhorn, Echtzeit Klassifikation von SEMG Signalen Mit Einem Low-Cost DSP Evaluation Board, Paderborn University, 2014."},"title":"Echtzeit Klassifikation von sEMG Signalen mit einem low-cost DSP Evaluation Board","publisher":"Paderborn University","date_updated":"2022-01-06T06:50:48Z","supervisor":[{"first_name":"Alexander","full_name":"Boschmann, Alexander","last_name":"Boschmann"}],"date_created":"2019-07-10T09:40:25Z","author":[{"first_name":"Arne","full_name":"Bockhorn, Arne","last_name":"Bockhorn"}],"status":"public","type":"bachelorsthesis","language":[{"iso":"eng"}],"_id":"10627","user_id":"3118","department":[{"_id":"78"}]},{"status":"public","type":"conference","publication":"Proc. MyoElectric Controls Symposium (MEC)","language":[{"iso":"eng"}],"_id":"10632","user_id":"3118","department":[{"_id":"78"}],"year":"2014","citation":{"apa":"Boschmann, A., &#38; Platzner, M. (2014). A computer vision-based approach to high density EMG pattern recognition using structural similarity. In <i>Proc. MyoElectric Controls Symposium (MEC)</i>.","bibtex":"@inproceedings{Boschmann_Platzner_2014, title={A computer vision-based approach to high density EMG pattern recognition using structural similarity}, booktitle={Proc. MyoElectric Controls Symposium (MEC)}, author={Boschmann, Alexander and Platzner, Marco}, year={2014} }","short":"A. Boschmann, M. Platzner, in: Proc. MyoElectric Controls Symposium (MEC), 2014.","mla":"Boschmann, Alexander, and Marco Platzner. “A Computer Vision-Based Approach to High Density EMG Pattern Recognition Using Structural Similarity.” <i>Proc. MyoElectric Controls Symposium (MEC)</i>, 2014.","ama":"Boschmann A, Platzner M. A computer vision-based approach to high density EMG pattern recognition using structural similarity. In: <i>Proc. MyoElectric Controls Symposium (MEC)</i>. ; 2014.","chicago":"Boschmann, Alexander, and Marco Platzner. “A Computer Vision-Based Approach to High Density EMG Pattern Recognition Using Structural Similarity.” In <i>Proc. MyoElectric Controls Symposium (MEC)</i>, 2014.","ieee":"A. Boschmann and M. Platzner, “A computer vision-based approach to high density EMG pattern recognition using structural similarity,” in <i>Proc. MyoElectric Controls Symposium (MEC)</i>, 2014."},"title":"A computer vision-based approach to high density EMG pattern recognition using structural similarity","date_updated":"2022-01-06T06:50:49Z","author":[{"full_name":"Boschmann, Alexander","last_name":"Boschmann","first_name":"Alexander"},{"first_name":"Marco","last_name":"Platzner","id":"398","full_name":"Platzner, Marco"}],"date_created":"2019-07-10T11:02:58Z"},{"status":"public","publication":"Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)","type":"conference","language":[{"iso":"eng"}],"_id":"10633","department":[{"_id":"78"}],"user_id":"3118","year":"2014","citation":{"short":"A. Boschmann, M. Platzner, in: Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC), 2014.","bibtex":"@inproceedings{Boschmann_Platzner_2014, title={Towards robust HD EMG pattern recognition: Reducing electrode displacement effect using structural similarity}, booktitle={Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)}, author={Boschmann, Alexander and Platzner, Marco}, year={2014} }","mla":"Boschmann, Alexander, and Marco Platzner. “Towards Robust HD EMG Pattern Recognition: Reducing Electrode Displacement Effect Using Structural Similarity.” <i>Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)</i>, 2014.","apa":"Boschmann, A., &#38; Platzner, M. (2014). Towards robust HD EMG pattern recognition: Reducing electrode displacement effect using structural similarity. In <i>Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)</i>.","ama":"Boschmann A, Platzner M. Towards robust HD EMG pattern recognition: Reducing electrode displacement effect using structural similarity. In: <i>Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)</i>. ; 2014.","chicago":"Boschmann, Alexander, and Marco Platzner. “Towards Robust HD EMG Pattern Recognition: Reducing Electrode Displacement Effect Using Structural Similarity.” In <i>Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)</i>, 2014.","ieee":"A. Boschmann and M. Platzner, “Towards robust HD EMG pattern recognition: Reducing electrode displacement effect using structural similarity,” in <i>Proc. IEEE Int. Conf. Eng. Med. Biolog. (EMBC)</i>, 2014."},"title":"Towards robust HD EMG pattern recognition: Reducing electrode displacement effect using structural similarity","date_updated":"2022-01-06T06:50:49Z","author":[{"last_name":"Boschmann","full_name":"Boschmann, Alexander","first_name":"Alexander"},{"first_name":"Marco","id":"398","full_name":"Platzner, Marco","last_name":"Platzner"}],"date_created":"2019-07-10T11:02:59Z"},{"citation":{"apa":"Brand, M. (2014). <i>A Generalized Loop Accelerator Implemented as a Coarse-Grained Array</i>. Paderborn University.","mla":"Brand, Marcel. <i>A Generalized Loop Accelerator Implemented as a Coarse-Grained Array</i>. Paderborn University, 2014.","bibtex":"@book{Brand_2014, title={A Generalized Loop Accelerator Implemented as a Coarse-Grained Array}, publisher={Paderborn University}, author={Brand, Marcel}, year={2014} }","short":"M. Brand, A Generalized Loop Accelerator Implemented as a Coarse-Grained Array, Paderborn University, 2014.","ieee":"M. Brand, <i>A Generalized Loop Accelerator Implemented as a Coarse-Grained Array</i>. Paderborn University, 2014.","chicago":"Brand, Marcel. <i>A Generalized Loop Accelerator Implemented as a Coarse-Grained Array</i>. Paderborn University, 2014.","ama":"Brand M. <i>A Generalized Loop Accelerator Implemented as a Coarse-Grained Array</i>. Paderborn University; 2014."},"year":"2014","title":"A Generalized Loop Accelerator Implemented as a Coarse-Grained Array","author":[{"first_name":"Marcel","full_name":"Brand, Marcel","last_name":"Brand"}],"date_created":"2019-07-10T11:03:41Z","date_updated":"2022-01-06T06:50:49Z","publisher":"Paderborn University","status":"public","type":"mastersthesis","language":[{"iso":"eng"}],"user_id":"3118","department":[{"_id":"78"}],"_id":"10640"},{"title":"Easy-to-use-on-the-fly binary program acceleration on many-cores","author":[{"first_name":"Marvin","last_name":"Damschen","full_name":"Damschen, Marvin"}],"date_created":"2019-07-10T11:08:47Z","publisher":"Paderborn University","date_updated":"2022-01-06T06:50:49Z","citation":{"bibtex":"@book{Damschen_2014, title={Easy-to-use-on-the-fly binary program acceleration on many-cores}, publisher={Paderborn University}, author={Damschen, Marvin}, year={2014} }","mla":"Damschen, Marvin. <i>Easy-to-Use-on-the-Fly Binary Program Acceleration on Many-Cores</i>. Paderborn University, 2014.","short":"M. Damschen, Easy-to-Use-on-the-Fly Binary Program Acceleration on Many-Cores, Paderborn University, 2014.","apa":"Damschen, M. (2014). <i>Easy-to-use-on-the-fly binary program acceleration on many-cores</i>. Paderborn University.","ama":"Damschen M. <i>Easy-to-Use-on-the-Fly Binary Program Acceleration on Many-Cores</i>. Paderborn University; 2014.","chicago":"Damschen, Marvin. <i>Easy-to-Use-on-the-Fly Binary Program Acceleration on Many-Cores</i>. Paderborn University, 2014.","ieee":"M. Damschen, <i>Easy-to-use-on-the-fly binary program acceleration on many-cores</i>. Paderborn University, 2014."},"year":"2014","language":[{"iso":"eng"}],"department":[{"_id":"78"}],"user_id":"3118","_id":"10645","status":"public","type":"mastersthesis"},{"type":"conference","publication":"IEEE Congress on Evolutionary Computation (CEC)","year":"2014","citation":{"ama":"Glette K, Kaufmann P. Lookup Table Partial Reconfiguration for an Evolvable Hardware Classifier System. In: <i>IEEE Congress on Evolutionary Computation (CEC)</i>. ; 2014.","chicago":"Glette, Kyrre, and Paul Kaufmann. “Lookup Table Partial Reconfiguration for an Evolvable Hardware Classifier System.” In <i>IEEE Congress on Evolutionary Computation (CEC)</i>, 2014.","ieee":"K. Glette and P. Kaufmann, “Lookup Table Partial Reconfiguration for an Evolvable Hardware Classifier System,” in <i>IEEE Congress on Evolutionary Computation (CEC)</i>, 2014.","short":"K. Glette, P. Kaufmann, in: IEEE Congress on Evolutionary Computation (CEC), 2014.","mla":"Glette, Kyrre, and Paul Kaufmann. “Lookup Table Partial Reconfiguration for an Evolvable Hardware Classifier System.” <i>IEEE Congress on Evolutionary Computation (CEC)</i>, 2014.","bibtex":"@inproceedings{Glette_Kaufmann_2014, title={Lookup Table Partial Reconfiguration for an Evolvable Hardware Classifier System}, booktitle={IEEE Congress on Evolutionary Computation (CEC)}, author={Glette, Kyrre and Kaufmann, Paul}, year={2014} }","apa":"Glette, K., &#38; Kaufmann, P. (2014). Lookup Table Partial Reconfiguration for an Evolvable Hardware Classifier System. In <i>IEEE Congress on Evolutionary Computation (CEC)</i>."},"status":"public","date_updated":"2022-01-06T06:50:49Z","_id":"10654","date_created":"2019-07-10T11:13:14Z","author":[{"first_name":"Kyrre","full_name":"Glette, Kyrre","last_name":"Glette"},{"first_name":"Paul","last_name":"Kaufmann","full_name":"Kaufmann, Paul"}],"user_id":"3118","department":[{"_id":"78"}],"title":"Lookup Table Partial Reconfiguration for an Evolvable Hardware Classifier System"},{"year":"2014","citation":{"ama":"Hagedorn C. <i>Entwicklung Einer Codegrößenoptimierten Softwarebibliothek Für 8-Bit Mikrocontroller in Netzunabhängigen Notleuchten</i>. Paderborn University; 2014.","ieee":"C. Hagedorn, <i>Entwicklung einer codegrößenoptimierten Softwarebibliothek für 8-Bit Mikrocontroller in netzunabhängigen Notleuchten</i>. Paderborn University, 2014.","chicago":"Hagedorn, Christoph. <i>Entwicklung Einer Codegrößenoptimierten Softwarebibliothek Für 8-Bit Mikrocontroller in Netzunabhängigen Notleuchten</i>. Paderborn University, 2014.","apa":"Hagedorn, C. (2014). <i>Entwicklung einer codegrößenoptimierten Softwarebibliothek für 8-Bit Mikrocontroller in netzunabhängigen Notleuchten</i>. Paderborn University.","mla":"Hagedorn, Christoph. <i>Entwicklung Einer Codegrößenoptimierten Softwarebibliothek Für 8-Bit Mikrocontroller in Netzunabhängigen Notleuchten</i>. Paderborn University, 2014.","bibtex":"@book{Hagedorn_2014, title={Entwicklung einer codegrößenoptimierten Softwarebibliothek für 8-Bit Mikrocontroller in netzunabhängigen Notleuchten}, publisher={Paderborn University}, author={Hagedorn, Christoph}, year={2014} }","short":"C. Hagedorn, Entwicklung Einer Codegrößenoptimierten Softwarebibliothek Für 8-Bit Mikrocontroller in Netzunabhängigen Notleuchten, Paderborn University, 2014."},"title":"Entwicklung einer codegrößenoptimierten Softwarebibliothek für 8-Bit Mikrocontroller in netzunabhängigen Notleuchten","publisher":"Paderborn University","date_updated":"2022-01-06T06:50:49Z","author":[{"full_name":"Hagedorn, Christoph","last_name":"Hagedorn","first_name":"Christoph"}],"date_created":"2019-07-10T11:15:09Z","supervisor":[{"last_name":"Meisner","full_name":"Meisner, Sebastian","first_name":"Sebastian"}],"status":"public","type":"bachelorsthesis","language":[{"iso":"eng"}],"_id":"10665","user_id":"3118","department":[{"_id":"78"}]},{"publication":"24th Intl. Conf. on Field Programmable Logic and Applications (FPL)","type":"conference","status":"public","department":[{"_id":"78"}],"user_id":"3118","_id":"10674","project":[{"grant_number":"257906","_id":"31","name":"Engineering Proprioception in Computing Systems"}],"language":[{"iso":"eng"}],"keyword":["Linux","hardware-software codesign","multiprocessing systems","parallel processing","LEON3 multicore platform","Linux kernel","PMU","hardware counters","hardware-software infrastructure","high performance embedded computing","perf_event","performance monitoring unit","Computer architecture","Hardware","Monitoring","Phasor measurement units","Radiation detectors","Registers","Software"],"page":"1-4","citation":{"ieee":"N. Ho, P. Kaufmann, and M. Platzner, “A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms,” in <i>24th Intl. Conf. on Field Programmable Logic and Applications (FPL)</i>, 2014, pp. 1–4.","chicago":"Ho, Nam, Paul Kaufmann, and Marco Platzner. “A Hardware/Software Infrastructure for Performance Monitoring on LEON3 Multicore Platforms.” In <i>24th Intl. Conf. on Field Programmable Logic and Applications (FPL)</i>, 1–4, 2014. <a href=\"https://doi.org/10.1109/FPL.2014.6927437\">https://doi.org/10.1109/FPL.2014.6927437</a>.","ama":"Ho N, Kaufmann P, Platzner M. A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms. In: <i>24th Intl. Conf. on Field Programmable Logic and Applications (FPL)</i>. ; 2014:1-4. doi:<a href=\"https://doi.org/10.1109/FPL.2014.6927437\">10.1109/FPL.2014.6927437</a>","apa":"Ho, N., Kaufmann, P., &#38; Platzner, M. (2014). A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms. In <i>24th Intl. Conf. on Field Programmable Logic and Applications (FPL)</i> (pp. 1–4). <a href=\"https://doi.org/10.1109/FPL.2014.6927437\">https://doi.org/10.1109/FPL.2014.6927437</a>","short":"N. Ho, P. Kaufmann, M. Platzner, in: 24th Intl. Conf. on Field Programmable Logic and Applications (FPL), 2014, pp. 1–4.","mla":"Ho, Nam, et al. “A Hardware/Software Infrastructure for Performance Monitoring on LEON3 Multicore Platforms.” <i>24th Intl. Conf. on Field Programmable Logic and Applications (FPL)</i>, 2014, pp. 1–4, doi:<a href=\"https://doi.org/10.1109/FPL.2014.6927437\">10.1109/FPL.2014.6927437</a>.","bibtex":"@inproceedings{Ho_Kaufmann_Platzner_2014, title={A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms}, DOI={<a href=\"https://doi.org/10.1109/FPL.2014.6927437\">10.1109/FPL.2014.6927437</a>}, booktitle={24th Intl. Conf. on Field Programmable Logic and Applications (FPL)}, author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2014}, pages={1–4} }"},"year":"2014","date_created":"2019-07-10T11:18:01Z","author":[{"full_name":"Ho, Nam","last_name":"Ho","first_name":"Nam"},{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"},{"first_name":"Marco","full_name":"Platzner, Marco","id":"398","last_name":"Platzner"}],"date_updated":"2022-01-06T06:50:49Z","doi":"10.1109/FPL.2014.6927437","title":"A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms"},{"page":"31-37","citation":{"chicago":"Ho, Nam, Paul Kaufmann, and Marco Platzner. “Towards Self-Adaptive Caches: A Run-Time Reconfigurable Multi-Core Infrastructure.” In <i>2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)</i>, 31–37, 2014. <a href=\"https://doi.org/10.1109/ICES.2014.7008719\">https://doi.org/10.1109/ICES.2014.7008719</a>.","ieee":"N. Ho, P. Kaufmann, and M. Platzner, “Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure,” in <i>2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)</i>, 2014, pp. 31–37.","ama":"Ho N, Kaufmann P, Platzner M. Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure. In: <i>2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)</i>. ; 2014:31-37. doi:<a href=\"https://doi.org/10.1109/ICES.2014.7008719\">10.1109/ICES.2014.7008719</a>","apa":"Ho, N., Kaufmann, P., &#38; Platzner, M. (2014). Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure. In <i>2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)</i> (pp. 31–37). <a href=\"https://doi.org/10.1109/ICES.2014.7008719\">https://doi.org/10.1109/ICES.2014.7008719</a>","mla":"Ho, Nam, et al. “Towards Self-Adaptive Caches: A Run-Time Reconfigurable Multi-Core Infrastructure.” <i>2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)</i>, 2014, pp. 31–37, doi:<a href=\"https://doi.org/10.1109/ICES.2014.7008719\">10.1109/ICES.2014.7008719</a>.","bibtex":"@inproceedings{Ho_Kaufmann_Platzner_2014, title={Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure}, DOI={<a href=\"https://doi.org/10.1109/ICES.2014.7008719\">10.1109/ICES.2014.7008719</a>}, booktitle={2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)}, author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2014}, pages={31–37} }","short":"N. Ho, P. Kaufmann, M. Platzner, in: 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES), 2014, pp. 31–37."},"year":"2014","author":[{"first_name":"Nam","full_name":"Ho, Nam","last_name":"Ho"},{"first_name":"Paul","last_name":"Kaufmann","full_name":"Kaufmann, Paul"},{"first_name":"Marco","full_name":"Platzner, Marco","id":"398","last_name":"Platzner"}],"date_created":"2019-07-10T11:23:00Z","date_updated":"2022-01-06T06:50:49Z","doi":"10.1109/ICES.2014.7008719","title":"Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure","publication":"2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)","type":"conference","status":"public","department":[{"_id":"78"}],"user_id":"3118","_id":"10677","language":[{"iso":"eng"}],"keyword":["Linux","cache storage","embedded systems","granular computing","multiprocessing systems","reconfigurable architectures","Leon3 SPARe processor","custom logic events","evolvable-self-adaptable processor cache","fine granular profiling","integer unit events","measurement infrastructure","microarchitectural events","multicore embedded system","perf_event standard Linux performance measurement interface","processor properties","run-time reconfigurable memory-to-cache address mapping engine","run-time reconfigurable multicore infrastructure","split-level caching","Field programmable gate arrays","Frequency locked loops","Irrigation","Phasor measurement units","Registers","Weaving"]},{"title":"EMG-basierte simultane und proportionale Online-Steuerung einer virtuellen Prothese","publisher":"Paderborn University","date_updated":"2022-01-06T06:50:49Z","author":[{"first_name":"Fabian","full_name":"König, Fabian","last_name":"König"}],"date_created":"2019-07-10T11:23:20Z","supervisor":[{"last_name":"Boschmann","full_name":"Boschmann, Alexander","first_name":"Alexander"}],"year":"2014","citation":{"apa":"König, F. (2014). <i>EMG-basierte simultane und proportionale Online-Steuerung einer virtuellen Prothese</i>. Paderborn University.","mla":"König, Fabian. <i>EMG-Basierte Simultane Und Proportionale Online-Steuerung Einer Virtuellen Prothese</i>. Paderborn University, 2014.","bibtex":"@book{König_2014, title={EMG-basierte simultane und proportionale Online-Steuerung einer virtuellen Prothese}, publisher={Paderborn University}, author={König, Fabian}, year={2014} }","short":"F. König, EMG-Basierte Simultane Und Proportionale Online-Steuerung Einer Virtuellen Prothese, Paderborn University, 2014.","ieee":"F. König, <i>EMG-basierte simultane und proportionale Online-Steuerung einer virtuellen Prothese</i>. Paderborn University, 2014.","chicago":"König, Fabian. <i>EMG-Basierte Simultane Und Proportionale Online-Steuerung Einer Virtuellen Prothese</i>. Paderborn University, 2014.","ama":"König F. <i>EMG-Basierte Simultane Und Proportionale Online-Steuerung Einer Virtuellen Prothese</i>. Paderborn University; 2014."},"language":[{"iso":"eng"}],"_id":"10679","user_id":"3118","department":[{"_id":"78"}],"status":"public","type":"bachelorsthesis"},{"citation":{"apa":"Koch, B. (2014). <i>Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA</i>. Paderborn University.","short":"B. Koch, Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA, Paderborn University, 2014.","bibtex":"@book{Koch_2014, title={Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA}, publisher={Paderborn University}, author={Koch, Benjamin}, year={2014} }","mla":"Koch, Benjamin. <i>Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA</i>. Paderborn University, 2014.","ama":"Koch B. <i>Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA</i>. Paderborn University; 2014.","ieee":"B. Koch, <i>Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA</i>. Paderborn University, 2014.","chicago":"Koch, Benjamin. <i>Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA</i>. Paderborn University, 2014."},"year":"2014","author":[{"first_name":"Benjamin","full_name":"Koch, Benjamin","last_name":"Koch"}],"date_created":"2019-07-10T11:38:27Z","supervisor":[{"first_name":"Marco","id":"398","full_name":"Platzner, Marco","last_name":"Platzner"}],"date_updated":"2022-01-06T06:50:50Z","publisher":"Paderborn University","title":"Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA","type":"mastersthesis","status":"public","user_id":"3118","department":[{"_id":"78"}],"_id":"10701","language":[{"iso":"eng"}]},{"user_id":"3118","department":[{"_id":"78"}],"_id":"10715","language":[{"iso":"eng"}],"type":"mastersthesis","status":"public","author":[{"first_name":"Robert","full_name":"Mittendorf, Robert","last_name":"Mittendorf"}],"date_created":"2019-07-10T11:48:26Z","publisher":"Paderborn University","date_updated":"2022-01-06T06:50:50Z","title":"Advanced AES-key recovery from decayed RAM using multi-threading and FPGAs","citation":{"short":"R. Mittendorf, Advanced AES-Key Recovery from Decayed RAM Using Multi-Threading and FPGAs, Paderborn University, 2014.","mla":"Mittendorf, Robert. <i>Advanced AES-Key Recovery from Decayed RAM Using Multi-Threading and FPGAs</i>. Paderborn University, 2014.","bibtex":"@book{Mittendorf_2014, title={Advanced AES-key recovery from decayed RAM using multi-threading and FPGAs}, publisher={Paderborn University}, author={Mittendorf, Robert}, year={2014} }","apa":"Mittendorf, R. (2014). <i>Advanced AES-key recovery from decayed RAM using multi-threading and FPGAs</i>. Paderborn University.","ama":"Mittendorf R. <i>Advanced AES-Key Recovery from Decayed RAM Using Multi-Threading and FPGAs</i>. Paderborn University; 2014.","ieee":"R. Mittendorf, <i>Advanced AES-key recovery from decayed RAM using multi-threading and FPGAs</i>. Paderborn University, 2014.","chicago":"Mittendorf, Robert. <i>Advanced AES-Key Recovery from Decayed RAM Using Multi-Threading and FPGAs</i>. Paderborn University, 2014."},"year":"2014"},{"date_updated":"2022-01-06T06:50:50Z","publisher":"Paderborn University","author":[{"first_name":"Christoph","full_name":"Rüthing, Christoph","last_name":"Rüthing"}],"date_created":"2019-07-10T11:58:05Z","title":"The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores","year":"2014","citation":{"apa":"Rüthing, C. (2014). <i>The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores</i>. Paderborn University.","mla":"Rüthing, Christoph. <i>The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores</i>. Paderborn University, 2014.","short":"C. Rüthing, The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores, Paderborn University, 2014.","bibtex":"@book{Rüthing_2014, title={The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores}, publisher={Paderborn University}, author={Rüthing, Christoph}, year={2014} }","chicago":"Rüthing, Christoph. <i>The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores</i>. Paderborn University, 2014.","ieee":"C. Rüthing, <i>The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores</i>. Paderborn University, 2014.","ama":"Rüthing C. <i>The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores</i>. Paderborn University; 2014."},"_id":"10732","user_id":"3118","department":[{"_id":"78"}],"language":[{"iso":"eng"}],"type":"bachelorsthesis","status":"public"},{"page":"133","citation":{"ieee":"L. Schäfers, <i>Parallel Monte-Carlo Tree Search for HPC Systems and its Application to Computer Go</i>. Berlin: Logos Verlag Berlin GmbH, 2014.","chicago":"Schäfers, Lars. <i>Parallel Monte-Carlo Tree Search for HPC Systems and Its Application to Computer Go</i>. Berlin: Logos Verlag Berlin GmbH, 2014.","ama":"Schäfers L. <i>Parallel Monte-Carlo Tree Search for HPC Systems and Its Application to Computer Go</i>. Berlin: Logos Verlag Berlin GmbH; 2014.","apa":"Schäfers, L. (2014). <i>Parallel Monte-Carlo Tree Search for HPC Systems and its Application to Computer Go</i>. Berlin: Logos Verlag Berlin GmbH.","mla":"Schäfers, Lars. <i>Parallel Monte-Carlo Tree Search for HPC Systems and Its Application to Computer Go</i>. Logos Verlag Berlin GmbH, 2014.","short":"L. Schäfers, Parallel Monte-Carlo Tree Search for HPC Systems and Its Application to Computer Go, Logos Verlag Berlin GmbH, Berlin, 2014.","bibtex":"@book{Schäfers_2014, place={Berlin}, title={Parallel Monte-Carlo Tree Search for HPC Systems and its Application to Computer Go}, publisher={Logos Verlag Berlin GmbH}, author={Schäfers, Lars}, year={2014} }"},"place":"Berlin","year":"2014","publication_identifier":{"isbn":["978-3-8325-3748-7"]},"publication_status":"published","title":"Parallel Monte-Carlo Tree Search for HPC Systems and its Application to Computer Go","author":[{"first_name":"Lars","full_name":"Schäfers, Lars","last_name":"Schäfers"}],"supervisor":[{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}],"date_created":"2019-07-10T11:58:06Z","date_updated":"2022-01-06T06:50:50Z","publisher":"Logos Verlag Berlin GmbH","status":"public","abstract":[{"text":"Monte-Carlo Tree Search (MCTS) is a class of simulation-based search algorithms. It brought about great success in the past few years regarding the evaluation of deterministic two-player games such as the Asian board game Go.\r\n\r\nIn this thesis, we present a parallelization of the most popular MCTS variant for large HPC compute clusters that efficiently shares a single game tree representation in a distributed memory environment and scales up to 128 compute nodes and 2048 cores. It is hereby one of the most powerful MCTS parallelizations to date.\r\n\r\nIn order to measure the impact of our parallelization on the search quality and remain comparable to the most advanced MCTS implementations to date, we implemented it in a state-of-the-art Go engine Gomorra, making it competitive with the strongest Go programs in the world.\r\n\r\nWe further present an empirical comparison of different Bayesian ranking systems when being used for predicting expert moves for the game of Go and introduce a novel technique for automated detection and analysis of evaluation uncertainties that show up during MCTS searches.","lang":"eng"}],"type":"dissertation","language":[{"iso":"eng"}],"department":[{"_id":"78"}],"user_id":"3118","_id":"10733"},{"_id":"10738","date_updated":"2022-01-06T06:50:50Z","department":[{"_id":"78"}],"user_id":"3118","date_created":"2019-07-10T11:59:36Z","author":[{"full_name":"Shen, Cong","last_name":"Shen","first_name":"Cong"},{"full_name":"Kaufmann, Paul","last_name":"Kaufmann","first_name":"Paul"},{"first_name":"Martin","last_name":"Braun","full_name":"Braun, Martin"}],"title":"Optimizing the Generator Start-up Sequence After a Power System Blackout","publication":"IEEE Power and Energy Society General Meeting (IEEE GM)","type":"conference","year":"2014","status":"public","citation":{"ieee":"C. Shen, P. Kaufmann, and M. Braun, “Optimizing the Generator Start-up Sequence After a Power System Blackout,” in <i>IEEE Power and Energy Society General Meeting (IEEE GM)</i>, 2014.","chicago":"Shen, Cong, Paul Kaufmann, and Martin Braun. “Optimizing the Generator Start-up Sequence After a Power System Blackout.” In <i>IEEE Power and Energy Society General Meeting (IEEE GM)</i>, 2014.","ama":"Shen C, Kaufmann P, Braun M. Optimizing the Generator Start-up Sequence After a Power System Blackout. In: <i>IEEE Power and Energy Society General Meeting (IEEE GM)</i>. ; 2014.","apa":"Shen, C., Kaufmann, P., &#38; Braun, M. (2014). Optimizing the Generator Start-up Sequence After a Power System Blackout. In <i>IEEE Power and Energy Society General Meeting (IEEE GM)</i>.","mla":"Shen, Cong, et al. “Optimizing the Generator Start-up Sequence After a Power System Blackout.” <i>IEEE Power and Energy Society General Meeting (IEEE GM)</i>, 2014.","bibtex":"@inproceedings{Shen_Kaufmann_Braun_2014, title={Optimizing the Generator Start-up Sequence After a Power System Blackout}, booktitle={IEEE Power and Energy Society General Meeting (IEEE GM)}, author={Shen, Cong and Kaufmann, Paul and Braun, Martin}, year={2014} }","short":"C. Shen, P. Kaufmann, M. Braun, in: IEEE Power and Energy Society General Meeting (IEEE GM), 2014."}},{"status":"public","type":"conference","publication":"Power Systems Computation Conference (PSCC)","user_id":"3118","department":[{"_id":"78"}],"_id":"10739","citation":{"chicago":"Shen, Cong, Paul Kaufmann, and Martin Braun. “A New Distribution Network Reconfiguration and Restoration Path Selection Algorithm.” In <i>Power Systems Computation Conference (PSCC)</i>. IEEE, 2014.","ieee":"C. Shen, P. Kaufmann, and M. Braun, “A New Distribution Network Reconfiguration and Restoration Path Selection Algorithm,” in <i>Power Systems Computation Conference (PSCC)</i>, 2014.","ama":"Shen C, Kaufmann P, Braun M. A New Distribution Network Reconfiguration and Restoration Path Selection Algorithm. In: <i>Power Systems Computation Conference (PSCC)</i>. IEEE; 2014.","apa":"Shen, C., Kaufmann, P., &#38; Braun, M. (2014). A New Distribution Network Reconfiguration and Restoration Path Selection Algorithm. In <i>Power Systems Computation Conference (PSCC)</i>. IEEE.","bibtex":"@inproceedings{Shen_Kaufmann_Braun_2014, title={A New Distribution Network Reconfiguration and Restoration Path Selection Algorithm}, booktitle={Power Systems Computation Conference (PSCC)}, publisher={IEEE}, author={Shen, Cong and Kaufmann, Paul and Braun, Martin}, year={2014} }","mla":"Shen, Cong, et al. “A New Distribution Network Reconfiguration and Restoration Path Selection Algorithm.” <i>Power Systems Computation Conference (PSCC)</i>, IEEE, 2014.","short":"C. Shen, P. Kaufmann, M. Braun, in: Power Systems Computation Conference (PSCC), IEEE, 2014."},"year":"2014","title":"A New Distribution Network Reconfiguration and Restoration Path Selection Algorithm","date_created":"2019-07-10T11:59:37Z","author":[{"full_name":"Shen, Cong","last_name":"Shen","first_name":"Cong"},{"first_name":"Paul","full_name":"Kaufmann, Paul","last_name":"Kaufmann"},{"first_name":"Martin","last_name":"Braun","full_name":"Braun, Martin"}],"publisher":"IEEE","date_updated":"2022-01-06T06:50:50Z"}]