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Exploiting HIV-1 protease and reverse transcriptase cross-resistance information for improved drug resistance prediction by means of multi-label classification. <i>BioData Mining</i>, <i>9</i>(10).","bibtex":"@article{Riemenschneider_Senge_Neumann_Hüllermeier_Heider_2016, title={Exploiting HIV-1 protease and reverse transcriptase cross-resistance information for improved drug resistance prediction by means of multi-label classification}, volume={9}, number={10}, journal={BioData Mining}, author={Riemenschneider, M. and Senge, Robin and Neumann, U. and Hüllermeier, Eyke and Heider, D.}, year={2016} }","chicago":"Riemenschneider, M., Robin Senge, U. Neumann, Eyke Hüllermeier, and D. Heider. “Exploiting HIV-1 Protease and Reverse Transcriptase Cross-Resistance Information for Improved Drug Resistance Prediction by Means of Multi-Label Classification.” <i>BioData Mining</i> 9, no. 10 (2016).","short":"M. Riemenschneider, R. Senge, U. Neumann, E. Hüllermeier, D. Heider, BioData Mining 9 (2016).","ama":"Riemenschneider M, Senge R, Neumann U, Hüllermeier E, Heider D. Exploiting HIV-1 protease and reverse transcriptase cross-resistance information for improved drug resistance prediction by means of multi-label classification. <i>BioData Mining</i>. 2016;9(10)."}},{"author":[{"id":"3952","first_name":"Thomas","last_name":"John","full_name":"John, Thomas"}],"title":"Business Model Modeling Languages as Tools for Innovation:  Theory and Empirical Evidence","year":"2016","status":"public","date_updated":"2022-01-06T06:50:35Z","_id":"10292","language":[{"iso":"eng"}],"user_id":"477","doi":"10.17619/UNIPB/1-259 ","citation":{"ama":"John T. <i>Business Model Modeling Languages as Tools for Innovation:  Theory and Empirical Evidence</i>. Universität Paderborn; 2016. doi:<a href=\"https://doi.org/10.17619/UNIPB/1-259 \">10.17619/UNIPB/1-259 </a>","bibtex":"@book{John_2016, place={Universität Paderborn}, title={Business Model Modeling Languages as Tools for Innovation:  Theory and Empirical Evidence}, DOI={<a href=\"https://doi.org/10.17619/UNIPB/1-259 \">10.17619/UNIPB/1-259 </a>}, author={John, Thomas}, year={2016} }","mla":"John, Thomas. <i>Business Model Modeling Languages as Tools for Innovation:  Theory and Empirical Evidence</i>. 2016, doi:<a href=\"https://doi.org/10.17619/UNIPB/1-259 \">10.17619/UNIPB/1-259 </a>.","short":"T. John, Business Model Modeling Languages as Tools for Innovation:  Theory and Empirical Evidence, Universität Paderborn, 2016.","chicago":"John, Thomas. <i>Business Model Modeling Languages as Tools for Innovation:  Theory and Empirical Evidence</i>. Universität Paderborn, 2016. <a href=\"https://doi.org/10.17619/UNIPB/1-259 \">https://doi.org/10.17619/UNIPB/1-259 </a>.","apa":"John, T. (2016). <i>Business Model Modeling Languages as Tools for Innovation:  Theory and Empirical Evidence</i>. Universität Paderborn. <a href=\"https://doi.org/10.17619/UNIPB/1-259 \">https://doi.org/10.17619/UNIPB/1-259 </a>","ieee":"T. John, <i>Business Model Modeling Languages as Tools for Innovation:  Theory and Empirical Evidence</i>. Universität Paderborn, 2016."},"supervisor":[{"last_name":"Kundisch","first_name":"Dennis","full_name":"Kundisch, Dennis","id":"21117"}],"project":[{"name":"SFB 901","_id":"1"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"17","name":"SFB 901 - Subproject C5"}],"date_created":"2019-06-25T09:50:01Z","place":"Universität Paderborn","department":[{"_id":"276"}],"type":"dissertation"},{"date_created":"2017-12-11T14:21:15Z","type":"conference","citation":{"ama":"Abujoda A, Razzaghi Kouchaksaraei H, Papadimitriou P. SDN-Based Source Routing for Scalable Service Chaining in Datacenters. In: Springer International Publishing; 2016:66-77.","bibtex":"@inproceedings{Abujoda_Razzaghi Kouchaksaraei_Papadimitriou_2016, title={SDN-Based Source Routing for Scalable Service Chaining in Datacenters}, publisher={Springer International Publishing}, author={Abujoda, Ahmed and Razzaghi Kouchaksaraei, Hadi and Papadimitriou, Panagiotis}, year={2016}, pages={66–77} }","mla":"Abujoda, Ahmed, et al. <i>SDN-Based Source Routing for Scalable Service Chaining in Datacenters</i>. Springer International Publishing, 2016, pp. 66–77.","short":"A. Abujoda, H. Razzaghi Kouchaksaraei, P. Papadimitriou, in: Springer International Publishing, 2016, pp. 66–77.","chicago":"Abujoda, Ahmed, Hadi Razzaghi Kouchaksaraei, and Panagiotis Papadimitriou. “SDN-Based Source Routing for Scalable Service Chaining in Datacenters,” 66–77. Springer International Publishing, 2016.","apa":"Abujoda, A., Razzaghi Kouchaksaraei, H., &#38; Papadimitriou, P. (2016). SDN-Based Source Routing for Scalable Service Chaining in Datacenters (pp. 66–77). Presented at the 14th IFIP WG 6.2 International Conference, WWIC 2016, Thessaloniki, Greece: Springer International Publishing.","ieee":"A. Abujoda, H. Razzaghi Kouchaksaraei, and P. Papadimitriou, “SDN-Based Source Routing for Scalable Service Chaining in Datacenters,” presented at the 14th IFIP WG 6.2 International Conference, WWIC 2016, Thessaloniki, Greece, 2016, pp. 66–77."},"extern":"1","page":"66-77","language":[{"iso":"eng"}],"_id":"1039","publisher":"Springer International Publishing","user_id":"60845","title":"SDN-Based Source Routing for Scalable Service Chaining in Datacenters","status":"public","year":"2016","author":[{"full_name":"Abujoda, Ahmed","last_name":"Abujoda","first_name":"Ahmed"},{"id":"60845","last_name":"Razzaghi Kouchaksaraei","first_name":"Hadi","full_name":"Razzaghi Kouchaksaraei, Hadi"},{"first_name":"Panagiotis","last_name":"Papadimitriou","full_name":"Papadimitriou, Panagiotis"}],"conference":{"end_date":"2016-27-2016","location":"Thessaloniki, Greece","start_date":"2016-05-25","name":"14th IFIP WG 6.2 International Conference, WWIC 2016"},"publication_status":"published","date_updated":"2022-01-06T06:50:38Z"},{"date_created":"2017-10-17T12:41:17Z","file":[{"creator":"abursig","date_created":"2018-11-14T12:46:37Z","date_updated":"2018-11-14T12:46:37Z","relation":"main_file","file_size":657458,"access_level":"closed","file_name":"MKWI2016_BMDT.PDF","content_type":"application/pdf","success":1,"file_id":"5608"}],"department":[{"_id":"276"}],"type":"conference_abstract","citation":{"chicago":"Strotmeyer, Sebastian, Thomas John, and Dennis Kundisch. “Vergleichende Betrachtung von Software-Werkzeugen Zur Geschäftsmodellentwicklung.” In <i>Multikonferenz Wirtschaftsinformatik (MKWI)</i>, 2016.","short":"S. Strotmeyer, T. John, D. Kundisch, in: Multikonferenz Wirtschaftsinformatik (MKWI), 2016.","ieee":"S. Strotmeyer, T. John, and D. Kundisch, “Vergleichende Betrachtung von Software-Werkzeugen zur Geschäftsmodellentwicklung,” in <i>Multikonferenz Wirtschaftsinformatik (MKWI)</i>, Ilmenau, Germany, 2016.","apa":"Strotmeyer, S., John, T., &#38; Kundisch, D. (2016). Vergleichende Betrachtung von Software-Werkzeugen zur Geschäftsmodellentwicklung. In <i>Multikonferenz Wirtschaftsinformatik (MKWI)</i>. Ilmenau, Germany.","bibtex":"@inproceedings{Strotmeyer_John_Kundisch_2016, title={Vergleichende Betrachtung von Software-Werkzeugen zur Geschäftsmodellentwicklung}, booktitle={Multikonferenz Wirtschaftsinformatik (MKWI)}, author={Strotmeyer, Sebastian and John, Thomas and Kundisch, Dennis}, year={2016} }","ama":"Strotmeyer S, John T, Kundisch D. Vergleichende Betrachtung von Software-Werkzeugen zur Geschäftsmodellentwicklung. In: <i>Multikonferenz Wirtschaftsinformatik (MKWI)</i>. ; 2016.","mla":"Strotmeyer, Sebastian, et al. “Vergleichende Betrachtung von Software-Werkzeugen Zur Geschäftsmodellentwicklung.” <i>Multikonferenz Wirtschaftsinformatik (MKWI)</i>, 2016."},"file_date_updated":"2018-11-14T12:46:37Z","publication":"Multikonferenz Wirtschaftsinformatik (MKWI)","project":[{"name":"SFB 901","_id":"1"},{"name":"SFB 901 - Subprojekt C5","_id":"17"},{"name":"SFB 901 - Project Area C","_id":"4"}],"language":[{"iso":"eng"}],"_id":"135","user_id":"477","ddc":["040"],"author":[{"full_name":"Strotmeyer, Sebastian","last_name":"Strotmeyer","first_name":"Sebastian"},{"id":"3952","first_name":"Thomas","last_name":"John","full_name":"John, Thomas"},{"id":"21117","last_name":"Kundisch","first_name":"Dennis","full_name":"Kundisch, Dennis"}],"conference":{"name":"Multikonferenz Wirtschaftsinformatik (MKWI)","location":"Ilmenau, Germany"},"year":"2016","title":"Vergleichende Betrachtung von Software-Werkzeugen zur Geschäftsmodellentwicklung","status":"public","has_accepted_license":"1","date_updated":"2022-01-06T06:51:37Z"},{"date_updated":"2022-01-06T06:51:40Z","status":"public","title":"Vergleich von Disambiguierungsansätzen bei Anforderungsbeschreibungen","year":"2016","author":[{"first_name":"Daniel","last_name":"Vollmers","full_name":"Vollmers, Daniel"}],"user_id":"477","_id":"136","publisher":"Universität Paderborn","language":[{"iso":"ger"}],"project":[{"name":"SFB 901","_id":"1"},{"_id":"9","name":"SFB 901 - Subprojekt B1"},{"name":"SFB 901 - Project Area B","_id":"3"}],"citation":{"short":"D. Vollmers, Vergleich von Disambiguierungsansätzen bei Anforderungsbeschreibungen, Universität Paderborn, 2016.","chicago":"Vollmers, Daniel. <i>Vergleich von Disambiguierungsansätzen bei Anforderungsbeschreibungen</i>. Universität Paderborn, 2016.","apa":"Vollmers, D. (2016). <i>Vergleich von Disambiguierungsansätzen bei Anforderungsbeschreibungen</i>. Universität Paderborn.","ieee":"D. Vollmers, <i>Vergleich von Disambiguierungsansätzen bei Anforderungsbeschreibungen</i>. Universität Paderborn, 2016.","ama":"Vollmers D. <i>Vergleich von Disambiguierungsansätzen bei Anforderungsbeschreibungen</i>. Universität Paderborn; 2016.","bibtex":"@book{Vollmers_2016, title={Vergleich von Disambiguierungsansätzen bei Anforderungsbeschreibungen}, publisher={Universität Paderborn}, author={Vollmers, Daniel}, year={2016} }","mla":"Vollmers, Daniel. <i>Vergleich von Disambiguierungsansätzen bei Anforderungsbeschreibungen</i>. Universität Paderborn, 2016."},"type":"bachelorsthesis","date_created":"2017-10-17T12:41:18Z"},{"publication":"Sustainable Computing: Informatics and Systems","citation":{"mla":"Herlich, Matthias, et al. “Delayed (de-)Activation in Servers with a Sleep Mode.” <i>Sustainable Computing: Informatics and Systems</i>, vol. 10, Elsevier BV, 2016, pp. 48–55, doi:<a href=\"https://doi.org/10.1016/j.suscom.2016.04.002\">10.1016/j.suscom.2016.04.002</a>.","ama":"Herlich M, Bredenbals N, Karl H. Delayed (de-)activation in servers with a sleep mode. <i>Sustainable Computing: Informatics and Systems</i>. 2016;10:48-55. doi:<a href=\"https://doi.org/10.1016/j.suscom.2016.04.002\">10.1016/j.suscom.2016.04.002</a>","bibtex":"@article{Herlich_Bredenbals_Karl_2016, title={Delayed (de-)activation in servers with a sleep mode}, volume={10}, DOI={<a href=\"https://doi.org/10.1016/j.suscom.2016.04.002\">10.1016/j.suscom.2016.04.002</a>}, journal={Sustainable Computing: Informatics and Systems}, publisher={Elsevier BV}, author={Herlich, Matthias and Bredenbals, Nico and Karl, Holger}, year={2016}, pages={48–55} }","apa":"Herlich, M., Bredenbals, N., &#38; Karl, H. (2016). Delayed (de-)activation in servers with a sleep mode. <i>Sustainable Computing: Informatics and Systems</i>, <i>10</i>, 48–55. <a href=\"https://doi.org/10.1016/j.suscom.2016.04.002\">https://doi.org/10.1016/j.suscom.2016.04.002</a>","ieee":"M. Herlich, N. Bredenbals, and H. Karl, “Delayed (de-)activation in servers with a sleep mode,” <i>Sustainable Computing: Informatics and Systems</i>, vol. 10, pp. 48–55, 2016.","chicago":"Herlich, Matthias, Nico Bredenbals, and Holger Karl. “Delayed (de-)Activation in Servers with a Sleep Mode.” <i>Sustainable Computing: Informatics and Systems</i> 10 (2016): 48–55. <a href=\"https://doi.org/10.1016/j.suscom.2016.04.002\">https://doi.org/10.1016/j.suscom.2016.04.002</a>.","short":"M. Herlich, N. Bredenbals, H. Karl, Sustainable Computing: Informatics and Systems 10 (2016) 48–55."},"type":"journal_article","department":[{"_id":"75"}],"date_created":"2018-03-19T13:29:17Z","publication_status":"published","date_updated":"2022-01-06T06:51:43Z","intvolume":"        10","year":"2016","title":"Delayed (de-)activation in servers with a sleep mode","status":"public","author":[{"last_name":"Herlich","first_name":"Matthias","full_name":"Herlich, Matthias"},{"last_name":"Bredenbals","first_name":"Nico","full_name":"Bredenbals, Nico"},{"id":"126","full_name":"Karl, Holger","first_name":"Holger","last_name":"Karl"}],"publication_identifier":{"issn":["2210-5379"]},"user_id":"15572","doi":"10.1016/j.suscom.2016.04.002","volume":10,"page":"48-55","_id":"1373","publisher":"Elsevier BV"},{"department":[{"_id":"58"}],"type":"conference","date_created":"2021-09-13T09:44:30Z","place":"Tallin, Estonia","abstract":[{"lang":"eng","text":"Electronic systems, like they are embedded in road vehicles, have to be compliant to functional safety standards like ISO 26262 [1], which limit the impacts of malfunctions for safety critical systems. ISO 26262, for instance, defines different safety levels for road vehicles, which require different means and measures for a safety compliant system and its development process like risk analysis and fault effect simulation. For fault effect simulation it is important to investigate the impact of physical and hardware related effects to the correct function of a system. This article first studies code and model mutations for fault injection in the context of fault effect simulation through different system abstraction levels. It demonstrates how high level mutations correlate to bit flips of software binaries by examples from the TriCore™ instruction set and finally presents a virtual platform based implementation for automated injection of bit flip based mutations into software binaries. Experimental results demonstrate the efficiency of the implemented approach."}],"related_material":{"link":[{"relation":"confirmation","url":"https://ieeexplore.ieee.org/document/7753545"}]},"citation":{"short":"P. Adelt, B. Koppelmann, W. Müller, M. Becker, B. Kleinjohann, C. Scheytt, in: Proceedings of the IEEE/IFIP International Conference on VLSI (VLSI-SOC), Tallin, Estonia, 2016.","chicago":"Adelt, Peer, Bastian Koppelmann, Wolfgang Müller, Markus Becker, Bernd Kleinjohann, and Christoph Scheytt. “Fast Dynamic Fault Injection for Virtual Microcontroller Platforms.” In <i>Proceedings of the IEEE/IFIP International Conference on VLSI (VLSI-SOC)</i>. Tallin, Estonia, 2016. <a href=\"https://doi.org/10.1109/VLSI-SoC.2016.7753545\">https://doi.org/10.1109/VLSI-SoC.2016.7753545</a>.","apa":"Adelt, P., Koppelmann, B., Müller, W., Becker, M., Kleinjohann, B., &#38; Scheytt, C. (2016). Fast Dynamic Fault Injection for Virtual Microcontroller Platforms. <i>Proceedings of the IEEE/IFIP International Conference on VLSI (VLSI-SOC)</i>. <a href=\"https://doi.org/10.1109/VLSI-SoC.2016.7753545\">https://doi.org/10.1109/VLSI-SoC.2016.7753545</a>","ieee":"P. Adelt, B. Koppelmann, W. Müller, M. Becker, B. Kleinjohann, and C. Scheytt, “Fast Dynamic Fault Injection for Virtual Microcontroller Platforms,” 2016, doi: <a href=\"https://doi.org/10.1109/VLSI-SoC.2016.7753545\">10.1109/VLSI-SoC.2016.7753545</a>.","ama":"Adelt P, Koppelmann B, Müller W, Becker M, Kleinjohann B, Scheytt C. Fast Dynamic Fault Injection for Virtual Microcontroller Platforms. In: <i>Proceedings of the IEEE/IFIP International Conference on VLSI (VLSI-SOC)</i>. ; 2016. doi:<a href=\"https://doi.org/10.1109/VLSI-SoC.2016.7753545\">10.1109/VLSI-SoC.2016.7753545</a>","bibtex":"@inproceedings{Adelt_Koppelmann_Müller_Becker_Kleinjohann_Scheytt_2016, place={Tallin, Estonia}, title={Fast Dynamic Fault Injection for Virtual Microcontroller Platforms}, DOI={<a href=\"https://doi.org/10.1109/VLSI-SoC.2016.7753545\">10.1109/VLSI-SoC.2016.7753545</a>}, booktitle={Proceedings of the IEEE/IFIP International Conference on VLSI (VLSI-SOC)}, author={Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Becker, Markus and Kleinjohann, Bernd and Scheytt, Christoph}, year={2016} }","mla":"Adelt, Peer, et al. “Fast Dynamic Fault Injection for Virtual Microcontroller Platforms.” <i>Proceedings of the IEEE/IFIP International Conference on VLSI (VLSI-SOC)</i>, 2016, doi:<a href=\"https://doi.org/10.1109/VLSI-SoC.2016.7753545\">10.1109/VLSI-SoC.2016.7753545</a>."},"publication":"Proceedings of the IEEE/IFIP International Conference on VLSI (VLSI-SOC)","user_id":"15931","doi":"10.1109/VLSI-SoC.2016.7753545","_id":"24264","language":[{"iso":"eng"}],"date_updated":"2022-02-17T13:57:45Z","author":[{"id":"5603","first_name":"Peer","last_name":"Adelt","full_name":"Adelt, Peer"},{"full_name":"Koppelmann, Bastian","last_name":"Koppelmann","first_name":"Bastian","id":"25260"},{"id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller","first_name":"Wolfgang"},{"full_name":"Becker, Markus","first_name":"Markus","last_name":"Becker"},{"full_name":"Kleinjohann, Bernd","first_name":"Bernd","last_name":"Kleinjohann"},{"first_name":"Christoph","last_name":"Scheytt","full_name":"Scheytt, Christoph","id":"37144"}],"publication_identifier":{"eissn":["2324-8440"]},"conference":{"end_date":"2016.09.28","start_date":"2016.09.26"},"title":"Fast Dynamic Fault Injection for Virtual Microcontroller Platforms","status":"public","year":"2016"},{"user_id":"15931","doi":"10.1109/RFIT.2016.7578132","language":[{"iso":"eng"}],"_id":"24265","date_updated":"2022-02-17T14:00:40Z","status":"public","year":"2016","title":"An all-transmission-line 220 GHz differential LNA in SiGe BiCMOS","publication_identifier":{"eisbn":["978-1-5090-1235-0"]},"author":[{"last_name":"Mao","first_name":"Yanfei","full_name":"Mao, Yanfei"},{"first_name":"Klaus","last_name":"Schmalz","full_name":"Schmalz, Klaus"},{"id":"37144","last_name":"Scheytt","first_name":"Christoph","full_name":"Scheytt, Christoph"},{"last_name":"Shiju","first_name":"E.","full_name":"Shiju, E."}],"conference":{"end_date":"2016.08.26","start_date":"2016.08.24"},"type":"conference","department":[{"_id":"58"}],"date_created":"2021-09-13T09:44:31Z","place":"Taipei, Taiwan","related_material":{"link":[{"relation":"confirmation","url":"https://ieeexplore.ieee.org/document/7578132"}]},"abstract":[{"lang":"eng","text":"This paper presents a four stage all-transmission-line 220 GHz differential LNA in SiGe BiCMOS technology. Cascode topology is chosen for each stage. The amplifier takes advantage of microstrip transmission lines to realize the inductive load, Marshand balun, input, output, and inter-stage matching of the LNA. The LNA has a gain of 21 dB at 224 GHz, a 3 dB bandwidth of more than 6 GHz. It has a supply voltage of 3V and power dissipation of 234 mW. The amplifier is intended for the use in communication, security scanning, imaging and remote sensing at 220 GHz."}],"publication":"IEEE International Symposium on Radio-Frequency Integration Technology","citation":{"chicago":"Mao, Yanfei, Klaus Schmalz, Christoph Scheytt, and E. Shiju. “An All-Transmission-Line 220 GHz Differential LNA in SiGe BiCMOS.” In <i>IEEE International Symposium on Radio-Frequency Integration Technology</i>. Taipei, Taiwan, 2016. <a href=\"https://doi.org/10.1109/RFIT.2016.7578132\">https://doi.org/10.1109/RFIT.2016.7578132</a>.","short":"Y. Mao, K. Schmalz, C. Scheytt, E. Shiju, in: IEEE International Symposium on Radio-Frequency Integration Technology, Taipei, Taiwan, 2016.","ieee":"Y. Mao, K. Schmalz, C. Scheytt, and E. Shiju, “An all-transmission-line 220 GHz differential LNA in SiGe BiCMOS,” 2016, doi: <a href=\"https://doi.org/10.1109/RFIT.2016.7578132\">10.1109/RFIT.2016.7578132</a>.","apa":"Mao, Y., Schmalz, K., Scheytt, C., &#38; Shiju, E. (2016). An all-transmission-line 220 GHz differential LNA in SiGe BiCMOS. <i>IEEE International Symposium on Radio-Frequency Integration Technology</i>. <a href=\"https://doi.org/10.1109/RFIT.2016.7578132\">https://doi.org/10.1109/RFIT.2016.7578132</a>","bibtex":"@inproceedings{Mao_Schmalz_Scheytt_Shiju_2016, place={Taipei, Taiwan}, title={An all-transmission-line 220 GHz differential LNA in SiGe BiCMOS}, DOI={<a href=\"https://doi.org/10.1109/RFIT.2016.7578132\">10.1109/RFIT.2016.7578132</a>}, booktitle={IEEE International Symposium on Radio-Frequency Integration Technology}, author={Mao, Yanfei and Schmalz, Klaus and Scheytt, Christoph and Shiju, E.}, year={2016} }","ama":"Mao Y, Schmalz K, Scheytt C, Shiju E. An all-transmission-line 220 GHz differential LNA in SiGe BiCMOS. In: <i>IEEE International Symposium on Radio-Frequency Integration Technology</i>. ; 2016. doi:<a href=\"https://doi.org/10.1109/RFIT.2016.7578132\">10.1109/RFIT.2016.7578132</a>","mla":"Mao, Yanfei, et al. “An All-Transmission-Line 220 GHz Differential LNA in SiGe BiCMOS.” <i>IEEE International Symposium on Radio-Frequency Integration Technology</i>, 2016, doi:<a href=\"https://doi.org/10.1109/RFIT.2016.7578132\">10.1109/RFIT.2016.7578132</a>."}},{"date_created":"2021-09-13T09:44:29Z","type":"conference","department":[{"_id":"58"}],"publication":"Analog 2016 - VDE","citation":{"ama":"Abughannam S, Wu L, Müller W, Scheytt C, Ecker W, Novello C. Fault Injection and Mixed-Level Simulation for Analog Circuits - A Case Study. In: <i>Analog 2016 - VDE</i>. ; 2016.","bibtex":"@inproceedings{Abughannam_Wu_Müller_Scheytt_Ecker_Novello_2016, title={Fault Injection and Mixed-Level Simulation for Analog Circuits - A Case Study}, booktitle={Analog 2016 - VDE}, author={Abughannam, Saed and Wu, Liang and Müller, Wolfgang and Scheytt, Christoph and Ecker, Wolfgang and Novello, Christiano}, year={2016} }","mla":"Abughannam, Saed, et al. “Fault Injection and Mixed-Level Simulation for Analog Circuits - A Case Study.” <i>Analog 2016 - VDE</i>, 2016.","short":"S. Abughannam, L. Wu, W. Müller, C. Scheytt, W. Ecker, C. Novello, in: Analog 2016 - VDE, 2016.","chicago":"Abughannam, Saed, Liang Wu, Wolfgang Müller, Christoph Scheytt, Wolfgang Ecker, and Christiano Novello. “Fault Injection and Mixed-Level Simulation for Analog Circuits - A Case Study.” In <i>Analog 2016 - VDE</i>, 2016.","apa":"Abughannam, S., Wu, L., Müller, W., Scheytt, C., Ecker, W., &#38; Novello, C. (2016). Fault Injection and Mixed-Level Simulation for Analog Circuits - A Case Study. <i>Analog 2016 - VDE</i>.","ieee":"S. Abughannam, L. Wu, W. Müller, C. Scheytt, W. Ecker, and C. Novello, “Fault Injection and Mixed-Level Simulation for Analog Circuits - A Case Study,” 2016."},"related_material":{"link":[{"relation":"confirmation","url":"https://ieeexplore.ieee.org/document/7584296/"}]},"abstract":[{"text":"The design of safety critical systems requires an efficient methodology for an effective fault effect simulation for analog and digital circuits where analog fault injection and fault effect simulation is currently a field of active research and commercial tools are not available yet. This article begins by discussing fault injection strategies for analog circuits applied on a case study with two topologies of a Voltage Controlled Oscillator (VCO). In the second part it performs on the basis of the example of a Wireless Sensor Network (WSN) node, how far different mixed level implementations with Verilog-A and SPICE can affect the simulation time and points out which component consumes the major part of the simulation time.","lang":"eng"}],"_id":"24263","language":[{"iso":"eng"}],"user_id":"15931","title":"Fault Injection and Mixed-Level Simulation for Analog Circuits - A Case Study","year":"2016","status":"public","publication_identifier":{"isbn":["978-3-8007-4265-3"]},"author":[{"first_name":"Saed","last_name":"Abughannam","full_name":"Abughannam, Saed","id":"37628"},{"full_name":"Wu, Liang","first_name":"Liang","last_name":"Wu","id":"30401"},{"last_name":"Müller","first_name":"Wolfgang","full_name":"Müller, Wolfgang","id":"16243"},{"id":"37144","first_name":"Christoph","last_name":"Scheytt","full_name":"Scheytt, Christoph"},{"full_name":"Ecker, Wolfgang","first_name":"Wolfgang","last_name":"Ecker"},{"full_name":"Novello, Christiano","first_name":"Christiano","last_name":"Novello"}],"conference":{"end_date":"2016.09.14","start_date":"2016.09.12"},"date_updated":"2022-02-17T13:58:08Z"},{"type":"conference","department":[{"_id":"58"}],"place":"Berlin, Germany","date_created":"2021-09-13T09:44:27Z","abstract":[{"lang":"eng","text":"Currently, all drone manufactures face the same problem: flight safety utility will become mandatory to obtain the legal admission for broad commercial use of drones. This means that on-board obstacle detection and collision avoidance is a must-have in order to overcome existing legal barriers and acceptance issues. Some of the currently available sensors are too large, too heavy, or can be poorly integrated into existing systems. During the exhibition a demonstration of a novel micro-sensor operating at 120 GHz will be given and participants will have the chance to experience the device first-hand."}],"publication":"DRONE Berlin 2016","citation":{"ama":"Nava F, Genschow D, Scheytt C. Obstacle detection using a miniaturized radar sensor operating at 120GHz ISM band. In: <i>DRONE Berlin 2016</i>. ; 2016.","bibtex":"@inproceedings{Nava_Genschow_Scheytt_2016, place={Berlin, Germany}, title={Obstacle detection using a miniaturized radar sensor operating at 120GHz ISM band}, booktitle={DRONE Berlin 2016}, author={Nava, Federico and Genschow, Dieter and Scheytt, Christoph}, year={2016} }","mla":"Nava, Federico, et al. “Obstacle Detection Using a Miniaturized Radar Sensor Operating at 120GHz ISM Band.” <i>DRONE Berlin 2016</i>, 2016.","chicago":"Nava, Federico, Dieter Genschow, and Christoph Scheytt. “Obstacle Detection Using a Miniaturized Radar Sensor Operating at 120GHz ISM Band.” In <i>DRONE Berlin 2016</i>. Berlin, Germany, 2016.","short":"F. Nava, D. Genschow, C. Scheytt, in: DRONE Berlin 2016, Berlin, Germany, 2016.","apa":"Nava, F., Genschow, D., &#38; Scheytt, C. (2016). Obstacle detection using a miniaturized radar sensor operating at 120GHz ISM band. <i>DRONE Berlin 2016</i>.","ieee":"F. Nava, D. Genschow, and C. Scheytt, “Obstacle detection using a miniaturized radar sensor operating at 120GHz ISM band,” 2016."},"user_id":"15931","language":[{"iso":"eng"}],"_id":"24262","date_updated":"2022-02-17T13:51:39Z","year":"2016","title":"Obstacle detection using a miniaturized radar sensor operating at 120GHz ISM band","status":"public","author":[{"first_name":"Federico","last_name":"Nava","full_name":"Nava, Federico"},{"first_name":"Dieter","last_name":"Genschow","full_name":"Genschow, Dieter"},{"id":"37144","full_name":"Scheytt, Christoph","first_name":"Christoph","last_name":"Scheytt"}]},{"language":[{"iso":"eng"}],"_id":"24271","publisher":"IEEE","doi":" 10.1109/BCTM.2016.7738962","user_id":"15931","conference":{"start_date":"2016.11.10"},"author":[{"last_name":"Javed","first_name":"Abdul Rehman","full_name":"Javed, Abdul Rehman"},{"id":"37144","full_name":"Scheytt, Christoph","last_name":"Scheytt","first_name":"Christoph"},{"id":"15739","full_name":"Von der Ahe, Uwe","last_name":"Von der Ahe","first_name":"Uwe"}],"publication_identifier":{"eissn":["https://ieeexplore.ieee.org/document/7738962"]},"status":"public","year":"2016","title":"Linear ultra-broadband NPN-only analog correlator at 33 Gbps in 130nm SiGe BiCMOS technology","date_updated":"2022-02-17T14:09:28Z","place":"New Brunswick, NJ, USA","date_created":"2021-09-13T09:44:39Z","department":[{"_id":"58"}],"type":"conference","citation":{"ama":"Javed AR, Scheytt C, Von der Ahe U. Linear ultra-broadband NPN-only analog correlator at 33 Gbps in 130nm SiGe BiCMOS technology. In: <i>IEEE Bipolar/BiCMOS Circuits and Technology Meeting</i>. IEEE; 2016. doi:<a href=\"https://doi.org/ 10.1109/BCTM.2016.7738962\"> 10.1109/BCTM.2016.7738962</a>","bibtex":"@inproceedings{Javed_Scheytt_Von der Ahe_2016, place={New Brunswick, NJ, USA}, title={Linear ultra-broadband NPN-only analog correlator at 33 Gbps in 130nm SiGe BiCMOS technology}, DOI={<a href=\"https://doi.org/ 10.1109/BCTM.2016.7738962\"> 10.1109/BCTM.2016.7738962</a>}, booktitle={IEEE Bipolar/BiCMOS Circuits and Technology Meeting}, publisher={IEEE}, author={Javed, Abdul Rehman and Scheytt, Christoph and Von der Ahe, Uwe}, year={2016} }","mla":"Javed, Abdul Rehman, et al. “Linear Ultra-Broadband NPN-Only Analog Correlator at 33 Gbps in 130nm SiGe BiCMOS Technology.” <i>IEEE Bipolar/BiCMOS Circuits and Technology Meeting</i>, IEEE, 2016, doi:<a href=\"https://doi.org/ 10.1109/BCTM.2016.7738962\"> 10.1109/BCTM.2016.7738962</a>.","short":"A.R. Javed, C. Scheytt, U. Von der Ahe, in: IEEE Bipolar/BiCMOS Circuits and Technology Meeting, IEEE, New Brunswick, NJ, USA, 2016.","chicago":"Javed, Abdul Rehman, Christoph Scheytt, and Uwe Von der Ahe. “Linear Ultra-Broadband NPN-Only Analog Correlator at 33 Gbps in 130nm SiGe BiCMOS Technology.” In <i>IEEE Bipolar/BiCMOS Circuits and Technology Meeting</i>. New Brunswick, NJ, USA: IEEE, 2016. <a href=\"https://doi.org/ 10.1109/BCTM.2016.7738962\">https://doi.org/ 10.1109/BCTM.2016.7738962</a>.","apa":"Javed, A. R., Scheytt, C., &#38; Von der Ahe, U. (2016). Linear ultra-broadband NPN-only analog correlator at 33 Gbps in 130nm SiGe BiCMOS technology. <i>IEEE Bipolar/BiCMOS Circuits and Technology Meeting</i>. <a href=\"https://doi.org/ 10.1109/BCTM.2016.7738962\">https://doi.org/ 10.1109/BCTM.2016.7738962</a>","ieee":"A. R. Javed, C. Scheytt, and U. Von der Ahe, “Linear ultra-broadband NPN-only analog correlator at 33 Gbps in 130nm SiGe BiCMOS technology,” 2016, doi: <a href=\"https://doi.org/ 10.1109/BCTM.2016.7738962\"> 10.1109/BCTM.2016.7738962</a>."},"publication":"IEEE Bipolar/BiCMOS Circuits and Technology Meeting","related_material":{"link":[{"url":"https://ieeexplore.ieee.org/document/7738962","relation":"confirmation"}]},"abstract":[{"lang":"eng","text":"An ultra-broadband analog correlator consisting of a four-quadrant multiplier and an ultra-fast resettable integrator using only NPN transistors was designed, fabricated, and measured. For the integrator, a cross-coupled transistor pair is used as a negative resistance generator. A novel ultra-fast reset circuit is implemented which allows to reset the integrator within very short time of 120 ps. The chip was fabricated using 130 nm SiGe BiCMOS technology with fT of 250 GHz and f max of 300 GHz. In the measurements carried out on printed circuit board, the correlator operated without noticeable performance degradation with inputs up to 33 Gbps which correspond to a bandwidth of more than 24 GHz. The correlator exhibits high linearity with output P1dB of more than 9.9 dBm (700 mV diff ) for both inputs. It dissipates 122.5 mW for the core circuit excluding the 50 Ω output driver. To the knowledge of the authors, the circuit represents the fastest analog correlator published so far. It can be used for spread spectrum communication, radar signal processing, and measurement applications."}]},{"doi":" 10.1016/j.protcy.2016.08.031","user_id":"15931","page":"227-234","_id":"24269","publisher":"Elsevier","language":[{"iso":"eng"}],"date_updated":"2022-02-17T14:06:38Z","status":"public","title":"Hierarchical Scheduling for Plug-and-Produce","year":"2016","author":[{"last_name":"Jatzkowski","first_name":"Jan","full_name":"Jatzkowski, Jan"},{"id":"5603","first_name":"Peer","last_name":"Adelt","full_name":"Adelt, Peer"},{"full_name":"Rettberg, Achim","first_name":"Achim","last_name":"Rettberg"}],"type":"conference","department":[{"_id":"58"}],"place":"Paderborn, DE","date_created":"2021-09-13T09:44:37Z","related_material":{"link":[{"url":"https://scholar.google.de/scholar?q=10.1016/j.protcy.2016.08.031&hl=de&as_sdt=0&as_vis=1&oi=scholart","relation":"confirmation"}]},"abstract":[{"text":"Today's increasing number of sensors and computation nodes covered by cyber physical systems (CPS) results in rising complexity. For instance, computation results are based on measured data whose quality strongly depends on their age. CPS therefore have real-time requirements on computation results and communication to keep temporal dependency between measured inputs and computed outputs. In addition, today's CPS shall be modular to enable flexibility and scalability, e.g., postulated for production systems in context of Industry 4.0. Enabling CPS to easily integrate components by some Plug-and-Produce mechanism is desired.In this paper, we aim at enabling Plug-and-Produce in CPS using hypervisor-based virtualization. This implies hierarchical scheduling of dependent real-time systems. Here, dependencies are given by precedence constraints of tasks. Based on an approach for detection of new components added to a real-time network, in this paper we focus on integration of enabled applications into the current schedule of a computation node. Here, enabled application refers to an application software that just got executable by plugging some component to the CPS. Applications are encapsulated by virtual machines and provide a self-description including information about required and provided data as well as timing behavior. This self-description is used to adjust global scheduling and thus include new functionality to the CPS.","lang":"eng"}],"publication":"3rd International Conference on System-integrated Intelligence: New Challenges for Product and Production Engineering","citation":{"short":"J. Jatzkowski, P. Adelt, A. Rettberg, in: 3rd International Conference on System-Integrated Intelligence: New Challenges for Product and Production Engineering, Elsevier, Paderborn, DE, 2016, pp. 227–234.","chicago":"Jatzkowski, Jan, Peer Adelt, and Achim Rettberg. “Hierarchical Scheduling for Plug-and-Produce.” In <i>3rd International Conference on System-Integrated Intelligence: New Challenges for Product and Production Engineering</i>, 227–34. Paderborn, DE: Elsevier, 2016. <a href=\"https://doi.org/ 10.1016/j.protcy.2016.08.031\">https://doi.org/ 10.1016/j.protcy.2016.08.031</a>.","apa":"Jatzkowski, J., Adelt, P., &#38; Rettberg, A. (2016). Hierarchical Scheduling for Plug-and-Produce. <i>3rd International Conference on System-Integrated Intelligence: New Challenges for Product and Production Engineering</i>, 227–234. <a href=\"https://doi.org/ 10.1016/j.protcy.2016.08.031\">https://doi.org/ 10.1016/j.protcy.2016.08.031</a>","ieee":"J. Jatzkowski, P. Adelt, and A. Rettberg, “Hierarchical Scheduling for Plug-and-Produce,” in <i>3rd International Conference on System-integrated Intelligence: New Challenges for Product and Production Engineering</i>, 2016, pp. 227–234, doi: <a href=\"https://doi.org/ 10.1016/j.protcy.2016.08.031\"> 10.1016/j.protcy.2016.08.031</a>.","ama":"Jatzkowski J, Adelt P, Rettberg A. Hierarchical Scheduling for Plug-and-Produce. In: <i>3rd International Conference on System-Integrated Intelligence: New Challenges for Product and Production Engineering</i>. Elsevier; 2016:227-234. doi:<a href=\"https://doi.org/ 10.1016/j.protcy.2016.08.031\"> 10.1016/j.protcy.2016.08.031</a>","bibtex":"@inproceedings{Jatzkowski_Adelt_Rettberg_2016, place={Paderborn, DE}, title={Hierarchical Scheduling for Plug-and-Produce}, DOI={<a href=\"https://doi.org/ 10.1016/j.protcy.2016.08.031\"> 10.1016/j.protcy.2016.08.031</a>}, booktitle={3rd International Conference on System-integrated Intelligence: New Challenges for Product and Production Engineering}, publisher={Elsevier}, author={Jatzkowski, Jan and Adelt, Peer and Rettberg, Achim}, year={2016}, pages={227–234} }","mla":"Jatzkowski, Jan, et al. “Hierarchical Scheduling for Plug-and-Produce.” <i>3rd International Conference on System-Integrated Intelligence: New Challenges for Product and Production Engineering</i>, Elsevier, 2016, pp. 227–34, doi:<a href=\"https://doi.org/ 10.1016/j.protcy.2016.08.031\"> 10.1016/j.protcy.2016.08.031</a>."}}]