@article{24216, abstract = {{In this article mixed analog/digital signal processing techniques based on parallel spread-spectrum sequencing (PSSS) and radio frequency (RF) carrier synchronization for ultra-broadband wireless communication are investigated on system and circuit level.}}, author = {{Scheytt, Christoph and Javed, Abdul Rehman and Bammidi, Eswara Rao and KrishneGowda, Karthik and Kallfass, Ingmar and Kraemer, Rolf}}, journal = {{Frequenz* Journal of RF-Engineering and Telecommunications}}, number = {{9-10}}, pages = {{399--414}}, title = {{{100 Gbps Wireless System and Circuit Design Using Parallel Spread-Spectrum Sequencing}}}, volume = {{71 }}, year = {{2017}}, } @inproceedings{24217, abstract = {{Parallel Sequence Spread Spectrum (PSSS) is a physical layer (PHY) baseband technology that is well suited for mixed-signal transceiver implementation for high data rate wireless communication systems. Mixed signal baseband realization allows for easier implementation of the channel equalization function and eliminates the need for high speed data converters. System design and architecture of a mixed signal baseband processor for 100 Gbps wireless communication is described that reduces the implementation complexity and results in a consequent reduction in power dissipation and chip area. An ultra-broadband analog correlator consisting of a four-quadrant multiplier and a fast resettable integrator using only NPN transistors was designed, fabricated, and measured. The correlator circuit is the core component of the receiver baseband. To the best knowledge of the authors, it is the fastest correlator circuit published so far.}}, author = {{Javed, Abdul Rehman and Scheytt, Christoph and Karthik, KrishneGowda and Kramer, Roland}}, booktitle = {{IEEE EUROCON 2017-17th International Conference on Smart Technologies}}, isbn = {{978-1-5090-3844-2}}, pages = {{228--233}}, title = {{{System design of a mixed signal PSSS transdeiver using a linear ultra-broadband analog correlator for the receiver baseband designed in 130nm SiGe BiCMOS technology}}}, doi = {{10.1109/EUROCON.2017.8011110}}, year = {{2017}}, } @misc{24218, abstract = {{ Die Erfindung betrifft eine Folge-Halte-Schaltung zum Konvertieren eines analogen Eingangssignals in ein digitales Ausgangssignal mit einer Haltekapazitätseinheit, mit einer Spannungsverstärkereinheit enthaltend einen Eingang, an dem ein analoges Eingangsspannungssignal anlegbar ist, und enthaltend einen Ausgang, der mit der Haltekapazitätseinheit verbunden ist, mit einer Arbeitspunkteinstelleinheit zur Steuerung der Spannungsverstärkereinheit, wobei an einem Eingang der Arbeitspunkteinstelleinheit ein Steuersignal anliegt, so dass in einem Folgebetrieb der Folge-Halte-Schaltung eine an dem Ausgang der Spannungsverstärkereinheit anliegendes Ausgangssignal einen an den Eingang der Spannungsverstärkereinheit anliegendes Eingangssignal folgt, und in einem Haltebetrieb der Folge-Halte-Schaltung das Ausgangssignal der Spannungsverstärkereinheit konstant ist, mit einer Taktsignalquelle zur Erzeugung einer Folge von einem Eingang der Arbeitspunkteinstelleinheit anliegenden Taktsignalen, wobei die Arbeitspunkteinstelleinheit elektrooptische Mittel zur Erzeugung des Steuersignals aufweist, dass die Taktsignalquelle als eine optische Taktsignalquelle ausgebildet ist, so dass als Taktsignal eine optische Impulsfolge mit hohen und tiefen Taktsignalen an den Eingang der Arbeitspunkteinstelleinheit anliegt. }}, author = {{Scheytt, Christoph}}, title = {{{Folge-Halte-Schaltung }}}, year = {{2017}}, } @inproceedings{24219, abstract = {{In this paper we present theoretical, simulated and measured data for a reader to tag communication RFID system at 5.8 GHz. First a theoretical link budget analysis for a reader to tag architecture is shown for a wireless industrial application at 1m distance. This includes a power budget of the passively powered transponder. The received power level of the backscattered data for the theoretical link budget is -52:5 dBm. For the first setup slot antennas are developed and measured in the anechoic chamber. The measured gain is 4.0 dB. The power of the backscatter data in setup 1 is -74:8 dBm. This corresponds to the theoretical link budget since, all losses such as cable or lower antenna gain are taken into account. Setup 2 is upgraded on the reader side with horn antennas. At 5.8 GHz, the gain reaches the value of 10.8 dB. The second setup shows improvement in the receiving backscattered power to a value of -62:4 dBm. Furthermore, as a solution to detect those transponders not presented in the main slope of the antenna, a steerable beam is introduced by means of a Rotman lens. On the topic of the passive transponder, different harvesting topologies at 5.8 GHz are investigated, and the efficiency simulation of the harvesting circuitry has been performed. The simulated efficiency of the implemented technique is 68 %.}}, author = {{Kuhn, Peter and Haddadian, Sanaz and Meyer, Frederic and Hoffmann, Marc and Grabmaier, Anton and Scheytt, Christoph and Kaiser, Thomas}}, booktitle = {{Smart SysTech 2017; European Conference on Smart Objects, Systems and Technologies}}, isbn = {{978-3-8007-4428-2}}, publisher = {{VDE ITG}}, title = {{{SHF RFID System for Automatic Process Optimization with Intelligent Tools}}}, year = {{2017}}, } @inproceedings{24220, author = {{Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Mueller-Gritschneder, Daniel and Kleinjohann, Bernd and Scheytt, Christoph}}, booktitle = {{Tagungsband des Wissenschaftsforums Intelligente Technische Systeme}}, isbn = {{978-3-942647-88-5}}, publisher = {{Verlagsschriftenreihe des Heinz Nixdorf Instituts}}, title = {{{Automatisierte Fehlerinjektion zur Entwicklung sicherer Mikrocontrolleranwendungen auf der Basis virtueller Plattformen}}}, doi = {{10.17619/UNIPB/1-93}}, year = {{2017}}, } @book{24221, abstract = {{Das Wissenschaftsforum Intelligente Technische Systeme (WInTeSys) legt am 11. und 12. Mai 2017 in Paderborn den Schwerpunkt auf die Grundlagen und die Entwicklung intelligenter technischer Systeme im Kontext Industrie 4.0. Etwa 40 begutachtete hochkarätige Beiträge geben einen Überblick über Forschungsfelder, Technologien und Anwendungen. Die Veranstaltung bietet den Teilnehmerinnen und Teilnehmern eine ausgezeichnete Bühne für den Erfahrungsaustausch auf dem Weg in die Digitalisierung von Produkten und Produktionssystemen. »Das Besondere ist der Dialog von Hochschulforschung und industrieller Entwicklung, also das Aufeinandertreffen von »Science-Push« und »Application-Pull«. Die Beiträge spiegeln die hervorragende Vernetzung in der Region OWL und darüber hinaus wider«, sagt Veranstalter Prof. Jürgen Gausemeier (Heinz Nixdorf Institut, Universität Paderborn).}}, author = {{Gausemeier, Jürgen and Bodden, Eric and Dressler, Falko and Dumitrescu, Roman and Meyer auf der Heide, Friedhelm and Scheytt, Christoph and Trächtler, Ansgar}}, isbn = {{978-3-942647-88-5}}, publisher = {{Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn}}, title = {{{Wissenschaftsforum Intelligente Technische Systeme (WInTeSys)}}}, doi = {{10.17619/UNIPB/1-93}}, volume = {{369}}, year = {{2017}}, } @inproceedings{24222, abstract = {{This paper focuses on the design of a high efficiency cross-connected differential drive rectifier for next-generation passive RFID tags. To provide a realistic estimation of the transponders’power and efficiency requirements at 5.8 GHz, detailed link/power-budget analysis for various blocks of the tag chip is carried out. From link budget analysis realistic RF power levels are obtained and a rectifier with high conversion efficiency at low power levels is designed. Simulations based on a commercial 65nm CMOS technology investigate the suitability of the harvesting circuit for 5.8 GHz RFID tags.}}, author = {{Haddadian, Sanaz and Scheytt, Christoph and Kramer, Roland}}, booktitle = {{ANALOG 2017; 16th ITG/GMM-Symposium}}, pages = {{18}}, publisher = {{Technische Universität Berlin}}, title = {{{Energy Harvesting Analysis for Next Generation Passive RFID Tags}}}, year = {{2017}}, } @inproceedings{24223, abstract = {{This paper presents the design flow of using sampling technique for fault injection on sche- matic level. The parameters used in the docu- ment to calculate the likelihood could be modi- fied by using more realistic data from the fab. With the help of the fault simulator, the whole design flow of the fault effect simulation can be realized automatically.}}, author = {{Wu, Liang and Abughannam, Saed and Müller, Wolfgang and Scheytt, Christoph and Ecker, Wolfgang}}, booktitle = {{2nd Workshop on Resiliency in Embedded Electronic Systems (REES)}}, pages = {{68}}, title = {{{SPICE-Level Fault Injection with Likelihood Weighted Random Sampling - A Case Study}}}, year = {{2017}}, } @inproceedings{24224, author = {{Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Kleinjohann, Bernd and Scheytt, Christoph}}, booktitle = {{Design Automation and Testing in Europe (DATE), University Booth Interactive Presentation}}, title = {{{ANALISA - A Tool for Static Instruction Set Analysis}}}, year = {{2017}}, } @inproceedings{24225, author = {{Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Kleinjohann, Bernd and Scheytt, Christoph}}, booktitle = {{2nd Workshop on Resiliency in Embedded Electronic Systems (REES) }}, pages = {{44}}, title = {{{An Automatic Injection Framework for Safety Assessements of Embedded Software Binaries}}}, year = {{2017}}, }