@inproceedings{24058, abstract = {{Embedded systems require a high energy efficiency in combination with an optimized performance. As such, Bit Manipulation Instructions (BMIs) were introduced for x86 and ARMv8 to improve the runtime efficiency and power dissipation of the compiled software for various applications. Though the RISC-V platform is meanwhile widely accepted for embedded systems application, its instruction set architecture (ISA) currently still supports only two basic BMIs.We introduce ten advanced BMIs for the RISC-V ISA and implemented them on Berkeley's Rocket CPU [1], which we synthesized for the Artix-7 FPGA and the TSMC 65nm cell library. Our RISC-V BMI definitions are based on an analysis and combination of existing x86 and ARMv8 BMIs. Our Rocket CPU hardware extensions show that RISC-V BMI extensions have no negative impact on the critical path of the execution pipeline. Our software evaluations show that we can, for example, expect a significant impact for time and power consuming cryptographic applications.}}, author = {{Koppelmann, Bastian and Adelt, Peer and Müller, Wolfgang and Scheytt, Christoph}}, booktitle = {{29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)}}, title = {{{RISC-V Extensions for Bit Manipulation Instructions}}}, doi = {{10.1109/PATMOS.2019.8862170}}, year = {{2019}}, } @inproceedings{24059, abstract = {{We present a complete Visible Light Communication (VLC) system for experimental Vehicular VLC (V-VLC) research activities. Visible light is becoming an important technology complementing existing Radio Frequency (RF) technologies such as Cellular V2X (C-V2X) and Dedicated Short Range Communication (DSRC). In this scope, first works helped introducing new simulation models to explore V-VLC capabilities, technologies, and algorithms. Yet, experimental prototypes are still in an early phase. We aim bridging this gap with our system, which integrates a custom-made driver hardware, commercial vehicle light modules, and an Open Source signal processing implementation in GNU Radio, which explicitly offers rapid prototyping. Our system supports OFDM with a variety of Modulation and Coding Schemes (MCS) and is compliant to IEEE 802.11; this is in line with the upcoming IEEE 802.11 LC standard as well. In an extensive series of experiments, we assessed the communication performance by looking at realistic inter vehicle distances. Our results clearly show that our system supports even higher order MCS with very low error rates over long distances.}}, author = {{Amjad, Muhammad Sohaib and Tebruegge, Claas and Memedi, Agon and Kruse, Stephan and Kress, Christian and Scheytt, Christoph and Dressler, Falko}}, booktitle = {{IEEE International Conference on Communications (ICC)}}, pages = {{1--6}}, publisher = {{ICC 2019 - 2019 IEEE International Conference on Communications (ICC)}}, title = {{{An IEEE 802.11 Compliant SDR-Based System for Vehicular Visible Light Communications}}}, doi = {{10.1109/ICC.2019.8761960}}, year = {{2019}}, } @inproceedings{24060, abstract = {{In diesem Artikel stellen wir eine Methode zur nicht-invasiven dynamischen Speicher- und IO-Analyse mit QEMU für sicherheitskritische eingebettete Software für die RISC-V Befehlssatzarchitektur vor. Die Implementierung basiert auf einer Erweiterung des Tiny Code Generator (TCG) des quelloffenen CPU-Emulators QEMU um die dynamische Identifikation von Zugriffen auf Datenspeicher sowie auf an die CPU angeschlossene IO-Geräte. Wir demonstrieren die Funktionalität der Methode anhand eines Versuchsaufbaus, bei dem eine Schließsystemkontrolle mittels serieller UART-Schnittstelle an einen RISC-V-Prozessor angebunden ist. Dieses Szenario zeigt, dass ein unberechtigter Zugriff auf die UART-Schnittstelle frühzeitig aufgedeckt und ein Angriff auf eine Zugangskontrolle somit endeckt werden kann. }}, author = {{Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Scheytt, Christoph}}, booktitle = {{MBMV 2019-22.Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2019)}}, isbn = {{978-3-8007-4945-4}}, title = {{{Analyse sicherheitskritischer Software für RISC-V Prozessoren}}}, year = {{2019}}, } @inproceedings{24061, author = {{Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Scheytt, Christoph and Driessen, Benedikt}}, booktitle = {{ 2nd International Workshop on Embedded Software for Industrial IoT in conjunction with DATE 2019}}, pages = {{32--34}}, title = {{{QEMU for Dynamic Memory Analysis of Security Sensitive Software}}}, year = {{2019}}, } @article{24063, abstract = {{It its current Version 3.1.0 QEMU supports RISC-V RV32GC and RV64GC software emulation in user and full system mode. We will first give an overview of the current state of the QEMU RISC-V implementation. Thereafter, we will present the DecodeTree tool, which will be available with the next QEMU release. DecodeTree is a code generator included in QEMU that can generate the program logic for extracting and decoding opcodes and operands from a formal instruction list of the target architecture. This enables the structured implementation of just-in-time compilations to guarantee that the QEMU implementation meets the ISA specification. As such, we completely replaced the existing RISC-V RV32GC and RV64GC implementations by DecodeTree generations in the next official QEMU release, which is expected in spring 2019. We will demonstrate the DecodeTree applications by the example of RISC-V ISA subset configurations.}}, author = {{Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Scheytt, Christoph}}, journal = {{2nd International Workshop on RISC-V Research Activities}}, title = {{{QEMU Support for RISC-V: Current State and Future Releases}}}, volume = {{(Presentation)}}, year = {{2019}}, } @inbook{24097, author = {{Hoyer, Kay-Peter and Schaper, Mirko}}, booktitle = {{TMS 2019 148th Annual Meeting & Exhibition Supplemental Proceedings}}, issn = {{2367-1181}}, title = {{{Alloy Design for Biomedical Applications in Additive Manufacturing}}}, doi = {{10.1007/978-3-030-05861-6_44}}, year = {{2019}}, } @inbook{24098, author = {{Tasche, Lennart and Hoyer, Kay-Peter and Zhuravlev, Evgeny and Grundmeier, Guido and Schaper, Mirko and Keßler, Olaf}}, booktitle = {{TMS 2019 148th Annual Meeting & Exhibition Supplemental Proceedings}}, issn = {{2367-1181}}, title = {{{Surface Inoculation of Aluminium Powders for Additive Manufacturing Guided by Differential Fast Scanning Calorimetry}}}, doi = {{10.1007/978-3-030-05861-6_45}}, year = {{2019}}, } @proceedings{24102, editor = {{Eiber, Marion}}, issn = {{2509-8772}}, location = {{Berlin}}, title = {{{Einfluss von Eigenspannungen und Oberflächenrauheit additiv gefertigter Komponenten aus 316L auf die Beschichtbarkeit und Ermüdungsfestigkeit, }}}, year = {{2019}}, } @proceedings{24103, editor = {{Azarmi, Fardad }}, isbn = {{9781510888005}}, location = {{Yokohama}}, publisher = {{ASM International}}, title = {{{Adhesion of HVOF sprayed WC-Co coatings on additively processed 316L}}}, year = {{2019}}, } @article{24122, author = {{Inguva, Venkatesh and Graceffa, Rita and Schulz, Joachim and Bilsel, Osman and Perot, Blair J.}}, issn = {{1738-494X}}, journal = {{Journal of Mechanical Science and Technology}}, pages = {{4281--4289}}, title = {{{Creating round focused micro-jets from rectangular nozzles}}}, doi = {{10.1007/s12206-019-0824-x}}, year = {{2019}}, }