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Szopinski, T. John, D. Kundisch, in: 2019.","ieee":"D. Szopinski, T. John, and D. Kundisch, “Digital Tools for Teaching Business Model Innovation in Information Systems: A newly developed didactic approach comprising video-based peer feedback,” presented at the Workshop on Information Technology and Systems (WITS), Munich, Germany, 2019.","apa":"Szopinski, D., John, T., & Kundisch, D. (2019). Digital Tools for Teaching Business Model Innovation in Information Systems: A newly developed didactic approach comprising video-based peer feedback. Presented at the Workshop on Information Technology and Systems (WITS), Munich, Germany.","ama":"Szopinski D, John T, Kundisch D. Digital Tools for Teaching Business Model Innovation in Information Systems: A newly developed didactic approach comprising video-based peer feedback. In: ; 2019.","chicago":"Szopinski, Daniel, Thomas John, and Dennis Kundisch. “Digital Tools for Teaching Business Model Innovation in Information Systems: A Newly Developed Didactic Approach Comprising Video-Based Peer Feedback,” 2019.","bibtex":"@inproceedings{Szopinski_John_Kundisch_2019, title={Digital Tools for Teaching Business Model Innovation in Information Systems: A newly developed didactic approach comprising video-based peer feedback}, author={Szopinski, Daniel and John, Thomas and Kundisch, Dennis}, year={2019} }","mla":"Szopinski, Daniel, et al. Digital Tools for Teaching Business Model Innovation in Information Systems: A Newly Developed Didactic Approach Comprising Video-Based Peer Feedback. 2019."}},{"title":"Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers","user_id":"477","department":[{"_id":"78"},{"_id":"34"},{"_id":"7"}],"publisher":"Universität Paderborn","author":[{"id":"49992","last_name":"Hansmeier","full_name":"Hansmeier, Tim","orcid":"0000-0003-1377-3339","first_name":"Tim"}],"date_created":"2019-11-05T14:32:46Z","project":[{"_id":"14","name":"SFB 901 - Subproject C2"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"1","name":"SFB 901"}],"status":"public","_id":"14546","date_updated":"2022-01-06T06:52:02Z","citation":{"ieee":"T. Hansmeier, Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers. Universität Paderborn, 2019.","short":"T. Hansmeier, Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers, Universität Paderborn, 2019.","mla":"Hansmeier, Tim. Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers. Universität Paderborn, 2019.","bibtex":"@book{Hansmeier_2019, title={Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers}, publisher={Universität Paderborn}, author={Hansmeier, Tim}, year={2019} }","apa":"Hansmeier, T. (2019). Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers. Universität Paderborn.","ama":"Hansmeier T. Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers. Universität Paderborn; 2019.","chicago":"Hansmeier, Tim. Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers. Universität Paderborn, 2019."},"year":"2019","type":"mastersthesis","supervisor":[{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"language":[{"iso":"eng"}]},{"language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:51:27Z","department":[{"_id":"48"}],"publication_identifier":{"eissn":["1937-4151"]},"publication_status":"published","title":"Built-in Test for Hidden Delay Faults","year":"2019","citation":{"ama":"Kampmann M, A. Kochte M, Liu C, Schneider E, Hellebrand S, Wunderlich H-J. Built-in Test for Hidden Delay Faults. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). 2019;38(10):1956-1968.","apa":"Kampmann, M., A. Kochte, M., Liu, C., Schneider, E., Hellebrand, S., & Wunderlich, H.-J. (2019). Built-in Test for Hidden Delay Faults. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 38(10), 1956–1968.","chicago":"Kampmann, Matthias, Michael A. Kochte, Chang Liu, Eric Schneider, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Built-in Test for Hidden Delay Faults.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 38, no. 10 (2019): 1956–68.","bibtex":"@article{Kampmann_A. Kochte_Liu_Schneider_Hellebrand_Wunderlich_2019, title={Built-in Test for Hidden Delay Faults}, volume={38}, number={10}, journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)}, publisher={IEEE}, author={Kampmann, Matthias and A. Kochte, Michael and Liu, Chang and Schneider, Eric and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2019}, pages={1956–1968} }","mla":"Kampmann, Matthias, et al. “Built-in Test for Hidden Delay Faults.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 38, no. 10, IEEE, 2019, pp. 1956–68.","short":"M. Kampmann, M. A. Kochte, C. Liu, E. Schneider, S. Hellebrand, H.-J. Wunderlich, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 38 (2019) 1956–1968.","ieee":"M. Kampmann, M. A. Kochte, C. Liu, E. Schneider, S. Hellebrand, and H.-J. Wunderlich, “Built-in Test for Hidden Delay Faults,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 38, no. 10, pp. 1956–1968, 2019."},"type":"journal_article","page":"1956 - 1968","intvolume":" 38","_id":"13048","issue":"10","author":[{"first_name":"Matthias","full_name":"Kampmann, Matthias","last_name":"Kampmann","id":"10935"},{"last_name":"A. Kochte","full_name":"A. Kochte, Michael","first_name":"Michael"},{"first_name":"Chang","full_name":"Liu, Chang","last_name":"Liu"},{"full_name":"Schneider, Eric","first_name":"Eric","last_name":"Schneider"},{"id":"209","last_name":"Hellebrand","full_name":"Hellebrand, Sybille","orcid":"0000-0002-3717-3939","first_name":"Sybille"},{"last_name":"Wunderlich","full_name":"Wunderlich, Hans-Joachim","first_name":"Hans-Joachim"}],"publisher":"IEEE","publication":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)","volume":38,"status":"public","date_created":"2019-08-28T11:44:25Z","abstract":[{"lang":"eng","text":"Marginal hardware introduces severe reliability threats throughout the life cycle of a system. Although marginalities may not affect the functionality of a circuit immediately after manufacturing, they can degrade into hard failures and must be screened out during manufacturing test to prevent early life failures. Furthermore, their evolution in the field must be proactively monitored by periodic tests before actual failures occur. In recent years small delay faults have gained increasing attention as possible indicators of marginal hardware. However, small delay faults on short paths may be undetectable even with advanced timing aware ATPG. Faster-than-at-speed test (FAST) can detect such hidden delay faults, but so far FAST has mainly been restricted to manufacturing test."}],"user_id":"209"},{"date_updated":"2022-01-06T06:51:28Z","_id":"13106","conference":{"name":"53. Jahrestagung der Gesellschaft für Didaktik der Mathematik","location":"Regensburg"},"citation":{"ieee":"J. Schumacher, “Rekonstruktion diagrammatischen Schließens am Beispiel der Subtraktion negativer Zahlen,” in Beiträge zum Mathematikunterricht 2019, Regensburg.","short":"J. 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