---
_id: '6856'
author:
- first_name: Michelle
full_name: Müller, Michelle
last_name: Müller
- first_name: Dominik
full_name: Gutt, Dominik
id: '14368'
last_name: Gutt
citation:
ama: 'Müller M, Gutt D. Heart over Heels? An Empirical Analysis of the Relationship
between Emotions and Review Helpfulness for Experience and Credence Goods. In:
Wirtschaftsinformatik Proceedings 2019. ; 2019.'
apa: Müller, M., & Gutt, D. (2019). Heart over Heels? An Empirical Analysis
of the Relationship between Emotions and Review Helpfulness for Experience and
Credence Goods. In Wirtschaftsinformatik Proceedings 2019. Siegen, Germany.
bibtex: '@inproceedings{Müller_Gutt_2019, title={Heart over Heels? An Empirical
Analysis of the Relationship between Emotions and Review Helpfulness for Experience
and Credence Goods}, booktitle={Wirtschaftsinformatik Proceedings 2019}, author={Müller,
Michelle and Gutt, Dominik}, year={2019} }'
chicago: Müller, Michelle, and Dominik Gutt. “Heart over Heels? An Empirical Analysis
of the Relationship between Emotions and Review Helpfulness for Experience and
Credence Goods.” In Wirtschaftsinformatik Proceedings 2019, 2019.
ieee: M. Müller and D. Gutt, “Heart over Heels? An Empirical Analysis of the Relationship
between Emotions and Review Helpfulness for Experience and Credence Goods,” in
Wirtschaftsinformatik Proceedings 2019, Siegen, Germany, 2019.
mla: Müller, Michelle, and Dominik Gutt. “Heart over Heels? An Empirical Analysis
of the Relationship between Emotions and Review Helpfulness for Experience and
Credence Goods.” Wirtschaftsinformatik Proceedings 2019, 2019.
short: 'M. Müller, D. Gutt, in: Wirtschaftsinformatik Proceedings 2019, 2019.'
conference:
location: Siegen, Germany
name: Wirtschaftsinformatik
date_created: 2019-01-17T14:39:49Z
date_updated: 2022-01-06T07:03:22Z
department:
- _id: '276'
language:
- iso: eng
project:
- _id: '1'
name: SFB 901
- _id: '2'
name: SFB 901 - Project Area A
- _id: '8'
name: SFB 901 - Subproject A4
publication: Wirtschaftsinformatik Proceedings 2019
status: public
title: Heart over Heels? An Empirical Analysis of the Relationship between Emotions
and Review Helpfulness for Experience and Credence Goods
type: conference
user_id: '16205'
year: '2019'
...
---
_id: '6857'
author:
- first_name: Martin
full_name: Poniatowski, Martin
id: '32441'
last_name: Poniatowski
- first_name: Jürgen
full_name: Neumann, Jürgen
id: '32456'
last_name: Neumann
- first_name: Thomas
full_name: Görzen, Thomas
id: '47700'
last_name: Görzen
- first_name: Dennis
full_name: Kundisch, Dennis
id: '21117'
last_name: Kundisch
citation:
ama: 'Poniatowski M, Neumann J, Görzen T, Kundisch D. A Semi-Automated Approach
for Generating Online Review Templates, . In: Wirtschaftsinformatik Proceedings
2019. ; 2019.'
apa: Poniatowski, M., Neumann, J., Görzen, T., & Kundisch, D. (2019). A Semi-Automated
Approach for Generating Online Review Templates, . In Wirtschaftsinformatik
Proceedings 2019. Siegen, Germany.
bibtex: '@inproceedings{Poniatowski_Neumann_Görzen_Kundisch_2019, title={A Semi-Automated
Approach for Generating Online Review Templates, }, booktitle={Wirtschaftsinformatik
Proceedings 2019}, author={Poniatowski, Martin and Neumann, Jürgen and Görzen,
Thomas and Kundisch, Dennis}, year={2019} }'
chicago: Poniatowski, Martin, Jürgen Neumann, Thomas Görzen, and Dennis Kundisch.
“A Semi-Automated Approach for Generating Online Review Templates, .” In Wirtschaftsinformatik
Proceedings 2019, 2019.
ieee: M. Poniatowski, J. Neumann, T. Görzen, and D. Kundisch, “A Semi-Automated
Approach for Generating Online Review Templates, ,” in Wirtschaftsinformatik
Proceedings 2019, Siegen, Germany, 2019.
mla: Poniatowski, Martin, et al. “A Semi-Automated Approach for Generating Online
Review Templates, .” Wirtschaftsinformatik Proceedings 2019, 2019.
short: 'M. Poniatowski, J. Neumann, T. Görzen, D. Kundisch, in: Wirtschaftsinformatik
Proceedings 2019, 2019.'
conference:
location: Siegen, Germany
name: Wirtschaftsinformatik
date_created: 2019-01-17T14:46:50Z
date_updated: 2022-01-06T07:03:22Z
department:
- _id: '276'
language:
- iso: eng
project:
- _id: '1'
name: SFB 901
- _id: '2'
name: SFB 901 - Project Area A
- _id: '8'
name: SFB 901 - Subproject A4
publication: Wirtschaftsinformatik Proceedings 2019
status: public
title: 'A Semi-Automated Approach for Generating Online Review Templates, '
type: conference
user_id: '477'
year: '2019'
...
---
_id: '6860'
author:
- first_name: Haitham
full_name: Afifi, Haitham
id: '65718'
last_name: Afifi
- first_name: Holger
full_name: Karl, Holger
id: '126'
last_name: Karl
citation:
ama: 'Afifi H, Karl H. Power Allocation with a Wireless Multi-cast Aware Routing
for Virtual Network Embedding. In: 2019 16th IEEE Annual Consumer Communications
& Networking Conference (CCNC2019). Las Vegas: IEEE.'
apa: 'Afifi, H., & Karl, H. (n.d.). Power Allocation with a Wireless Multi-cast
Aware Routing for Virtual Network Embedding. In 2019 16th IEEE Annual Consumer
Communications & Networking Conference (CCNC2019). Las Vegas: IEEE.'
bibtex: '@inproceedings{Afifi_Karl, place={Las Vegas}, title={Power Allocation with
a Wireless Multi-cast Aware Routing for Virtual Network Embedding}, booktitle={2019
16th IEEE Annual Consumer Communications & Networking Conference (CCNC2019)},
publisher={IEEE}, author={Afifi, Haitham and Karl, Holger} }'
chicago: 'Afifi, Haitham, and Holger Karl. “Power Allocation with a Wireless Multi-Cast
Aware Routing for Virtual Network Embedding.” In 2019 16th IEEE Annual Consumer
Communications & Networking Conference (CCNC2019). Las Vegas: IEEE, n.d.'
ieee: H. Afifi and H. Karl, “Power Allocation with a Wireless Multi-cast Aware Routing
for Virtual Network Embedding,” in 2019 16th IEEE Annual Consumer Communications
& Networking Conference (CCNC2019).
mla: Afifi, Haitham, and Holger Karl. “Power Allocation with a Wireless Multi-Cast
Aware Routing for Virtual Network Embedding.” 2019 16th IEEE Annual Consumer
Communications & Networking Conference (CCNC2019), IEEE.
short: 'H. Afifi, H. Karl, in: 2019 16th IEEE Annual Consumer Communications &
Networking Conference (CCNC2019), IEEE, Las Vegas, n.d.'
date_created: 2019-01-17T15:51:34Z
date_updated: 2022-01-06T07:03:22Z
ddc:
- '000'
department:
- _id: '75'
file:
- access_level: open_access
content_type: application/pdf
creator: hafifi
date_created: 2019-01-17T15:49:37Z
date_updated: 2019-01-17T15:49:37Z
file_id: '6861'
file_name: globecom.pdf
file_size: 320283
relation: main_file
file_date_updated: 2019-01-17T15:49:37Z
has_accepted_license: '1'
language:
- iso: eng
oa: '1'
place: Las Vegas
project:
- _id: '27'
name: 'Akustische Sensornetzwerke - Teilprojekt '
- _id: '27'
name: Akustische Sensornetzwerke - Teilprojekt "Verteilte akustische Signalverarbeitung
über funkbasierte Sensornetzwerke
publication: 2019 16th IEEE Annual Consumer Communications & Networking Conference
(CCNC2019)
publication_status: accepted
publisher: IEEE
status: public
title: Power Allocation with a Wireless Multi-cast Aware Routing for Virtual Network
Embedding
type: conference
user_id: '65718'
year: '2019'
...
---
_id: '6976'
abstract:
- lang: eng
text: "We investigate the maintenance of overlay networks under massive churn, i.e.\r\nnodes
joining and leaving the network. We assume an adversary that may churn a\r\nconstant
fraction $\\alpha n$ of nodes over the course of $\\mathcal{O}(\\log n)$\r\nrounds.
In particular, the adversary has an almost up-to-date information of\r\nthe network
topology as it can observe an only slightly outdated topology that\r\nis at least
$2$ rounds old. Other than that, we only have the provably minimal\r\nrestriction
that new nodes can only join the network via nodes that have taken\r\npart in
the network for at least one round.\r\n Our contributions are as follows: First,
we show that it is impossible to\r\nmaintain a connected topology if adversary
has up-to-date information about the\r\nnodes' connections. Further, we show that
our restriction concerning the join\r\nis also necessary. As our main result present
an algorithm that constructs a\r\nnew overlay- completely independent of all previous
overlays - every $2$\r\nrounds. Furthermore, each node sends and receives only
$\\mathcal{O}(\\log^3 n)$\r\nmessages each round. As part of our solution we propose
the Linearized DeBruijn\r\nSwarm (LDS), a highly churn resistant overlay, which
will be maintained by the\r\nalgorithm. However, our approaches can be transferred
to a variety of classical\r\nP2P Topologies where nodes are mapped into the $[0,1)$-interval."
author:
- first_name: Thorsten
full_name: Götte, Thorsten
id: '34727'
last_name: Götte
- first_name: Vipin Ravindran
full_name: Vijayalakshmi, Vipin Ravindran
last_name: Vijayalakshmi
- first_name: Christian
full_name: Scheideler, Christian
id: '20792'
last_name: Scheideler
citation:
ama: 'Götte T, Vijayalakshmi VR, Scheideler C. Always be Two Steps Ahead of Your
Enemy - Maintaining a Routable Overlay under Massive Churn with an Almost Up-to-date
Adversary. In: Proceedings of the 2019 IEEE 33rd International Parallel and
Distributed Processing Symposium (IPDPS ’19). IEEE.'
apa: 'Götte, T., Vijayalakshmi, V. R., & Scheideler, C. (n.d.). Always be Two
Steps Ahead of Your Enemy - Maintaining a Routable Overlay under Massive Churn
with an Almost Up-to-date Adversary. In Proceedings of the 2019 IEEE 33rd International
Parallel and Distributed Processing Symposium (IPDPS ’19). Rio de Janeiro,
Brazil: IEEE.'
bibtex: '@inproceedings{Götte_Vijayalakshmi_Scheideler, title={Always be Two Steps
Ahead of Your Enemy - Maintaining a Routable Overlay under Massive Churn with
an Almost Up-to-date Adversary}, booktitle={Proceedings of the 2019 IEEE 33rd
International Parallel and Distributed Processing Symposium (IPDPS ’19)}, publisher={IEEE},
author={Götte, Thorsten and Vijayalakshmi, Vipin Ravindran and Scheideler, Christian}
}'
chicago: Götte, Thorsten, Vipin Ravindran Vijayalakshmi, and Christian Scheideler.
“Always Be Two Steps Ahead of Your Enemy - Maintaining a Routable Overlay under
Massive Churn with an Almost Up-to-Date Adversary.” In Proceedings of the 2019
IEEE 33rd International Parallel and Distributed Processing Symposium (IPDPS
’19). IEEE, n.d.
ieee: T. Götte, V. R. Vijayalakshmi, and C. Scheideler, “Always be Two Steps Ahead
of Your Enemy - Maintaining a Routable Overlay under Massive Churn with an Almost
Up-to-date Adversary,” in Proceedings of the 2019 IEEE 33rd International Parallel
and Distributed Processing Symposium (IPDPS ’19), Rio de Janeiro, Brazil.
mla: Götte, Thorsten, et al. “Always Be Two Steps Ahead of Your Enemy - Maintaining
a Routable Overlay under Massive Churn with an Almost Up-to-Date Adversary.” Proceedings
of the 2019 IEEE 33rd International Parallel and Distributed Processing Symposium
(IPDPS ’19), IEEE.
short: 'T. Götte, V.R. Vijayalakshmi, C. Scheideler, in: Proceedings of the 2019
IEEE 33rd International Parallel and Distributed Processing Symposium (IPDPS
’19), IEEE, n.d.'
conference:
end_date: 24.05.19
location: Rio de Janeiro, Brazil
name: 2019 IEEE 33rd International Parallel and Distributed Processing Symposium
(IPDPS '19)
start_date: 20.05.19
date_created: 2019-01-24T18:53:11Z
date_updated: 2022-01-06T07:03:25Z
ddc:
- '000'
department:
- _id: '79'
file:
- access_level: closed
content_type: application/pdf
creator: thgoette
date_created: 2019-01-26T16:09:08Z
date_updated: 2019-01-26T16:09:08Z
file_id: '7007'
file_name: Always_be_Two_Steps_Ahead_of_Your_Enemy.pdf
file_size: 638020
relation: main_file
success: 1
file_date_updated: 2019-01-26T16:09:08Z
has_accepted_license: '1'
language:
- iso: eng
project:
- _id: '1'
name: SFB 901
- _id: '4'
name: SFB 901 - Project Area C
- _id: '13'
name: SFB 901 - Subproject C1
publication: Proceedings of the 2019 IEEE 33rd International Parallel and Distributed
Processing Symposium (IPDPS '19)
publication_status: accepted
publisher: IEEE
status: public
title: Always be Two Steps Ahead of Your Enemy - Maintaining a Routable Overlay under
Massive Churn with an Almost Up-to-date Adversary
type: conference
user_id: '34727'
year: '2019'
...
---
_id: '16411'
abstract:
- lang: eng
text: FPGA devices have been proving to be good candidates to accelerate applications
from different research topics. For instance, machine learning applications such
as K-Means clustering usually relies on large amount of data to be processed,
and, despite the performance offered by other architectures, FPGAs can offer better
energy efficiency. With that in mind, Intel has launched a platform that integrates
a multicore and an FPGA in the same package, enabling low latency and coherent
fine-grained data offload. In this paper, we present a parallel implementation
of the K-Means clustering algorithm, for this novel platform, using OpenCL language,
and compared it against other platforms. We found that the CPU+FPGA platform was
more energy efficient than the CPU-only approach from 70.71% to 85.92%, with Standard
and Tiny input sizes respectively, and up to 68.21% of performance improvement
was obtained with Tiny input size. Furthermore, it was up to 7.2×more energy efficient
than an Intel® Xeon Phi ™, 21.5×than a cluster of Raspberry Pi boards, and 3.8×than
the low-power MPPA-256 architecture, when the Standard input size was used.
author:
- first_name: Matheus A.
full_name: Souza, Matheus A.
last_name: Souza
- first_name: Lucas A.
full_name: Maciel, Lucas A.
last_name: Maciel
- first_name: Pedro Henrique
full_name: Penna, Pedro Henrique
last_name: Penna
- first_name: Henrique C.
full_name: Freitas, Henrique C.
last_name: Freitas
citation:
ama: 'Souza MA, Maciel LA, Penna PH, Freitas HC. Energy Efficient Parallel K-Means
Clustering for an Intel® Hybrid Multi-Chip Package. In: 2018 30th International
Symposium on Computer Architecture and High Performance Computing (SBAC-PAD).
; 2019. doi:10.1109/cahpc.2018.8645850'
apa: Souza, M. A., Maciel, L. A., Penna, P. H., & Freitas, H. C. (2019). Energy
Efficient Parallel K-Means Clustering for an Intel® Hybrid Multi-Chip Package.
In 2018 30th International Symposium on Computer Architecture and High Performance
Computing (SBAC-PAD). https://doi.org/10.1109/cahpc.2018.8645850
bibtex: '@inproceedings{Souza_Maciel_Penna_Freitas_2019, title={Energy Efficient
Parallel K-Means Clustering for an Intel® Hybrid Multi-Chip Package}, DOI={10.1109/cahpc.2018.8645850},
booktitle={2018 30th International Symposium on Computer Architecture and High
Performance Computing (SBAC-PAD)}, author={Souza, Matheus A. and Maciel, Lucas
A. and Penna, Pedro Henrique and Freitas, Henrique C.}, year={2019} }'
chicago: Souza, Matheus A., Lucas A. Maciel, Pedro Henrique Penna, and Henrique
C. Freitas. “Energy Efficient Parallel K-Means Clustering for an Intel® Hybrid
Multi-Chip Package.” In 2018 30th International Symposium on Computer Architecture
and High Performance Computing (SBAC-PAD), 2019. https://doi.org/10.1109/cahpc.2018.8645850.
ieee: M. A. Souza, L. A. Maciel, P. H. Penna, and H. C. Freitas, “Energy Efficient
Parallel K-Means Clustering for an Intel® Hybrid Multi-Chip Package,” in 2018
30th International Symposium on Computer Architecture and High Performance Computing
(SBAC-PAD), 2019.
mla: Souza, Matheus A., et al. “Energy Efficient Parallel K-Means Clustering for
an Intel® Hybrid Multi-Chip Package.” 2018 30th International Symposium on
Computer Architecture and High Performance Computing (SBAC-PAD), 2019, doi:10.1109/cahpc.2018.8645850.
short: 'M.A. Souza, L.A. Maciel, P.H. Penna, H.C. Freitas, in: 2018 30th International
Symposium on Computer Architecture and High Performance Computing (SBAC-PAD),
2019.'
date_created: 2020-04-06T09:41:41Z
date_updated: 2022-01-06T06:52:50Z
doi: 10.1109/cahpc.2018.8645850
keyword:
- pc2-harp-ressources
language:
- iso: eng
publication: 2018 30th International Symposium on Computer Architecture and High Performance
Computing (SBAC-PAD)
publication_identifier:
isbn:
- '9781538677698'
publication_status: published
status: public
title: Energy Efficient Parallel K-Means Clustering for an Intel® Hybrid Multi-Chip
Package
type: conference
user_id: '61189'
year: '2019'
...
---
_id: '16413'
abstract:
- lang: eng
text: In recent years, FPGAs have been successfully employed for the implementation
of efficient, application-specific accelerators for a wide range of machine learning
tasks. In this work, we consider probabilistic models, namely, (Mixed) Sum-Product
Networks (SPN), a deep architecture that can provide tractable inference for multivariate
distributions over mixed data-sources. We develop a fully pipelined FPGA accelerator
architecture, including a pipelined interface to external memory, for the inference
in (mixed) SPNs. To meet the precision constraints of SPNs, all computations are
conducted using double-precision floating point arithmetic. Starting from an input
description, the custom FPGA-accelerator is synthesized fully automatically by
our tool flow. To the best of our knowledge, this work is the first approach to
offload the SPN inference problem to FPGA-based accelerators. Our evaluation shows
that the SPN inference problem benefits from offloading to our pipelined FPGA
accelerator architecture.
author:
- first_name: Lukas
full_name: Sommer, Lukas
last_name: Sommer
- first_name: Julian
full_name: Oppermann, Julian
last_name: Oppermann
- first_name: Alejandro
full_name: Molina, Alejandro
last_name: Molina
- first_name: Carsten
full_name: Binnig, Carsten
last_name: Binnig
- first_name: Kristian
full_name: Kersting, Kristian
last_name: Kersting
- first_name: Andreas
full_name: Koch, Andreas
last_name: Koch
citation:
ama: 'Sommer L, Oppermann J, Molina A, Binnig C, Kersting K, Koch A. Automatic Mapping
of the Sum-Product Network Inference Problem to FPGA-Based Accelerators. In: 2018
IEEE 36th International Conference on Computer Design (ICCD). ; 2019. doi:10.1109/iccd.2018.00060'
apa: Sommer, L., Oppermann, J., Molina, A., Binnig, C., Kersting, K., & Koch,
A. (2019). Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-Based
Accelerators. In 2018 IEEE 36th International Conference on Computer Design
(ICCD). https://doi.org/10.1109/iccd.2018.00060
bibtex: '@inproceedings{Sommer_Oppermann_Molina_Binnig_Kersting_Koch_2019, title={Automatic
Mapping of the Sum-Product Network Inference Problem to FPGA-Based Accelerators},
DOI={10.1109/iccd.2018.00060},
booktitle={2018 IEEE 36th International Conference on Computer Design (ICCD)},
author={Sommer, Lukas and Oppermann, Julian and Molina, Alejandro and Binnig,
Carsten and Kersting, Kristian and Koch, Andreas}, year={2019} }'
chicago: Sommer, Lukas, Julian Oppermann, Alejandro Molina, Carsten Binnig, Kristian
Kersting, and Andreas Koch. “Automatic Mapping of the Sum-Product Network Inference
Problem to FPGA-Based Accelerators.” In 2018 IEEE 36th International Conference
on Computer Design (ICCD), 2019. https://doi.org/10.1109/iccd.2018.00060.
ieee: L. Sommer, J. Oppermann, A. Molina, C. Binnig, K. Kersting, and A. Koch, “Automatic
Mapping of the Sum-Product Network Inference Problem to FPGA-Based Accelerators,”
in 2018 IEEE 36th International Conference on Computer Design (ICCD), 2019.
mla: Sommer, Lukas, et al. “Automatic Mapping of the Sum-Product Network Inference
Problem to FPGA-Based Accelerators.” 2018 IEEE 36th International Conference
on Computer Design (ICCD), 2019, doi:10.1109/iccd.2018.00060.
short: 'L. Sommer, J. Oppermann, A. Molina, C. Binnig, K. Kersting, A. Koch, in:
2018 IEEE 36th International Conference on Computer Design (ICCD), 2019.'
date_created: 2020-04-06T10:33:58Z
date_updated: 2022-01-06T06:52:50Z
doi: 10.1109/iccd.2018.00060
keyword:
- pc2-harp-ressources
language:
- iso: eng
publication: 2018 IEEE 36th International Conference on Computer Design (ICCD)
publication_identifier:
isbn:
- '9781538684771'
publication_status: published
status: public
title: Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-Based
Accelerators
type: conference
user_id: '61189'
year: '2019'
...
---
_id: '16415'
author:
- first_name: Julian
full_name: Lienen, Julian
id: '44040'
last_name: Lienen
citation:
ama: Lienen J. Automated Feature Engineering on Time Series Data.; 2019.
apa: Lienen, J. (2019). Automated Feature Engineering on Time Series Data.
bibtex: '@book{Lienen_2019, title={Automated Feature Engineering on Time Series
Data}, author={Lienen, Julian}, year={2019} }'
chicago: Lienen, Julian. Automated Feature Engineering on Time Series Data,
2019.
ieee: J. Lienen, Automated Feature Engineering on Time Series Data. 2019.
mla: Lienen, Julian. Automated Feature Engineering on Time Series Data. 2019.
short: J. Lienen, Automated Feature Engineering on Time Series Data, 2019.
date_created: 2020-04-06T11:44:17Z
date_updated: 2022-01-06T06:52:50Z
language:
- iso: eng
status: public
title: Automated Feature Engineering on Time Series Data
type: mastersthesis
user_id: '44040'
year: '2019'
...
---
_id: '16417'
abstract:
- lang: eng
text: The performance of High-Level Synthesis (HLS) applications with irregular
data structures is limited by its imperative programming paradigm like C/C++.
In this paper, we show that constructing concurrent data structures with channels,
a programming construct derived from CSP (communicating sequential processes)
paradigm, is an effective approach to improve the performance of these applications.
We evaluate concurrent data structure for FPGA by synthesizing a K-means clustering
algorithm on the Intel HARP2 platform. A fully pipelined KMC processing element
can be synthesized from OpenCL with the help of a SPSC (single-producer-single-consumer)
queue and stack built from channels, achieving 15.2x speedup over a sequential
baseline. The number of processing element can be scaled up by leveraging a MPMC
(multiple-producer-multiple-consumer) stack with work distribution for dynamic
load balance. Evaluation shows that an additional 3.5x speedup can be achieved
when 4 processing element is instantiated. These results show that the concurrent
data structure built with channels has great potential for improving the parallelism
of HLS applications. We hope that our study will stimulate further research into
the potential of channel-based HLS.
author:
- first_name: Hui
full_name: Yan, Hui
last_name: Yan
- first_name: Zhaoshi
full_name: Li, Zhaoshi
last_name: Li
- first_name: Leibo
full_name: Liu, Leibo
last_name: Liu
- first_name: Shouyi
full_name: Yin, Shouyi
last_name: Yin
- first_name: Shaojun
full_name: Wei, Shaojun
last_name: Wei
citation:
ama: 'Yan H, Li Z, Liu L, Yin S, Wei S. Constructing Concurrent Data Structures
on FPGA with Channels. In: Proceedings of the 2019 ACM/SIGDA International
Symposium on Field-Programmable Gate Arrays. ; 2019. doi:10.1145/3289602.3293921'
apa: Yan, H., Li, Z., Liu, L., Yin, S., & Wei, S. (2019). Constructing Concurrent
Data Structures on FPGA with Channels. In Proceedings of the 2019 ACM/SIGDA
International Symposium on Field-Programmable Gate Arrays. https://doi.org/10.1145/3289602.3293921
bibtex: '@inproceedings{Yan_Li_Liu_Yin_Wei_2019, title={Constructing Concurrent
Data Structures on FPGA with Channels}, DOI={10.1145/3289602.3293921},
booktitle={Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable
Gate Arrays}, author={Yan, Hui and Li, Zhaoshi and Liu, Leibo and Yin, Shouyi
and Wei, Shaojun}, year={2019} }'
chicago: Yan, Hui, Zhaoshi Li, Leibo Liu, Shouyi Yin, and Shaojun Wei. “Constructing
Concurrent Data Structures on FPGA with Channels.” In Proceedings of the 2019
ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019.
https://doi.org/10.1145/3289602.3293921.
ieee: H. Yan, Z. Li, L. Liu, S. Yin, and S. Wei, “Constructing Concurrent Data Structures
on FPGA with Channels,” in Proceedings of the 2019 ACM/SIGDA International
Symposium on Field-Programmable Gate Arrays, 2019.
mla: Yan, Hui, et al. “Constructing Concurrent Data Structures on FPGA with Channels.”
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable
Gate Arrays, 2019, doi:10.1145/3289602.3293921.
short: 'H. Yan, Z. Li, L. Liu, S. Yin, S. Wei, in: Proceedings of the 2019 ACM/SIGDA
International Symposium on Field-Programmable Gate Arrays, 2019.'
date_created: 2020-04-06T11:53:34Z
date_updated: 2022-01-06T06:52:50Z
doi: 10.1145/3289602.3293921
keyword:
- pc2-harp-ressources
language:
- iso: eng
publication: Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable
Gate Arrays
publication_identifier:
isbn:
- '9781450361378'
publication_status: published
status: public
title: Constructing Concurrent Data Structures on FPGA with Channels
type: conference
user_id: '61189'
year: '2019'
...
---
_id: '16420'
abstract:
- lang: eng
text: ' Field-Programmable Gate Arrays (FPGAs) are widely used in the central
signal processing design of the Square Kilometer Array (SKA) as hardware accelerators.
The frequency domain acceleration search (FDAS) module is an important part of
the SKA1-MID pulsar search engine. To develop for a yet to be finalized hardware,
for cross-discipline interoperability and to achieve fast prototyping, OpenCL
as a high-level FPGA synthesis approaches employed to create the sub-modules of
FDAS. The FT convolution and the harmonic-summing plus some other minor sub-modules
are elements in the FDAS module that have been well-optimized separately before.
In this paper, we explore the design space of combining well-optimized designs,
dealing with the ensuing need to trade-off and compromise. Pipeline computing
is employed to handle multiple input arrays at high speed. The hardware target
is to employ multiple high-end FPGAs to process the combined FDAS module. The
results show interesting consequences, where the best individual solutions are
not necessarily the best solutions for the speed of a pipeline where FPGA resources
and memory bandwidth need to be shared. By proposing multiple buffering techniques
to the pipeline, the combined FDAS module can achieve up to 2[Formula: see text]
speedup over implementations without pipeline computing. We perform an extensive
experimental evaluation on multiple high-end FPGA cards hosted in a workstation
and compare to a technology comparable mid-range GPU. '
article_number: '1950008'
author:
- first_name: Haomiao
full_name: Wang, Haomiao
last_name: Wang
- first_name: Prabu
full_name: Thiagaraj, Prabu
last_name: Thiagaraj
- first_name: Oliver
full_name: Sinnen, Oliver
last_name: Sinnen
citation:
ama: Wang H, Thiagaraj P, Sinnen O. Combining Multiple Optimized FPGA-based Pulsar
Search Modules Using OpenCL. Journal of Astronomical Instrumentation. 2019.
doi:10.1142/s2251171719500089
apa: Wang, H., Thiagaraj, P., & Sinnen, O. (2019). Combining Multiple Optimized
FPGA-based Pulsar Search Modules Using OpenCL. Journal of Astronomical Instrumentation.
https://doi.org/10.1142/s2251171719500089
bibtex: '@article{Wang_Thiagaraj_Sinnen_2019, title={Combining Multiple Optimized
FPGA-based Pulsar Search Modules Using OpenCL}, DOI={10.1142/s2251171719500089},
number={1950008}, journal={Journal of Astronomical Instrumentation}, author={Wang,
Haomiao and Thiagaraj, Prabu and Sinnen, Oliver}, year={2019} }'
chicago: Wang, Haomiao, Prabu Thiagaraj, and Oliver Sinnen. “Combining Multiple
Optimized FPGA-Based Pulsar Search Modules Using OpenCL.” Journal of Astronomical
Instrumentation, 2019. https://doi.org/10.1142/s2251171719500089.
ieee: H. Wang, P. Thiagaraj, and O. Sinnen, “Combining Multiple Optimized FPGA-based
Pulsar Search Modules Using OpenCL,” Journal of Astronomical Instrumentation,
2019.
mla: Wang, Haomiao, et al. “Combining Multiple Optimized FPGA-Based Pulsar Search
Modules Using OpenCL.” Journal of Astronomical Instrumentation, 1950008,
2019, doi:10.1142/s2251171719500089.
short: H. Wang, P. Thiagaraj, O. Sinnen, Journal of Astronomical Instrumentation
(2019).
date_created: 2020-04-06T12:00:06Z
date_updated: 2022-01-06T06:52:50Z
doi: 10.1142/s2251171719500089
keyword:
- pc2-harp-ressources
language:
- iso: eng
publication: Journal of Astronomical Instrumentation
publication_identifier:
issn:
- 2251-1717
- 2251-1725
publication_status: published
status: public
title: Combining Multiple Optimized FPGA-based Pulsar Search Modules Using OpenCL
type: journal_article
user_id: '61189'
year: '2019'
...
---
_id: '16422'
abstract:
- lang: eng
text: Intel recently introduced the Heterogeneous Architecture Research
Platform, HARP. In this platform, the Central Processing Unit and a Field-Programmable
Gate Array are connected through a high-bandwidth, low-latency interconnect and
both share DRAM memory. For this platform, Open Computing Language (OpenCL), a
High-Level Synthesis (HLS) language, is made available. By making use of HLS,
a faster design cycle can be achieved compared to programming in a traditional
hardware description language. This, however, comes at the cost of having less
control over the hardware implementation. We will investigate how OpenCL can be
applied to implement a real-time guided image filter on the HARP platform. In
the first phase, the performance-critical parameters of the OpenCL programming
model are defined using several specialized benchmarks. In a second phase, the
guided image filter algorithm is implemented using the insights gained in the
first phase. Both a floating-point and a fixed-point implementation were developed
for this algorithm, based on a sliding window implementation. This resulted in
a maximum floating-point performance of 135 GFLOPS, a maximum fixed-point performance
of 430 GOPS and a throughput of HD color images at 74 frames per second.
article_number: '149'
author:
- first_name: Thomas
full_name: Faict, Thomas
last_name: Faict
- first_name: Erik H.
full_name: D’Hollander, Erik H.
last_name: D’Hollander
- first_name: Bart
full_name: Goossens, Bart
last_name: Goossens
citation:
ama: Faict T, D’Hollander EH, Goossens B. Mapping a Guided Image Filter on the HARP
Reconfigurable Architecture Using OpenCL. Algorithms. 2019. doi:10.3390/a12080149
apa: Faict, T., D’Hollander, E. H., & Goossens, B. (2019). Mapping a Guided
Image Filter on the HARP Reconfigurable Architecture Using OpenCL. Algorithms.
https://doi.org/10.3390/a12080149
bibtex: '@article{Faict_D’Hollander_Goossens_2019, title={Mapping a Guided Image
Filter on the HARP Reconfigurable Architecture Using OpenCL}, DOI={10.3390/a12080149},
number={149}, journal={Algorithms}, author={Faict, Thomas and D’Hollander, Erik
H. and Goossens, Bart}, year={2019} }'
chicago: Faict, Thomas, Erik H. D’Hollander, and Bart Goossens. “Mapping a Guided
Image Filter on the HARP Reconfigurable Architecture Using OpenCL.” Algorithms,
2019. https://doi.org/10.3390/a12080149.
ieee: T. Faict, E. H. D’Hollander, and B. Goossens, “Mapping a Guided Image Filter
on the HARP Reconfigurable Architecture Using OpenCL,” Algorithms, 2019.
mla: Faict, Thomas, et al. “Mapping a Guided Image Filter on the HARP Reconfigurable
Architecture Using OpenCL.” Algorithms, 149, 2019, doi:10.3390/a12080149.
short: T. Faict, E.H. D’Hollander, B. Goossens, Algorithms (2019).
date_created: 2020-04-06T12:08:24Z
date_updated: 2022-01-06T06:52:50Z
doi: 10.3390/a12080149
keyword:
- pc2-harp-ressources
language:
- iso: eng
publication: Algorithms
publication_identifier:
issn:
- 1999-4893
publication_status: published
status: public
title: Mapping a Guided Image Filter on the HARP Reconfigurable Architecture Using
OpenCL
type: journal_article
user_id: '61189'
year: '2019'
...
---
_id: '16423'
abstract:
- lang: eng
text: Heterogeneous computing that exploits simultaneous co-processing with different
device types has been shown to be effective at both increasing performance and
reducing energy consumption. In this paper, we extend a scheduling framework encapsulated
in a high-level C++ template and previously developed for heterogeneous chips
comprising CPU and GPU cores, to new high-performance platforms for the data center,
which include a cache coherent FPGA fabric and many-core CPU resources. Our goal
is to evaluate the suitability of our framework with these new FPGA-based platforms,
identifying performance benefits and limitations.We target the state-of-the-art
HARP processor that includes 14 high-end Xeon classes tightly coupled to a FPGA
device located in the same package. We select eight benchmarks from the high-performance
computing domain that have been ported and optimized for this heterogeneous platform.
The results show that a dynamic and adaptive scheduler that exploits simultaneous
processing among the devices can improve performance up to a factor of 8 × compared
to the best alternative solutions that only use the CPU cores or the FPGA fabric.
Moreover, our proposal achieves up to 15% and 37% of improvement compared to the
best heterogeneous solutions found with a dynamic and static schedulers, respectively.
author:
- first_name: Andrés
full_name: Rodríguez, Andrés
last_name: Rodríguez
- first_name: Angeles
full_name: Navarro, Angeles
last_name: Navarro
- first_name: Rafael
full_name: Asenjo, Rafael
last_name: Asenjo
- first_name: Francisco
full_name: Corbera, Francisco
last_name: Corbera
- first_name: Rubén
full_name: Gran, Rubén
last_name: Gran
- first_name: Darío
full_name: Suárez, Darío
last_name: Suárez
- first_name: Jose
full_name: Nunez-Yanez, Jose
last_name: Nunez-Yanez
citation:
ama: Rodríguez A, Navarro A, Asenjo R, et al. Parallel multiprocessing and scheduling
on the heterogeneous Xeon+FPGA platform. The Journal of Supercomputing.
2019. doi:10.1007/s11227-019-02935-1
apa: Rodríguez, A., Navarro, A., Asenjo, R., Corbera, F., Gran, R., Suárez, D.,
& Nunez-Yanez, J. (2019). Parallel multiprocessing and scheduling on the heterogeneous
Xeon+FPGA platform. The Journal of Supercomputing. https://doi.org/10.1007/s11227-019-02935-1
bibtex: '@article{Rodríguez_Navarro_Asenjo_Corbera_Gran_Suárez_Nunez-Yanez_2019,
title={Parallel multiprocessing and scheduling on the heterogeneous Xeon+FPGA
platform}, DOI={10.1007/s11227-019-02935-1},
journal={The Journal of Supercomputing}, author={Rodríguez, Andrés and Navarro,
Angeles and Asenjo, Rafael and Corbera, Francisco and Gran, Rubén and Suárez,
Darío and Nunez-Yanez, Jose}, year={2019} }'
chicago: Rodríguez, Andrés, Angeles Navarro, Rafael Asenjo, Francisco Corbera, Rubén
Gran, Darío Suárez, and Jose Nunez-Yanez. “Parallel Multiprocessing and Scheduling
on the Heterogeneous Xeon+FPGA Platform.” The Journal of Supercomputing,
2019. https://doi.org/10.1007/s11227-019-02935-1.
ieee: A. Rodríguez et al., “Parallel multiprocessing and scheduling on the
heterogeneous Xeon+FPGA platform,” The Journal of Supercomputing, 2019.
mla: Rodríguez, Andrés, et al. “Parallel Multiprocessing and Scheduling on the Heterogeneous
Xeon+FPGA Platform.” The Journal of Supercomputing, 2019, doi:10.1007/s11227-019-02935-1.
short: A. Rodríguez, A. Navarro, R. Asenjo, F. Corbera, R. Gran, D. Suárez, J. Nunez-Yanez,
The Journal of Supercomputing (2019).
date_created: 2020-04-06T12:09:25Z
date_updated: 2022-01-06T06:52:50Z
doi: 10.1007/s11227-019-02935-1
keyword:
- pc2-harp-ressources
language:
- iso: eng
publication: The Journal of Supercomputing
publication_identifier:
issn:
- 0920-8542
- 1573-0484
publication_status: published
status: public
title: Parallel multiprocessing and scheduling on the heterogeneous Xeon+FPGA platform
type: journal_article
user_id: '61189'
year: '2019'
...
---
_id: '16427'
abstract:
- lang: eng
text: "Transactional Memory (TM) has been considered as a promising alternative
to existing synchronization operations, which are often the largest stumbling
block to unleashing parallelism of applications. Efficient implementations of
TM, however, are challenging due to the tension between lowering performance overhead
and avoiding unnecessary aborts.\r\n\r\nIn this paper, we present Reachability-based
Optimistic Concurrency Control for Transactional Memory (ROCoCoTM), a novel scheme
which offloads concurrency control (CC) algorithms, the central building blocks
of TM systems, to reconfigurable hardware. To reduce the abort rate, an innovative
formalization of mainstream CC algorithms is developed to reveal a common restriction
that leads to unnecessary aborts. This restriction is resolved by the ROCoCo algorithm
with a centralized validation phase, which can be efficiently pipelined in hardware.
Thanks to a high-performance offloading engine implemented in reconfigurable hardware,
ROCoCo algorithm results in decreased abort rates and reduced performance overhead.
The whole system is implemented on Intel's HARP2 platform and evaluated with the
STAMP benchmark suite. Experiments show 1.55x and 8.05x geomean speedup over TinySTM
and an HTM based on Intel TSX, respectively. Given the fast-growing deployment
of commodity CPU-FPGA platforms, ROCoCoTM paves the way for software programmers
to exploit heterogeneous computing resources with a high-level transactional abstraction
to effectively extract the parallelism in modern applications."
author:
- first_name: Zhaoshi
full_name: Li, Zhaoshi
last_name: Li
- first_name: Leibo
full_name: Liu, Leibo
last_name: Liu
- first_name: Yangdong
full_name: Deng, Yangdong
last_name: Deng
- first_name: Jiawei
full_name: Wang, Jiawei
last_name: Wang
- first_name: Zhiwei
full_name: Liu, Zhiwei
last_name: Liu
- first_name: Shouyi
full_name: Yin, Shouyi
last_name: Yin
- first_name: Shaojun
full_name: Wei, Shaojun
last_name: Wei
citation:
ama: 'Li Z, Liu L, Deng Y, et al. FPGA-Accelerated Optimistic Concurrency Control
for Transactional Memory. In: Proceedings of the 52nd Annual IEEE/ACM International
Symposium on Microarchitecture. ; 2019. doi:10.1145/3352460.3358270'
apa: Li, Z., Liu, L., Deng, Y., Wang, J., Liu, Z., Yin, S., & Wei, S. (2019).
FPGA-Accelerated Optimistic Concurrency Control for Transactional Memory. In Proceedings
of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture.
https://doi.org/10.1145/3352460.3358270
bibtex: '@inproceedings{Li_Liu_Deng_Wang_Liu_Yin_Wei_2019, title={FPGA-Accelerated
Optimistic Concurrency Control for Transactional Memory}, DOI={10.1145/3352460.3358270},
booktitle={Proceedings of the 52nd Annual IEEE/ACM International Symposium on
Microarchitecture}, author={Li, Zhaoshi and Liu, Leibo and Deng, Yangdong and
Wang, Jiawei and Liu, Zhiwei and Yin, Shouyi and Wei, Shaojun}, year={2019} }'
chicago: Li, Zhaoshi, Leibo Liu, Yangdong Deng, Jiawei Wang, Zhiwei Liu, Shouyi
Yin, and Shaojun Wei. “FPGA-Accelerated Optimistic Concurrency Control for Transactional
Memory.” In Proceedings of the 52nd Annual IEEE/ACM International Symposium
on Microarchitecture, 2019. https://doi.org/10.1145/3352460.3358270.
ieee: Z. Li et al., “FPGA-Accelerated Optimistic Concurrency Control for
Transactional Memory,” in Proceedings of the 52nd Annual IEEE/ACM International
Symposium on Microarchitecture, 2019.
mla: Li, Zhaoshi, et al. “FPGA-Accelerated Optimistic Concurrency Control for Transactional
Memory.” Proceedings of the 52nd Annual IEEE/ACM International Symposium on
Microarchitecture, 2019, doi:10.1145/3352460.3358270.
short: 'Z. Li, L. Liu, Y. Deng, J. Wang, Z. Liu, S. Yin, S. Wei, in: Proceedings
of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019.'
date_created: 2020-04-06T12:49:40Z
date_updated: 2022-01-06T06:52:50Z
doi: 10.1145/3352460.3358270
keyword:
- pc2-harp-ressources
language:
- iso: eng
publication: Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture
publication_identifier:
isbn:
- '9781450369381'
publication_status: published
status: public
title: FPGA-Accelerated Optimistic Concurrency Control for Transactional Memory
type: conference
user_id: '61189'
year: '2019'
...
---
_id: '16433'
author:
- first_name: Philipp
full_name: Rehlaender, Philipp
id: '69469'
last_name: Rehlaender
- first_name: Tobias
full_name: Grote, Tobias
last_name: Grote
- first_name: Sergey
full_name: Tikhonov, Sergey
last_name: Tikhonov
- first_name: Hugues
full_name: Niejende, Hugues
last_name: Niejende
- first_name: Frank
full_name: Schafmeister, Frank
last_name: Schafmeister
- first_name: Joachim
full_name: Bocker, Joachim
last_name: Bocker
- first_name: Peter
full_name: Thiemann, Peter
last_name: Thiemann
citation:
ama: 'Rehlaender P, Grote T, Tikhonov S, et al. A PCB Integrated Winding Using a
Litz Structure for a Wireless Charging Coil. In: 2019 21st European Conference
on Power Electronics and Applications (EPE ’19 ECCE Europe). ; 2019. doi:10.23919/epe.2019.8914900'
apa: Rehlaender, P., Grote, T., Tikhonov, S., Niejende, H., Schafmeister, F., Bocker,
J., & Thiemann, P. (2019). A PCB Integrated Winding Using a Litz Structure
for a Wireless Charging Coil. In 2019 21st European Conference on Power Electronics
and Applications (EPE ’19 ECCE Europe). https://doi.org/10.23919/epe.2019.8914900
bibtex: '@inproceedings{Rehlaender_Grote_Tikhonov_Niejende_Schafmeister_Bocker_Thiemann_2019,
title={A PCB Integrated Winding Using a Litz Structure for a Wireless Charging
Coil}, DOI={10.23919/epe.2019.8914900},
booktitle={2019 21st European Conference on Power Electronics and Applications
(EPE ’19 ECCE Europe)}, author={Rehlaender, Philipp and Grote, Tobias and Tikhonov,
Sergey and Niejende, Hugues and Schafmeister, Frank and Bocker, Joachim and Thiemann,
Peter}, year={2019} }'
chicago: Rehlaender, Philipp, Tobias Grote, Sergey Tikhonov, Hugues Niejende, Frank
Schafmeister, Joachim Bocker, and Peter Thiemann. “A PCB Integrated Winding Using
a Litz Structure for a Wireless Charging Coil.” In 2019 21st European Conference
on Power Electronics and Applications (EPE ’19 ECCE Europe), 2019. https://doi.org/10.23919/epe.2019.8914900.
ieee: P. Rehlaender et al., “A PCB Integrated Winding Using a Litz Structure
for a Wireless Charging Coil,” in 2019 21st European Conference on Power Electronics
and Applications (EPE ’19 ECCE Europe), 2019.
mla: Rehlaender, Philipp, et al. “A PCB Integrated Winding Using a Litz Structure
for a Wireless Charging Coil.” 2019 21st European Conference on Power Electronics
and Applications (EPE ’19 ECCE Europe), 2019, doi:10.23919/epe.2019.8914900.
short: 'P. Rehlaender, T. Grote, S. Tikhonov, H. Niejende, F. Schafmeister, J. Bocker,
P. Thiemann, in: 2019 21st European Conference on Power Electronics and Applications
(EPE ’19 ECCE Europe), 2019.'
date_created: 2020-04-06T14:57:01Z
date_updated: 2022-01-06T06:52:50Z
doi: 10.23919/epe.2019.8914900
language:
- iso: eng
publication: 2019 21st European Conference on Power Electronics and Applications (EPE
'19 ECCE Europe)
publication_identifier:
isbn:
- '9789075815313'
publication_status: published
status: public
title: A PCB Integrated Winding Using a Litz Structure for a Wireless Charging Coil
type: conference
user_id: '69469'
year: '2019'
...
---
_id: '16438'
author:
- first_name: Philipp
full_name: Rehlaender, Philipp
id: '69469'
last_name: Rehlaender
- first_name: Frank
full_name: Schafmeister, Frank
last_name: Schafmeister
- first_name: Joachim
full_name: Bocker, Joachim
last_name: Bocker
- first_name: Tobias
full_name: Grote, Tobias
last_name: Grote
citation:
ama: 'Rehlaender P, Schafmeister F, Bocker J, Grote T. Analytical Topology Comparison
for a Single Stage On-Board EV-Battery Converter. In: 2019 IEEE 28th International
Symposium on Industrial Electronics (ISIE). ; 2019. doi:10.1109/isie.2019.8781222'
apa: Rehlaender, P., Schafmeister, F., Bocker, J., & Grote, T. (2019). Analytical
Topology Comparison for a Single Stage On-Board EV-Battery Converter. In 2019
IEEE 28th International Symposium on Industrial Electronics (ISIE). https://doi.org/10.1109/isie.2019.8781222
bibtex: '@inproceedings{Rehlaender_Schafmeister_Bocker_Grote_2019, title={Analytical
Topology Comparison for a Single Stage On-Board EV-Battery Converter}, DOI={10.1109/isie.2019.8781222},
booktitle={2019 IEEE 28th International Symposium on Industrial Electronics (ISIE)},
author={Rehlaender, Philipp and Schafmeister, Frank and Bocker, Joachim and Grote,
Tobias}, year={2019} }'
chicago: Rehlaender, Philipp, Frank Schafmeister, Joachim Bocker, and Tobias Grote.
“Analytical Topology Comparison for a Single Stage On-Board EV-Battery Converter.”
In 2019 IEEE 28th International Symposium on Industrial Electronics (ISIE),
2019. https://doi.org/10.1109/isie.2019.8781222.
ieee: P. Rehlaender, F. Schafmeister, J. Bocker, and T. Grote, “Analytical Topology
Comparison for a Single Stage On-Board EV-Battery Converter,” in 2019 IEEE
28th International Symposium on Industrial Electronics (ISIE), 2019.
mla: Rehlaender, Philipp, et al. “Analytical Topology Comparison for a Single Stage
On-Board EV-Battery Converter.” 2019 IEEE 28th International Symposium on Industrial
Electronics (ISIE), 2019, doi:10.1109/isie.2019.8781222.
short: 'P. Rehlaender, F. Schafmeister, J. Bocker, T. Grote, in: 2019 IEEE 28th
International Symposium on Industrial Electronics (ISIE), 2019.'
date_created: 2020-04-06T14:58:32Z
date_updated: 2022-01-06T06:52:50Z
doi: 10.1109/isie.2019.8781222
language:
- iso: eng
publication: 2019 IEEE 28th International Symposium on Industrial Electronics (ISIE)
publication_identifier:
isbn:
- '9781728136660'
publication_status: published
status: public
title: Analytical Topology Comparison for a Single Stage On-Board EV-Battery Converter
type: conference
user_id: '69469'
year: '2019'
...
---
_id: '16443'
author:
- first_name: Philipp
full_name: Rehlaender, Philipp
id: '69469'
last_name: Rehlaender
- first_name: Maik
full_name: Schroeer, Maik
last_name: Schroeer
- first_name: Gavneet
full_name: Chadha, Gavneet
last_name: Chadha
- first_name: Andreas
full_name: Schwung, Andreas
last_name: Schwung
citation:
ama: 'Rehlaender P, Schroeer M, Chadha G, Schwung A. Traffic Sign Detection Using
R-CNN. In: Proceedings of the International Neural Networks Society. Cham;
2019. doi:10.1007/978-3-030-16841-4_24'
apa: Rehlaender, P., Schroeer, M., Chadha, G., & Schwung, A. (2019). Traffic
Sign Detection Using R-CNN. In Proceedings of the International Neural Networks
Society. Cham. https://doi.org/10.1007/978-3-030-16841-4_24
bibtex: '@inbook{Rehlaender_Schroeer_Chadha_Schwung_2019, place={Cham}, title={Traffic
Sign Detection Using R-CNN}, DOI={10.1007/978-3-030-16841-4_24},
booktitle={Proceedings of the International Neural Networks Society}, author={Rehlaender,
Philipp and Schroeer, Maik and Chadha, Gavneet and Schwung, Andreas}, year={2019}
}'
chicago: Rehlaender, Philipp, Maik Schroeer, Gavneet Chadha, and Andreas Schwung.
“Traffic Sign Detection Using R-CNN.” In Proceedings of the International Neural
Networks Society. Cham, 2019. https://doi.org/10.1007/978-3-030-16841-4_24.
ieee: P. Rehlaender, M. Schroeer, G. Chadha, and A. Schwung, “Traffic Sign Detection
Using R-CNN,” in Proceedings of the International Neural Networks Society,
Cham, 2019.
mla: Rehlaender, Philipp, et al. “Traffic Sign Detection Using R-CNN.” Proceedings
of the International Neural Networks Society, 2019, doi:10.1007/978-3-030-16841-4_24.
short: 'P. Rehlaender, M. Schroeer, G. Chadha, A. Schwung, in: Proceedings of the
International Neural Networks Society, Cham, 2019.'
date_created: 2020-04-06T15:21:15Z
date_updated: 2022-01-06T06:52:50Z
doi: 10.1007/978-3-030-16841-4_24
extern: '1'
language:
- iso: eng
place: Cham
publication: Proceedings of the International Neural Networks Society
publication_identifier:
isbn:
- '9783030168407'
- '9783030168414'
issn:
- 2661-8141
- 2661-815X
publication_status: published
status: public
title: Traffic Sign Detection Using R-CNN
type: book_chapter
user_id: '69469'
year: '2019'
...
---
_id: '16709'
author:
- first_name: Tuhin
full_name: Sahai, Tuhin
last_name: Sahai
- first_name: Adrian
full_name: Ziessler, Adrian
last_name: Ziessler
- first_name: Stefan
full_name: Klus, Stefan
last_name: Klus
- first_name: Michael
full_name: Dellnitz, Michael
last_name: Dellnitz
citation:
ama: Sahai T, Ziessler A, Klus S, Dellnitz M. Continuous relaxations for the traveling
salesman problem. Nonlinear Dynamics. 2019. doi:10.1007/s11071-019-05092-5
apa: Sahai, T., Ziessler, A., Klus, S., & Dellnitz, M. (2019). Continuous relaxations
for the traveling salesman problem. Nonlinear Dynamics. https://doi.org/10.1007/s11071-019-05092-5
bibtex: '@article{Sahai_Ziessler_Klus_Dellnitz_2019, title={Continuous relaxations
for the traveling salesman problem}, DOI={10.1007/s11071-019-05092-5},
journal={Nonlinear Dynamics}, author={Sahai, Tuhin and Ziessler, Adrian and Klus,
Stefan and Dellnitz, Michael}, year={2019} }'
chicago: Sahai, Tuhin, Adrian Ziessler, Stefan Klus, and Michael Dellnitz. “Continuous
Relaxations for the Traveling Salesman Problem.” Nonlinear Dynamics, 2019.
https://doi.org/10.1007/s11071-019-05092-5.
ieee: T. Sahai, A. Ziessler, S. Klus, and M. Dellnitz, “Continuous relaxations for
the traveling salesman problem,” Nonlinear Dynamics, 2019.
mla: Sahai, Tuhin, et al. “Continuous Relaxations for the Traveling Salesman Problem.”
Nonlinear Dynamics, 2019, doi:10.1007/s11071-019-05092-5.
short: T. Sahai, A. Ziessler, S. Klus, M. Dellnitz, Nonlinear Dynamics (2019).
date_created: 2020-04-16T14:05:04Z
date_updated: 2022-01-06T06:52:55Z
department:
- _id: '101'
doi: 10.1007/s11071-019-05092-5
language:
- iso: eng
publication: Nonlinear Dynamics
publication_identifier:
issn:
- 0924-090X
- 1573-269X
publication_status: published
status: public
title: Continuous relaxations for the traveling salesman problem
type: journal_article
user_id: '47427'
year: '2019'
...
---
_id: '16793'
author:
- first_name: Florian
full_name: Pfeifer, Florian
id: '22717'
last_name: Pfeifer
- first_name: André
full_name: Dietrich, André
last_name: Dietrich
- first_name: Thorsten
full_name: Marten, Thorsten
id: '338'
last_name: Marten
- first_name: Thomas
full_name: Tröster, Thomas
id: '553'
last_name: Tröster
- first_name: Bernard
full_name: Nacke, Bernard
last_name: Nacke
citation:
ama: 'Pfeifer F, Dietrich A, Marten T, Tröster T, Nacke B. Investigation on Inductive
Heating of Sheet Metal for an Industrial Hot Stamping Process. In: Proceedings
of 7th International Conference on Hot Sheet Metal Forming of High-Performance
Steel. ; 2019:585-593.'
apa: Pfeifer, F., Dietrich, A., Marten, T., Tröster, T., & Nacke, B. (2019).
Investigation on Inductive Heating of Sheet Metal for an Industrial Hot Stamping
Process. In Proceedings of 7th International Conference on Hot Sheet Metal
Forming of High-Performance Steel (pp. 585–593). Luleå.
bibtex: '@inproceedings{Pfeifer_Dietrich_Marten_Tröster_Nacke_2019, title={Investigation
on Inductive Heating of Sheet Metal for an Industrial Hot Stamping Process}, booktitle={Proceedings
of 7th International Conference on Hot Sheet Metal Forming of High-Performance
Steel}, author={Pfeifer, Florian and Dietrich, André and Marten, Thorsten and
Tröster, Thomas and Nacke, Bernard}, year={2019}, pages={585–593} }'
chicago: Pfeifer, Florian, André Dietrich, Thorsten Marten, Thomas Tröster, and
Bernard Nacke. “Investigation on Inductive Heating of Sheet Metal for an Industrial
Hot Stamping Process.” In Proceedings of 7th International Conference on Hot
Sheet Metal Forming of High-Performance Steel, 585–93, 2019.
ieee: F. Pfeifer, A. Dietrich, T. Marten, T. Tröster, and B. Nacke, “Investigation
on Inductive Heating of Sheet Metal for an Industrial Hot Stamping Process,” in
Proceedings of 7th International Conference on Hot Sheet Metal Forming of High-Performance
Steel, Luleå, 2019, pp. 585–593.
mla: Pfeifer, Florian, et al. “Investigation on Inductive Heating of Sheet Metal
for an Industrial Hot Stamping Process.” Proceedings of 7th International Conference
on Hot Sheet Metal Forming of High-Performance Steel, 2019, pp. 585–93.
short: 'F. Pfeifer, A. Dietrich, T. Marten, T. Tröster, B. Nacke, in: Proceedings
of 7th International Conference on Hot Sheet Metal Forming of High-Performance
Steel, 2019, pp. 585–593.'
conference:
end_date: 2019-06-05
location: Luleå
name: 7th International Conference on Hot Sheet Metal Forming of High-Performance
Steel
start_date: 2091-06-02
date_created: 2020-04-21T13:39:45Z
date_updated: 2022-01-06T06:52:56Z
department:
- _id: '149'
language:
- iso: eng
page: 585-593
publication: Proceedings of 7th International Conference on Hot Sheet Metal Forming
of High-Performance Steel
publication_identifier:
isbn:
- 978-3-95735-104-3
status: public
title: Investigation on Inductive Heating of Sheet Metal for an Industrial Hot Stamping
Process
type: conference
user_id: '22717'
year: '2019'
...
---
_id: '16794'
author:
- first_name: Jan André
full_name: Striewe, Jan André
id: '29413'
last_name: Striewe
- first_name: Robert
full_name: Thomas, Robert
last_name: Thomas
- first_name: Fabian
full_name: Fischer, Fabian
last_name: Fischer
- first_name: Timo
full_name: Wiens, Timo
last_name: Wiens
- first_name: Thomas
full_name: Tröster, Thomas
id: '553'
last_name: Tröster
citation:
ama: 'Striewe JA, Thomas R, Fischer F, Wiens T, Tröster T. Energieabsorptions- und
Versagensverhalten eines automobilen Seitenschwellers mit lokaler Verstärkung
aus kohlenstofffaserverstärktem Kunststoff nach Alterung. In: Sankt Augustin:
DGM-Inventum GmbH ; 2019.'
apa: 'Striewe, J. A., Thomas, R., Fischer, F., Wiens, T., & Tröster, T. (2019).
Energieabsorptions- und Versagensverhalten eines automobilen Seitenschwellers
mit lokaler Verstärkung aus kohlenstofffaserverstärktem Kunststoff nach Alterung.
Presented at the Tagung Werkstoffprüfung 2019, Sankt Augustin: DGM-Inventum GmbH
.'
bibtex: '@inproceedings{Striewe_Thomas_Fischer_Wiens_Tröster_2019, place={Sankt
Augustin}, title={Energieabsorptions- und Versagensverhalten eines automobilen
Seitenschwellers mit lokaler Verstärkung aus kohlenstofffaserverstärktem Kunststoff
nach Alterung}, publisher={DGM-Inventum GmbH }, author={Striewe, Jan André and
Thomas, Robert and Fischer, Fabian and Wiens, Timo and Tröster, Thomas}, year={2019}
}'
chicago: 'Striewe, Jan André, Robert Thomas, Fabian Fischer, Timo Wiens, and Thomas
Tröster. “Energieabsorptions- Und Versagensverhalten Eines Automobilen Seitenschwellers
Mit Lokaler Verstärkung Aus Kohlenstofffaserverstärktem Kunststoff Nach Alterung.”
Sankt Augustin: DGM-Inventum GmbH , 2019.'
ieee: J. A. Striewe, R. Thomas, F. Fischer, T. Wiens, and T. Tröster, “Energieabsorptions-
und Versagensverhalten eines automobilen Seitenschwellers mit lokaler Verstärkung
aus kohlenstofffaserverstärktem Kunststoff nach Alterung,” presented at the Tagung
Werkstoffprüfung 2019, Neu-Ulm, 2019.
mla: Striewe, Jan André, et al. Energieabsorptions- Und Versagensverhalten Eines
Automobilen Seitenschwellers Mit Lokaler Verstärkung Aus Kohlenstofffaserverstärktem
Kunststoff Nach Alterung. DGM-Inventum GmbH , 2019.
short: 'J.A. Striewe, R. Thomas, F. Fischer, T. Wiens, T. Tröster, in: DGM-Inventum
GmbH , Sankt Augustin, 2019.'
conference:
end_date: 04.12.2019
location: Neu-Ulm
name: Tagung Werkstoffprüfung 2019
start_date: 03.12.2019
date_created: 2020-04-22T06:43:46Z
date_updated: 2022-01-06T06:52:56Z
department:
- _id: '9'
- _id: '321'
- _id: '149'
- _id: '9'
language:
- iso: eng
place: Sankt Augustin
publisher: 'DGM-Inventum GmbH '
status: public
title: Energieabsorptions- und Versagensverhalten eines automobilen Seitenschwellers
mit lokaler Verstärkung aus kohlenstofffaserverstärktem Kunststoff nach Alterung
type: conference
user_id: '29413'
year: '2019'
...
---
_id: '16825'
author:
- first_name: Dominik
full_name: Ahlers, Dominik
id: '11207'
last_name: Ahlers
- first_name: Thomas
full_name: Tröster, Thomas
id: '553'
last_name: Tröster
citation:
ama: 'Ahlers D, Tröster T. Performance Parameters and HIP Routes for Additively
Manufactured Titanium Alloy Ti6Al4V. Maastricht: EuroPM; 2019.'
apa: 'Ahlers, D., & Tröster, T. (2019). Performance Parameters and HIP Routes
for additively manufactured titanium alloy Ti6Al4V. Maastricht: EuroPM.'
bibtex: '@book{Ahlers_Tröster_2019, place={Maastricht}, series={EuroPM 2019 Congress
& Exhibition – SIS: Optimising the Properties of AM Parts using Hot Isostatic
Pressing}, title={Performance Parameters and HIP Routes for additively manufactured
titanium alloy Ti6Al4V}, publisher={EuroPM}, author={Ahlers, Dominik and Tröster,
Thomas}, year={2019}, collection={EuroPM 2019 Congress & Exhibition – SIS:
Optimising the Properties of AM Parts using Hot Isostatic Pressing} }'
chicago: 'Ahlers, Dominik, and Thomas Tröster. Performance Parameters and HIP
Routes for Additively Manufactured Titanium Alloy Ti6Al4V. EuroPM 2019 Congress
& Exhibition – SIS: Optimising the Properties of AM Parts Using Hot Isostatic
Pressing. Maastricht: EuroPM, 2019.'
ieee: 'D. Ahlers and T. Tröster, Performance Parameters and HIP Routes for additively
manufactured titanium alloy Ti6Al4V. Maastricht: EuroPM, 2019.'
mla: Ahlers, Dominik, and Thomas Tröster. Performance Parameters and HIP Routes
for Additively Manufactured Titanium Alloy Ti6Al4V. EuroPM, 2019.
short: D. Ahlers, T. Tröster, Performance Parameters and HIP Routes for Additively
Manufactured Titanium Alloy Ti6Al4V, EuroPM, Maastricht, 2019.
date_created: 2020-04-22T13:01:09Z
date_updated: 2022-01-06T06:52:57Z
department:
- _id: '9'
- _id: '321'
- _id: '149'
- _id: '219'
language:
- iso: eng
place: Maastricht
publisher: EuroPM
series_title: 'EuroPM 2019 Congress & Exhibition – SIS: Optimising the Properties
of AM Parts using Hot Isostatic Pressing'
status: public
title: Performance Parameters and HIP Routes for additively manufactured titanium
alloy Ti6Al4V
type: misc
user_id: '11207'
year: '2019'
...
---
_id: '16826'
author:
- first_name: Alan Adam
full_name: Camberg, Alan Adam
id: '60544'
last_name: Camberg
- first_name: Christian
full_name: Hielscher, Christian
last_name: Hielscher
citation:
ama: 'Camberg AA, Hielscher C. A holistic approach to the lightweight design of
tailored structural components using the example of a hybrid A-pillar. In: Aachen
Body Engineering Days 2019. ; 2019.'
apa: Camberg, A. A., & Hielscher, C. (2019). A holistic approach to the lightweight
design of tailored structural components using the example of a hybrid A-pillar.
In Aachen Body Engineering Days 2019. Aachen.
bibtex: '@inproceedings{Camberg_Hielscher_2019, title={A holistic approach to the
lightweight design of tailored structural components using the example of a hybrid
A-pillar}, booktitle={Aachen Body Engineering Days 2019}, author={Camberg, Alan
Adam and Hielscher, Christian}, year={2019} }'
chicago: Camberg, Alan Adam, and Christian Hielscher. “A Holistic Approach to the
Lightweight Design of Tailored Structural Components Using the Example of a Hybrid
A-Pillar.” In Aachen Body Engineering Days 2019, 2019.
ieee: A. A. Camberg and C. Hielscher, “A holistic approach to the lightweight design
of tailored structural components using the example of a hybrid A-pillar,” in
Aachen Body Engineering Days 2019, Aachen, 2019.
mla: Camberg, Alan Adam, and Christian Hielscher. “A Holistic Approach to the Lightweight
Design of Tailored Structural Components Using the Example of a Hybrid A-Pillar.”
Aachen Body Engineering Days 2019, 2019.
short: 'A.A. Camberg, C. Hielscher, in: Aachen Body Engineering Days 2019, 2019.'
conference:
end_date: 2019-09-18
location: Aachen
name: Aachen Body Engineering Days (Aachener Karosserietage)
start_date: 2019-09-17
date_created: 2020-04-22T13:55:57Z
date_updated: 2022-01-06T06:52:57Z
department:
- _id: '9'
- _id: '321'
- _id: '149'
language:
- iso: eng
popular_science: '1'
project:
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: Aachen Body Engineering Days 2019
status: public
title: A holistic approach to the lightweight design of tailored structural components
using the example of a hybrid A-pillar
type: conference
user_id: '60544'
year: '2019'
...