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Zusammenhänge zwischen der generischen Unterrichtsplanungsfähigkeit und der Reflexionskompetenz angehender Lehrkräfte.","user_id":"28542"},{"_id":"46269","date_updated":"2023-08-02T11:30:23Z","conference":{"location":"Nürnberg","start_date":"2023-05-09","name":"PCIM Europe 2023","end_date":"2023-05-11"},"citation":{"chicago":"Urbaneck, Daniel, Frank Schafmeister, and Joachim Böcker. “Advanced Synchronous Rectification for an IGBT-Based ZCS LLC Converter with High Output Currents for a 2 KW Automotive DC-DC Stage.” In PCIM Europe 2023, 2023.","apa":"Urbaneck, D., Schafmeister, F., & Böcker, J. (2023). Advanced Synchronous Rectification for an IGBT-Based ZCS LLC Converter with High Output Currents for a 2 kW Automotive DC-DC Stage. PCIM Europe 2023. PCIM Europe 2023, Nürnberg.","short":"D. Urbaneck, F. Schafmeister, J. Böcker, in: PCIM Europe 2023, 2023.","ama":"Urbaneck D, Schafmeister F, Böcker J. Advanced Synchronous Rectification for an IGBT-Based ZCS LLC Converter with High Output Currents for a 2 kW Automotive DC-DC Stage. In: PCIM Europe 2023. ; 2023.","mla":"Urbaneck, Daniel, et al. “Advanced Synchronous Rectification for an IGBT-Based ZCS LLC Converter with High Output Currents for a 2 KW Automotive DC-DC Stage.” PCIM Europe 2023, 2023.","bibtex":"@inproceedings{Urbaneck_Schafmeister_Böcker_2023, title={Advanced Synchronous Rectification for an IGBT-Based ZCS LLC Converter with High Output Currents for a 2 kW Automotive DC-DC Stage}, booktitle={PCIM Europe 2023}, author={Urbaneck, Daniel and Schafmeister, Frank and Böcker, Joachim}, year={2023} }","ieee":"D. Urbaneck, F. Schafmeister, and J. Böcker, “Advanced Synchronous Rectification for an IGBT-Based ZCS LLC Converter with High Output Currents for a 2 kW Automotive DC-DC Stage,” presented at the PCIM Europe 2023, Nürnberg, 2023."},"year":"2023","type":"conference","language":[{"iso":"eng"}],"main_file_link":[{"url":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10173337"}],"title":"Advanced Synchronous Rectification for an IGBT-Based ZCS LLC Converter with High Output Currents for a 2 kW Automotive DC-DC Stage","user_id":"60223","abstract":[{"lang":"eng","text":"State-of-the-art LLC resonant converters use MOSFETs in their inverter stage, which allows high switching frequencies and thus the use of compact magnetic components. The large parasitic output capacitance and the poor reverse-recovery behaviour of the inherent body diode of high-voltage (600 V) silicon MOSFETs require soft switching, i.e. zero-voltage switching (ZVS). Otherwise, the high turn-on switching losses would lead to excessive heating and ultimately to the destruction of the switch. Therefore, MOSFET-based LLC converters are operated in the so-called inductive region only, which enables ZVS. The use of robust and cost-effective IGBTs instead of MOSFETs is particularly advantageous for automotive applications, since in addition to high reliability low costs are an important objective here. Since IGBTs are characterized by dominant turn-off losses and generally higher switching losses compared to MOSFETs, the aim is to operate them with zero-current switching (ZCS) and at low switching frequencies below the resonance frequency. In this region also the voltage transfer characteristic is steeper, which qualifies for applications with a strongly varying input-to-output voltage ratio, such as given for automotive on-board DC-DC converters connecting the (high-voltage) traction battery with the (12 V) auxiliary battery. In this paper, a stress value analysis based on a switched-model simulation is used to design a ZCS LLC converter and take advantage of the mentioned benefits of IGBTs as well as of the steeper voltage transfer characteristic. Within this operation region below the resonance frequency, however, a new phenomenon of several current pulses occurring during a single switching period through the rectifier components may appear. Generally, in applications with high output currents a synchronous rectifier (SR) is often used to keep the conduction losses of the rectifier stage at a moderate level: Low-voltage MOSFETs, which actively need to be gated synchronously to the polarity of the current pulses, are employed then instead of more lossy rectifier diodes. However, standard SR driver ICs have been shown to be unable to properly rectify the multi-pulse output currents of the proposed LLC operation, resulting in high conduction losses of the rectifier stage. A cost-effective hardware concept is presented which ensures proper rectification by using standard SR-ICs that are actively overdriven by the converter’s central microcontroller. A 2 kW prototype for an EV on-board DC-DC converter was built to show the effectiveness of the method, documenting an increase in efficiency by up to 4.1 % compared to a purely SR-IC-based solution. Overall efficiency is very similar to that of a conventional (MOSFET-based) LLC converter so that the ZCS-operated LLC IGBT-converter represents a cost-effective alternative, which even shows 10 % less worst-case losses."}],"publication_status":"published","status":"public","date_created":"2023-08-02T11:27:32Z","author":[{"id":"60223","last_name":"Urbaneck","full_name":"Urbaneck, Daniel","first_name":"Daniel"},{"full_name":"Schafmeister, Frank","first_name":"Frank","last_name":"Schafmeister"},{"first_name":"Joachim","full_name":"Böcker, Joachim","last_name":"Böcker"}],"keyword":["LLC Converter","IGBT","ZCS","Synchronous Rectification"],"publication":"PCIM Europe 2023"},{"title":"Computing and Compressing Electron Repulsion Integrals on FPGAs","user_id":"75963","abstract":[{"text":"The computation of electron repulsion integrals (ERIs) over Gaussian-type orbitals (GTOs) is a challenging problem in quantum-mechanics-based atomistic simulations. In practical simulations, several trillions of ERIs may have to be\r\ncomputed for every time step.\r\nIn this work, we investigate FPGAs as accelerators for the ERI computation. We use template parameters, here within the Intel oneAPI tool flow, to create customized designs for 256 different ERI quartet classes, based on their orbitals. To maximize data reuse, all intermediates are buffered in FPGA on-chip memory with customized layout. The pre-calculation of intermediates also helps to overcome data dependencies caused by multi-dimensional recurrence\r\nrelations. The involved loop structures are partially or even fully unrolled for high throughput of FPGA kernels. Furthermore, a lossy compression algorithm utilizing arbitrary bitwidth integers is integrated in the FPGA kernels. To our\r\nbest knowledge, this is the first work on ERI computation on FPGAs that supports more than just the single most basic quartet class. Also, the integration of ERI computation and compression it a novelty that is not even covered by CPU or GPU libraries so far.\r\nOur evaluation shows that using 16-bit integer for the ERI compression, the fastest FPGA kernels exceed the performance of 10 GERIS ($10 \\times 10^9$ ERIs per second) on one Intel Stratix 10 GX 2800 FPGA, with maximum absolute errors around $10^{-7}$ - $10^{-5}$ Hartree. The measured throughput can be accurately explained by a performance model. The FPGA kernels deployed on 2 FPGAs outperform similar computations using the widely used libint reference on a two-socket server with 40 Xeon Gold 6148 CPU cores of the same process technology by factors up to 6.0x and on a new two-socket server with 128 EPYC 7713 CPU cores by up to 1.9x.","lang":"eng"}],"external_id":{"arxiv":["2303.13632"]},"date_created":"2023-03-30T11:15:40Z","project":[{"name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"status":"public","publication":"2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)","department":[{"_id":"27"},{"_id":"518"}],"author":[{"full_name":"Wu, Xin","first_name":"Xin","id":"77439","last_name":"Wu"},{"full_name":"Kenter, Tobias","first_name":"Tobias","id":"3145","last_name":"Kenter"},{"id":"75963","last_name":"Schade","orcid":"0000-0002-6268-539","full_name":"Schade, Robert","first_name":"Robert"},{"full_name":"Kühne, Thomas","first_name":"Thomas","id":"49079","last_name":"Kühne"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"quality_controlled":"1","doi":"10.1109/FCCM57271.2023.00026","date_updated":"2023-08-02T15:05:42Z","_id":"43228","page":"162-173","type":"conference","citation":{"chicago":"Wu, Xin, Tobias Kenter, Robert Schade, Thomas Kühne, and Christian Plessl. “Computing and Compressing Electron Repulsion Integrals on FPGAs.” In 2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 162–73, 2023. https://doi.org/10.1109/FCCM57271.2023.00026.","short":"X. Wu, T. Kenter, R. Schade, T. Kühne, C. Plessl, in: 2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2023, pp. 162–173.","ama":"Wu X, Kenter T, Schade R, Kühne T, Plessl C. Computing and Compressing Electron Repulsion Integrals on FPGAs. In: 2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). ; 2023:162-173. doi:10.1109/FCCM57271.2023.00026","apa":"Wu, X., Kenter, T., Schade, R., Kühne, T., & Plessl, C. (2023). Computing and Compressing Electron Repulsion Integrals on FPGAs. 2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 162–173. https://doi.org/10.1109/FCCM57271.2023.00026","bibtex":"@inproceedings{Wu_Kenter_Schade_Kühne_Plessl_2023, title={Computing and Compressing Electron Repulsion Integrals on FPGAs}, DOI={10.1109/FCCM57271.2023.00026}, booktitle={2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)}, author={Wu, Xin and Kenter, Tobias and Schade, Robert and Kühne, Thomas and Plessl, Christian}, year={2023}, pages={162–173} }","mla":"Wu, Xin, et al. “Computing and Compressing Electron Repulsion Integrals on FPGAs.” 2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2023, pp. 162–73, doi:10.1109/FCCM57271.2023.00026.","ieee":"X. Wu, T. Kenter, R. Schade, T. Kühne, and C. Plessl, “Computing and Compressing Electron Repulsion Integrals on FPGAs,” in 2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2023, pp. 162–173, doi: 10.1109/FCCM57271.2023.00026."},"year":"2023","language":[{"iso":"eng"}],"main_file_link":[{"url":"https://ieeexplore.ieee.org/document/10171537"}]}]