{"citation":{"apa":"Vaz, G. F., Riebler, H., Kenter, T., &#38; Plessl, C. (2016). Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code. <i>Computers and Electrical Engineering</i>, <i>55</i>, 91–111. <a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.021\">https://doi.org/10.1016/j.compeleceng.2016.04.021</a>","mla":"Vaz, Gavin Francis, et al. “Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code.” <i>Computers and Electrical Engineering</i>, vol. 55, Elsevier, 2016, pp. 91–111, doi:<a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.021\">10.1016/j.compeleceng.2016.04.021</a>.","ama":"Vaz GF, Riebler H, Kenter T, Plessl C. Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code. <i>Computers and Electrical Engineering</i>. 2016;55:91-111. doi:<a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.021\">10.1016/j.compeleceng.2016.04.021</a>","ieee":"G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code,” <i>Computers and Electrical Engineering</i>, vol. 55, pp. 91–111, 2016, doi: <a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.021\">10.1016/j.compeleceng.2016.04.021</a>.","chicago":"Vaz, Gavin Francis, Heinrich Riebler, Tobias Kenter, and Christian Plessl. “Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code.” <i>Computers and Electrical Engineering</i> 55 (2016): 91–111. <a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.021\">https://doi.org/10.1016/j.compeleceng.2016.04.021</a>.","short":"G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, Computers and Electrical Engineering 55 (2016) 91–111.","bibtex":"@article{Vaz_Riebler_Kenter_Plessl_2016, title={Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code}, volume={55}, DOI={<a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.021\">10.1016/j.compeleceng.2016.04.021</a>}, journal={Computers and Electrical Engineering}, publisher={Elsevier}, author={Vaz, Gavin Francis and Riebler, Heinrich and Kenter, Tobias and Plessl, Christian}, year={2016}, pages={91–111} }"},"user_id":"15278","volume":55,"publication_identifier":{"issn":["0045-7906"]},"department":[{"_id":"27"},{"_id":"518"}],"_id":"165","title":"Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code","author":[{"first_name":"Gavin Francis","full_name":"Vaz, Gavin Francis","last_name":"Vaz","id":"30332"},{"full_name":"Riebler, Heinrich","id":"8961","last_name":"Riebler","first_name":"Heinrich"},{"first_name":"Tobias","last_name":"Kenter","id":"3145","full_name":"Kenter, Tobias"},{"orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl","full_name":"Plessl, Christian"}],"publisher":"Elsevier","year":"2016","intvolume":"        55","status":"public","publication":"Computers and Electrical Engineering","date_updated":"2023-09-26T13:26:38Z","type":"journal_article","language":[{"iso":"eng"}],"date_created":"2017-10-17T12:41:24Z","file_date_updated":"2018-03-21T12:45:47Z","abstract":[{"text":"A broad spectrum of applications can be accelerated by offloading computation intensive parts to reconfigurable hardware. However, to achieve speedups, the number of loop it- erations (trip count) needs to be sufficiently large to amortize offloading overheads. Trip counts are frequently not known at compile time, but only at runtime just before entering a loop. Therefore, we propose to generate code for both the CPU and the coprocessor, and defer the offloading decision to the application runtime. We demonstrate how a toolflow, based on the LLVM compiler framework, can automatically embed dynamic offloading de- cisions into the application code. We perform in-depth static and dynamic analysis of pop- ular benchmarks, which confirm the general potential of such an approach. We also pro- pose to optimize the offloading process by decoupling the runtime decision from the loop execution (decision slack). The feasibility of our approach is demonstrated by a toolflow that automatically identifies suitable data-parallel loops and generates code for the FPGA coprocessor of a Convey HC-1. We evaluate the integrated toolflow with representative loops executed for different input data sizes.","lang":"eng"}],"quality_controlled":"1","has_accepted_license":"1","project":[{"grant_number":"160364472","_id":"1","name":"SFB 901"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34","grant_number":"610996"}],"file":[{"relation":"main_file","access_level":"closed","content_type":"application/pdf","creator":"florida","file_size":3037854,"date_created":"2018-03-21T12:45:47Z","date_updated":"2018-03-21T12:45:47Z","success":1,"file_name":"165-1-s2.0-S0045790616301021-main.pdf","file_id":"1544"}],"page":"91-111","doi":"10.1016/j.compeleceng.2016.04.021","ddc":["040"]}