{"file":[{"success":1,"date_created":"2018-11-02T15:27:04Z","creator":"ups","date_updated":"2018-11-02T15:27:04Z","relation":"main_file","file_size":523362,"access_level":"closed","content_type":"application/pdf","file_name":"08053741.pdf","file_id":"5303"}],"year":"2018","author":[{"last_name":"Isenberg","full_name":"Isenberg, Tobias","first_name":"Tobias"},{"first_name":"Marie-Christine","last_name":"Jakobs","full_name":"Jakobs, Marie-Christine"},{"id":"22398","first_name":"Felix","last_name":"Pauck","full_name":"Pauck, Felix"},{"id":"573","last_name":"Wehrheim","full_name":"Wehrheim, Heike","first_name":"Heike"}],"publication_identifier":{"issn":["1943-0663","1943-0671"]},"language":[{"iso":"eng"}],"_id":"1043","type":"journal_article","file_date_updated":"2018-11-02T15:27:04Z","publisher":"Institute of Electrical and Electronics Engineers (IEEE)","date_updated":"2022-01-06T06:50:39Z","department":[{"_id":"77"}],"user_id":"477","has_accepted_license":"1","status":"public","date_created":"2017-12-11T16:11:00Z","citation":{"ieee":"T. Isenberg, M.-C. Jakobs, F. Pauck, and H. Wehrheim, “Validity of Software Verification Results on Approximate Hardware,” <i>IEEE Embedded Systems Letters</i>, pp. 22–25, 2018.","mla":"Isenberg, Tobias, et al. “Validity of Software Verification Results on Approximate Hardware.” <i>IEEE Embedded Systems Letters</i>, Institute of Electrical and Electronics Engineers (IEEE), 2018, pp. 22–25, doi:<a href=\"https://doi.org/10.1109/LES.2017.2758200\">10.1109/LES.2017.2758200</a>.","bibtex":"@article{Isenberg_Jakobs_Pauck_Wehrheim_2018, title={Validity of Software Verification Results on Approximate Hardware}, DOI={<a href=\"https://doi.org/10.1109/LES.2017.2758200\">10.1109/LES.2017.2758200</a>}, journal={IEEE Embedded Systems Letters}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Isenberg, Tobias and Jakobs, Marie-Christine and Pauck, Felix and Wehrheim, Heike}, year={2018}, pages={22–25} }","apa":"Isenberg, T., Jakobs, M.-C., Pauck, F., &#38; Wehrheim, H. (2018). Validity of Software Verification Results on Approximate Hardware. <i>IEEE Embedded Systems Letters</i>, 22–25. <a href=\"https://doi.org/10.1109/LES.2017.2758200\">https://doi.org/10.1109/LES.2017.2758200</a>","short":"T. Isenberg, M.-C. Jakobs, F. Pauck, H. Wehrheim, IEEE Embedded Systems Letters (2018) 22–25.","chicago":"Isenberg, Tobias, Marie-Christine Jakobs, Felix Pauck, and Heike Wehrheim. “Validity of Software Verification Results on Approximate Hardware.” <i>IEEE Embedded Systems Letters</i>, 2018, 22–25. <a href=\"https://doi.org/10.1109/LES.2017.2758200\">https://doi.org/10.1109/LES.2017.2758200</a>.","ama":"Isenberg T, Jakobs M-C, Pauck F, Wehrheim H. Validity of Software Verification Results on Approximate Hardware. <i>IEEE Embedded Systems Letters</i>. 2018:22-25. doi:<a href=\"https://doi.org/10.1109/LES.2017.2758200\">10.1109/LES.2017.2758200</a>"},"doi":"10.1109/LES.2017.2758200","publication_status":"published","publication":"IEEE Embedded Systems Letters","project":[{"name":"SFB 901","_id":"1"},{"_id":"3","name":"SFB 901 - Project Area B"},{"_id":"12","name":"SFB 901 - Subproject B4"}],"title":"Validity of Software Verification Results on Approximate Hardware","page":"22-25","abstract":[{"text":"Approximate computing (AC) is an emerging paradigm for energy-efficient computation. The basic idea of AC is to sacrifice high precision for low energy by allowing hardware to carry out “approximately correct” calculations. This provides a major challenge for software quality assurance: programs successfully verified to be correct might be erroneous on approximate hardware. In this letter, we present a novel approach for determining under what conditions a software verification result is valid for approximate hardware. To this end, we compute the allowed tolerances for AC hardware from successful verification runs. More precisely, we derive a set of constraints which—when met by the AC hardware—guarantees the verification result to carry over to AC. On the practical side, we furthermore: 1) show how to extract tolerances from verification runs employing predicate abstraction as verification technology and 2) show how to check such constraints on hardware designs. We have implemented all techniques, and exemplify them on example C programs and a number of recently proposed approximate adders.","lang":"eng"}],"ddc":["000"]}