Microarchitectural optimization by means of reconfigurable and evolvable cache mappings Ho, Nam Ahmed, Abdullah Fathi Kaufmann, Paul Platzner, Marco cache storage field programmable gate arrays multiprocessing systems parallel architectures reconfigurable architectures FPGA dynamic reconfiguration evolvable cache mapping many-core architecture memory-to-cache address mapping function microarchitectural optimization multicore architecture nature-inspired optimization parallelization degrees processor reconfigurable cache mapping reconfigurable computing Field programmable gate arrays Software Tuning 2015 info:eu-repo/semantics/conferenceObject doc-type:conferenceObject text http://purl.org/coar/resource_type/c_5794 https://ris.uni-paderborn.de/record/10673 Ho N, Ahmed AF, Kaufmann P, Platzner M. Microarchitectural optimization by means of reconfigurable and evolvable cache mappings. In: <i>Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)</i>. ; 2015:1-7. doi:<a href="https://doi.org/10.1109/AHS.2015.7231178">10.1109/AHS.2015.7231178</a> eng info:eu-repo/semantics/altIdentifier/doi/10.1109/AHS.2015.7231178 info:eu-repo/grantAgreement/EC/257906 info:eu-repo/semantics/closedAccess