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<titleInfo><title>Microarchitectural optimization by means of reconfigurable and evolvable cache mappings</title></titleInfo>





<name type="personal">
  <namePart type="given">Nam</namePart>
  <namePart type="family">Ho</namePart>
  <role><roleTerm type="text">author</roleTerm> </role></name>
<name type="personal">
  <namePart type="given">Abdullah Fathi</namePart>
  <namePart type="family">Ahmed</namePart>
  <role><roleTerm type="text">author</roleTerm> </role></name>
<name type="personal">
  <namePart type="given">Paul</namePart>
  <namePart type="family">Kaufmann</namePart>
  <role><roleTerm type="text">author</roleTerm> </role></name>
<name type="personal">
  <namePart type="given">Marco</namePart>
  <namePart type="family">Platzner</namePart>
  <role><roleTerm type="text">author</roleTerm> </role><identifier type="local">398</identifier></name>







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  <identifier type="local">78</identifier>
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  <namePart>Engineering Proprioception in Computing Systems</namePart>
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<originInfo><dateIssued encoding="w3cdtf">2015</dateIssued>
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<language><languageTerm authority="iso639-2b" type="code">eng</languageTerm>
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<subject><topic>cache storage</topic><topic>field programmable gate arrays</topic><topic>multiprocessing systems</topic><topic>parallel architectures</topic><topic>reconfigurable architectures</topic><topic>FPGA</topic><topic>dynamic reconfiguration</topic><topic>evolvable cache mapping</topic><topic>many-core architecture</topic><topic>memory-to-cache address mapping function</topic><topic>microarchitectural optimization</topic><topic>multicore architecture</topic><topic>nature-inspired optimization</topic><topic>parallelization degrees</topic><topic>processor</topic><topic>reconfigurable cache mapping</topic><topic>reconfigurable computing</topic><topic>Field programmable gate arrays</topic><topic>Software</topic><topic>Tuning</topic>
</subject>


<relatedItem type="host"><titleInfo><title>Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)</title></titleInfo><identifier type="doi">10.1109/AHS.2015.7231178</identifier>
<part><extent unit="pages">1-7</extent>
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<short>N. Ho, A.F. Ahmed, P. Kaufmann, M. Platzner, in: Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 2015, pp. 1–7.</short>
<bibtex>@inproceedings{Ho_Ahmed_Kaufmann_Platzner_2015, title={Microarchitectural optimization by means of reconfigurable and evolvable cache mappings}, DOI={&lt;a href=&quot;https://doi.org/10.1109/AHS.2015.7231178&quot;&gt;10.1109/AHS.2015.7231178&lt;/a&gt;}, booktitle={Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)}, author={Ho, Nam and Ahmed, Abdullah Fathi and Kaufmann, Paul and Platzner, Marco}, year={2015}, pages={1–7} }</bibtex>
<mla>Ho, Nam, et al. “Microarchitectural Optimization by Means of Reconfigurable and Evolvable Cache Mappings.” &lt;i&gt;Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)&lt;/i&gt;, 2015, pp. 1–7, doi:&lt;a href=&quot;https://doi.org/10.1109/AHS.2015.7231178&quot;&gt;10.1109/AHS.2015.7231178&lt;/a&gt;.</mla>
<apa>Ho, N., Ahmed, A. F., Kaufmann, P., &amp;#38; Platzner, M. (2015). Microarchitectural optimization by means of reconfigurable and evolvable cache mappings. In &lt;i&gt;Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)&lt;/i&gt; (pp. 1–7). &lt;a href=&quot;https://doi.org/10.1109/AHS.2015.7231178&quot;&gt;https://doi.org/10.1109/AHS.2015.7231178&lt;/a&gt;</apa>
<ieee>N. Ho, A. F. Ahmed, P. Kaufmann, and M. Platzner, “Microarchitectural optimization by means of reconfigurable and evolvable cache mappings,” in &lt;i&gt;Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)&lt;/i&gt;, 2015, pp. 1–7.</ieee>
<chicago>Ho, Nam, Abdullah Fathi Ahmed, Paul Kaufmann, and Marco Platzner. “Microarchitectural Optimization by Means of Reconfigurable and Evolvable Cache Mappings.” In &lt;i&gt;Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)&lt;/i&gt;, 1–7, 2015. &lt;a href=&quot;https://doi.org/10.1109/AHS.2015.7231178&quot;&gt;https://doi.org/10.1109/AHS.2015.7231178&lt;/a&gt;.</chicago>
<ama>Ho N, Ahmed AF, Kaufmann P, Platzner M. Microarchitectural optimization by means of reconfigurable and evolvable cache mappings. In: &lt;i&gt;Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)&lt;/i&gt;. ; 2015:1-7. doi:&lt;a href=&quot;https://doi.org/10.1109/AHS.2015.7231178&quot;&gt;10.1109/AHS.2015.7231178&lt;/a&gt;</ama>
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