{"status":"public","citation":{"short":"J. Anwer, M. Platzner, in: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), IEEE, 2014, pp. 177–184.","apa":"Anwer, J., &#38; Platzner, M. (2014). Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs. In <i>IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)</i> (pp. 177–184). IEEE. <a href=\"https://doi.org/10.1109/DFT.2014.6962108\">https://doi.org/10.1109/DFT.2014.6962108</a>","mla":"Anwer, Jahanzeb, and Marco Platzner. “Analytic Reliability Evaluation for Fault-Tolerant Circuit Structures on FPGAs.” <i>IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)</i>, IEEE, 2014, pp. 177–84, doi:<a href=\"https://doi.org/10.1109/DFT.2014.6962108\">10.1109/DFT.2014.6962108</a>.","ama":"Anwer J, Platzner M. Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs. In: <i>IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)</i>. IEEE; 2014:177-184. doi:<a href=\"https://doi.org/10.1109/DFT.2014.6962108\">10.1109/DFT.2014.6962108</a>","bibtex":"@inproceedings{Anwer_Platzner_2014, title={Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs}, DOI={<a href=\"https://doi.org/10.1109/DFT.2014.6962108\">10.1109/DFT.2014.6962108</a>}, booktitle={IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)}, publisher={IEEE}, author={Anwer, Jahanzeb and Platzner, Marco}, year={2014}, pages={177–184} }","ieee":"J. Anwer and M. Platzner, “Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs,” in <i>IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)</i>, 2014, pp. 177–184.","chicago":"Anwer, Jahanzeb, and Marco Platzner. “Analytic Reliability Evaluation for Fault-Tolerant Circuit Structures on FPGAs.” In <i>IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)</i>, 177–84. IEEE, 2014. <a href=\"https://doi.org/10.1109/DFT.2014.6962108\">https://doi.org/10.1109/DFT.2014.6962108</a>."},"title":"Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs","author":[{"first_name":"Jahanzeb","full_name":"Anwer, Jahanzeb","last_name":"Anwer"},{"first_name":"Marco","last_name":"Platzner","id":"398","full_name":"Platzner, Marco"}],"department":[{"_id":"78"}],"publication":"IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","publisher":"IEEE","date_updated":"2022-01-06T06:50:50Z","page":"177-184","type":"conference","year":"2014","date_created":"2019-07-10T12:07:05Z","language":[{"iso":"eng"}],"_id":"10764","user_id":"398","doi":"10.1109/DFT.2014.6962108"}