{"language":[{"iso":"eng"}],"year":"2015","date_updated":"2022-01-06T06:50:50Z","extern":"1","page":"1117-1126","department":[{"_id":"78"}],"title":"From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires","status":"public","volume":14,"intvolume":"        14","citation":{"bibtex":"@article{Ghasemzadeh Mohammadi_Gaillardon_De Micheli_2015, title={From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires}, volume={14}, DOI={<a href=\"https://doi.org/10.1109/TNANO.2015.2482359\">10.1109/TNANO.2015.2482359</a>}, number={6}, journal={IEEE Transactions on Nanotechnology}, publisher={IEEE}, author={Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and De Micheli, Giovanni}, year={2015}, pages={1117–1126} }","short":"H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, G. De Micheli, IEEE Transactions on Nanotechnology 14 (2015) 1117–1126.","mla":"Ghasemzadeh Mohammadi, Hassan, et al. “From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires.” <i>IEEE Transactions on Nanotechnology</i>, vol. 14, no. 6, IEEE, 2015, pp. 1117–26, doi:<a href=\"https://doi.org/10.1109/TNANO.2015.2482359\">10.1109/TNANO.2015.2482359</a>.","ieee":"H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, and G. De Micheli, “From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires,” <i>IEEE Transactions on Nanotechnology</i>, vol. 14, no. 6, pp. 1117–1126, 2015.","chicago":"Ghasemzadeh Mohammadi, Hassan, Pierre-Emmanuel Gaillardon, and Giovanni De Micheli. “From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires.” <i>IEEE Transactions on Nanotechnology</i> 14, no. 6 (2015): 1117–26. <a href=\"https://doi.org/10.1109/TNANO.2015.2482359\">https://doi.org/10.1109/TNANO.2015.2482359</a>.","apa":"Ghasemzadeh Mohammadi, H., Gaillardon, P.-E., &#38; De Micheli, G. (2015). From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires. <i>IEEE Transactions on Nanotechnology</i>, <i>14</i>(6), 1117–1126. <a href=\"https://doi.org/10.1109/TNANO.2015.2482359\">https://doi.org/10.1109/TNANO.2015.2482359</a>","ama":"Ghasemzadeh Mohammadi H, Gaillardon P-E, De Micheli G. From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires. <i>IEEE Transactions on Nanotechnology</i>. 2015;14(6):1117-1126. doi:<a href=\"https://doi.org/10.1109/TNANO.2015.2482359\">10.1109/TNANO.2015.2482359</a>"},"publisher":"IEEE","date_created":"2019-07-10T12:08:15Z","author":[{"full_name":"Ghasemzadeh Mohammadi, Hassan","first_name":"Hassan","id":"61186","last_name":"Ghasemzadeh Mohammadi"},{"full_name":"Gaillardon, Pierre-Emmanuel","first_name":"Pierre-Emmanuel","last_name":"Gaillardon"},{"last_name":"De Micheli","first_name":"Giovanni","full_name":"De Micheli, Giovanni"}],"user_id":"3118","publication":"IEEE Transactions on Nanotechnology","type":"journal_article","_id":"10770","issue":"6","doi":"10.1109/TNANO.2015.2482359"}