article Hassan Ghasemzadeh Mohammadi author 61186 Pierre-Emmanuel Gaillardon author Giovanni De Micheli author 78 department IEEE2015 eng 10.1109/TNANO.2015.2482359 1461117-1126 yes Ghasemzadeh Mohammadi, Hassan, et al. “From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires.” <i>IEEE Transactions on Nanotechnology</i>, vol. 14, no. 6, IEEE, 2015, pp. 1117–26, doi:<a href="https://doi.org/10.1109/TNANO.2015.2482359">10.1109/TNANO.2015.2482359</a>. H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, G. De Micheli, IEEE Transactions on Nanotechnology 14 (2015) 1117–1126. @article{Ghasemzadeh Mohammadi_Gaillardon_De Micheli_2015, title={From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires}, volume={14}, DOI={<a href="https://doi.org/10.1109/TNANO.2015.2482359">10.1109/TNANO.2015.2482359</a>}, number={6}, journal={IEEE Transactions on Nanotechnology}, publisher={IEEE}, author={Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and De Micheli, Giovanni}, year={2015}, pages={1117–1126} } Ghasemzadeh Mohammadi, H., Gaillardon, P.-E., &#38; De Micheli, G. (2015). From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires. <i>IEEE Transactions on Nanotechnology</i>, <i>14</i>(6), 1117–1126. <a href="https://doi.org/10.1109/TNANO.2015.2482359">https://doi.org/10.1109/TNANO.2015.2482359</a> Ghasemzadeh Mohammadi H, Gaillardon P-E, De Micheli G. From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires. <i>IEEE Transactions on Nanotechnology</i>. 2015;14(6):1117-1126. doi:<a href="https://doi.org/10.1109/TNANO.2015.2482359">10.1109/TNANO.2015.2482359</a> H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, and G. De Micheli, “From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires,” <i>IEEE Transactions on Nanotechnology</i>, vol. 14, no. 6, pp. 1117–1126, 2015. Ghasemzadeh Mohammadi, Hassan, Pierre-Emmanuel Gaillardon, and Giovanni De Micheli. “From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires.” <i>IEEE Transactions on Nanotechnology</i> 14, no. 6 (2015): 1117–26. <a href="https://doi.org/10.1109/TNANO.2015.2482359">https://doi.org/10.1109/TNANO.2015.2482359</a>. 107702019-07-10T12:08:15Z2022-01-06T06:50:50Z