{"date_updated":"2022-01-06T06:50:50Z","page":"1-6","language":[{"iso":"eng"}],"publication":"2013 14th Latin American Test Workshop-LATW","extern":"1","title":"Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study","author":[{"full_name":"Gaillardon, Pierre-Emmanuel","last_name":"Gaillardon","first_name":"Pierre-Emmanuel"},{"full_name":"Ghasemzadeh Mohammadi, Hassan","last_name":"Ghasemzadeh Mohammadi","first_name":"Hassan","id":"61186"},{"first_name":"Giovanni","last_name":"De Micheli","full_name":"De Micheli, Giovanni"}],"year":"2013","user_id":"3118","_id":"10775","status":"public","doi":"10.1109/LATW.2013.6562673","date_created":"2019-07-10T12:10:18Z","department":[{"_id":"78"}],"citation":{"chicago":"Gaillardon, Pierre-Emmanuel, Hassan Ghasemzadeh Mohammadi, and Giovanni De Micheli. “Vertically-Stacked Silicon Nanowire Transistors with Controllable Polarity: A Robustness Study.” In <i>2013 14th Latin American Test Workshop-LATW</i>, 1–6. IEEE, 2013. <a href=\"https://doi.org/10.1109/LATW.2013.6562673\">https://doi.org/10.1109/LATW.2013.6562673</a>.","mla":"Gaillardon, Pierre-Emmanuel, et al. “Vertically-Stacked Silicon Nanowire Transistors with Controllable Polarity: A Robustness Study.” <i>2013 14th Latin American Test Workshop-LATW</i>, IEEE, 2013, pp. 1–6, doi:<a href=\"https://doi.org/10.1109/LATW.2013.6562673\">10.1109/LATW.2013.6562673</a>.","apa":"Gaillardon, P.-E., Ghasemzadeh Mohammadi, H., &#38; De Micheli, G. (2013). Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study. In <i>2013 14th Latin American Test Workshop-LATW</i> (pp. 1–6). IEEE. <a href=\"https://doi.org/10.1109/LATW.2013.6562673\">https://doi.org/10.1109/LATW.2013.6562673</a>","short":"P.-E. Gaillardon, H. Ghasemzadeh Mohammadi, G. De Micheli, in: 2013 14th Latin American Test Workshop-LATW, IEEE, 2013, pp. 1–6.","ama":"Gaillardon P-E, Ghasemzadeh Mohammadi H, De Micheli G. Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study. In: <i>2013 14th Latin American Test Workshop-LATW</i>. IEEE; 2013:1-6. doi:<a href=\"https://doi.org/10.1109/LATW.2013.6562673\">10.1109/LATW.2013.6562673</a>","ieee":"P.-E. Gaillardon, H. Ghasemzadeh Mohammadi, and G. De Micheli, “Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study,” in <i>2013 14th Latin American Test Workshop-LATW</i>, 2013, pp. 1–6.","bibtex":"@inproceedings{Gaillardon_Ghasemzadeh Mohammadi_De Micheli_2013, title={Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study}, DOI={<a href=\"https://doi.org/10.1109/LATW.2013.6562673\">10.1109/LATW.2013.6562673</a>}, booktitle={2013 14th Latin American Test Workshop-LATW}, publisher={IEEE}, author={Gaillardon, Pierre-Emmanuel and Ghasemzadeh Mohammadi, Hassan and De Micheli, Giovanni}, year={2013}, pages={1–6} }"},"publisher":"IEEE","type":"conference"}