{"department":[{"_id":"48"}],"doi":"10.1109/ddecs.2007.4295278","language":[{"iso":"eng"}],"citation":{"ieee":"P. Oehler, S. Hellebrand, and H.-J. Wunderlich, “Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair,” in <i>10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07)</i>, 2007, pp. 185–190, doi: <a href=\"https://doi.org/10.1109/ddecs.2007.4295278\">10.1109/ddecs.2007.4295278</a>.","bibtex":"@inproceedings{Oehler_Hellebrand_Wunderlich_2007, place={Krakow, Poland}, title={Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair}, DOI={<a href=\"https://doi.org/10.1109/ddecs.2007.4295278\">10.1109/ddecs.2007.4295278</a>}, booktitle={10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07)}, publisher={IEEE}, author={Oehler, Philipp and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2007}, pages={185–190} }","short":"P. Oehler, S. Hellebrand, H.-J. Wunderlich, in: 10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07), IEEE, Krakow, Poland, 2007, pp. 185–190.","chicago":"Oehler, Philipp, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair.” In <i>10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07)</i>, 185–90. Krakow, Poland: IEEE, 2007. <a href=\"https://doi.org/10.1109/ddecs.2007.4295278\">https://doi.org/10.1109/ddecs.2007.4295278</a>.","mla":"Oehler, Philipp, et al. “Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair.” <i>10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07)</i>, IEEE, 2007, pp. 185–90, doi:<a href=\"https://doi.org/10.1109/ddecs.2007.4295278\">10.1109/ddecs.2007.4295278</a>.","ama":"Oehler P, Hellebrand S, Wunderlich H-J. Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair. In: <i>10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07)</i>. IEEE; 2007:185-190. doi:<a href=\"https://doi.org/10.1109/ddecs.2007.4295278\">10.1109/ddecs.2007.4295278</a>","apa":"Oehler, P., Hellebrand, S., &#38; Wunderlich, H.-J. (2007). Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair. <i>10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS’07)</i>, 185–190. <a href=\"https://doi.org/10.1109/ddecs.2007.4295278\">https://doi.org/10.1109/ddecs.2007.4295278</a>"},"place":"Krakow, Poland","year":"2007","_id":"12996","publication":"10th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'07)","publisher":"IEEE","date_created":"2019-08-28T10:19:52Z","status":"public","author":[{"last_name":"Oehler","first_name":"Philipp","full_name":"Oehler, Philipp"},{"id":"209","last_name":"Hellebrand","first_name":"Sybille","orcid":"0000-0002-3717-3939","full_name":"Hellebrand, Sybille"},{"first_name":"Hans-Joachim","last_name":"Wunderlich","full_name":"Wunderlich, Hans-Joachim"}],"page":"185-190","type":"conference","user_id":"209","date_updated":"2022-05-11T16:34:43Z","title":"Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair"}