Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers Hellebrand, Sybille Rajski, Janusz Tarnick, Steffen Venkataraman, Srikanth Courtois, B. IEEE 1995 info:eu-repo/semantics/article doc-type:article text http://purl.org/coar/resource_type/c_6501 https://ris.uni-paderborn.de/record/13011 Hellebrand S, Rajski J, Tarnick S, Venkataraman S, Courtois B. Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers. <i>IEEE Transactions on Computers</i>. 1995;44(2):223-233. doi:<a href="https://doi.org/10.1109/12.364534">10.1109/12.364534</a> eng info:eu-repo/semantics/altIdentifier/doi/10.1109/12.364534 info:eu-repo/semantics/closedAccess