{"author":[{"last_name":"Sommer","full_name":"Sommer, Lukas","first_name":"Lukas"},{"first_name":"Julian","full_name":"Oppermann, Julian","last_name":"Oppermann"},{"last_name":"Molina","full_name":"Molina, Alejandro","first_name":"Alejandro"},{"first_name":"Carsten","last_name":"Binnig","full_name":"Binnig, Carsten"},{"first_name":"Kristian","full_name":"Kersting, Kristian","last_name":"Kersting"},{"last_name":"Koch","full_name":"Koch, Andreas","first_name":"Andreas"}],"keyword":["pc2-harp-ressources"],"title":"Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-Based Accelerators","status":"public","citation":{"chicago":"Sommer, Lukas, Julian Oppermann, Alejandro Molina, Carsten Binnig, Kristian Kersting, and Andreas Koch. “Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-Based Accelerators.” In 2018 IEEE 36th International Conference on Computer Design (ICCD), 2019. https://doi.org/10.1109/iccd.2018.00060.","ieee":"L. Sommer, J. Oppermann, A. Molina, C. Binnig, K. Kersting, and A. Koch, “Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-Based Accelerators,” in 2018 IEEE 36th International Conference on Computer Design (ICCD), 2019.","ama":"Sommer L, Oppermann J, Molina A, Binnig C, Kersting K, Koch A. Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-Based Accelerators. In: 2018 IEEE 36th International Conference on Computer Design (ICCD). ; 2019. doi:10.1109/iccd.2018.00060","bibtex":"@inproceedings{Sommer_Oppermann_Molina_Binnig_Kersting_Koch_2019, title={Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-Based Accelerators}, DOI={10.1109/iccd.2018.00060}, booktitle={2018 IEEE 36th International Conference on Computer Design (ICCD)}, author={Sommer, Lukas and Oppermann, Julian and Molina, Alejandro and Binnig, Carsten and Kersting, Kristian and Koch, Andreas}, year={2019} }","apa":"Sommer, L., Oppermann, J., Molina, A., Binnig, C., Kersting, K., & Koch, A. (2019). Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-Based Accelerators. In 2018 IEEE 36th International Conference on Computer Design (ICCD). https://doi.org/10.1109/iccd.2018.00060","short":"L. Sommer, J. Oppermann, A. Molina, C. Binnig, K. Kersting, A. Koch, in: 2018 IEEE 36th International Conference on Computer Design (ICCD), 2019.","mla":"Sommer, Lukas, et al. “Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-Based Accelerators.” 2018 IEEE 36th International Conference on Computer Design (ICCD), 2019, doi:10.1109/iccd.2018.00060."},"publication_status":"published","publication":"2018 IEEE 36th International Conference on Computer Design (ICCD)","abstract":[{"lang":"eng","text":"In recent years, FPGAs have been successfully employed for the implementation of efficient, application-specific accelerators for a wide range of machine learning tasks. In this work, we consider probabilistic models, namely, (Mixed) Sum-Product Networks (SPN), a deep architecture that can provide tractable inference for multivariate distributions over mixed data-sources. We develop a fully pipelined FPGA accelerator architecture, including a pipelined interface to external memory, for the inference in (mixed) SPNs. To meet the precision constraints of SPNs, all computations are conducted using double-precision floating point arithmetic. Starting from an input description, the custom FPGA-accelerator is synthesized fully automatically by our tool flow. To the best of our knowledge, this work is the first approach to offload the SPN inference problem to FPGA-based accelerators. Our evaluation shows that the SPN inference problem benefits from offloading to our pipelined FPGA accelerator architecture."}],"publication_identifier":{"isbn":["9781538684771"]},"year":"2019","type":"conference","date_updated":"2022-01-06T06:52:50Z","doi":"10.1109/iccd.2018.00060","date_created":"2020-04-06T10:33:58Z","language":[{"iso":"eng"}],"_id":"16413","user_id":"61189"}