{"date_created":"2020-04-06T10:33:58Z","title":"Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-Based Accelerators","publication":"2018 IEEE 36th International Conference on Computer Design (ICCD)","type":"conference","year":"2019","_id":"16413","language":[{"iso":"eng"}],"publication_identifier":{"isbn":["9781538684771"]},"status":"public","author":[{"full_name":"Sommer, Lukas","last_name":"Sommer","first_name":"Lukas"},{"full_name":"Oppermann, Julian","last_name":"Oppermann","first_name":"Julian"},{"first_name":"Alejandro","last_name":"Molina","full_name":"Molina, Alejandro"},{"full_name":"Binnig, Carsten","last_name":"Binnig","first_name":"Carsten"},{"first_name":"Kristian","last_name":"Kersting","full_name":"Kersting, Kristian"},{"last_name":"Koch","full_name":"Koch, Andreas","first_name":"Andreas"}],"date_updated":"2022-01-06T06:52:50Z","publication_status":"published","doi":"10.1109/iccd.2018.00060","abstract":[{"lang":"eng","text":"In recent years, FPGAs have been successfully employed for the implementation of efficient, application-specific accelerators for a wide range of machine learning tasks. In this work, we consider probabilistic models, namely, (Mixed) Sum-Product Networks (SPN), a deep architecture that can provide tractable inference for multivariate distributions over mixed data-sources. We develop a fully pipelined FPGA accelerator architecture, including a pipelined interface to external memory, for the inference in (mixed) SPNs. To meet the precision constraints of SPNs, all computations are conducted using double-precision floating point arithmetic. Starting from an input description, the custom FPGA-accelerator is synthesized fully automatically by our tool flow. To the best of our knowledge, this work is the first approach to offload the SPN inference problem to FPGA-based accelerators. Our evaluation shows that the SPN inference problem benefits from offloading to our pipelined FPGA accelerator architecture."}],"user_id":"61189","citation":{"ama":"Sommer L, Oppermann J, Molina A, Binnig C, Kersting K, Koch A. Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-Based Accelerators. In: <i>2018 IEEE 36th International Conference on Computer Design (ICCD)</i>. ; 2019. doi:<a href=\"https://doi.org/10.1109/iccd.2018.00060\">10.1109/iccd.2018.00060</a>","bibtex":"@inproceedings{Sommer_Oppermann_Molina_Binnig_Kersting_Koch_2019, title={Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-Based Accelerators}, DOI={<a href=\"https://doi.org/10.1109/iccd.2018.00060\">10.1109/iccd.2018.00060</a>}, booktitle={2018 IEEE 36th International Conference on Computer Design (ICCD)}, author={Sommer, Lukas and Oppermann, Julian and Molina, Alejandro and Binnig, Carsten and Kersting, Kristian and Koch, Andreas}, year={2019} }","chicago":"Sommer, Lukas, Julian Oppermann, Alejandro Molina, Carsten Binnig, Kristian Kersting, and Andreas Koch. “Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-Based Accelerators.” In <i>2018 IEEE 36th International Conference on Computer Design (ICCD)</i>, 2019. <a href=\"https://doi.org/10.1109/iccd.2018.00060\">https://doi.org/10.1109/iccd.2018.00060</a>.","short":"L. Sommer, J. Oppermann, A. Molina, C. Binnig, K. Kersting, A. Koch, in: 2018 IEEE 36th International Conference on Computer Design (ICCD), 2019.","ieee":"L. Sommer, J. Oppermann, A. Molina, C. Binnig, K. Kersting, and A. Koch, “Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-Based Accelerators,” in <i>2018 IEEE 36th International Conference on Computer Design (ICCD)</i>, 2019.","apa":"Sommer, L., Oppermann, J., Molina, A., Binnig, C., Kersting, K., &#38; Koch, A. (2019). Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-Based Accelerators. In <i>2018 IEEE 36th International Conference on Computer Design (ICCD)</i>. <a href=\"https://doi.org/10.1109/iccd.2018.00060\">https://doi.org/10.1109/iccd.2018.00060</a>","mla":"Sommer, Lukas, et al. “Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-Based Accelerators.” <i>2018 IEEE 36th International Conference on Computer Design (ICCD)</i>, 2019, doi:<a href=\"https://doi.org/10.1109/iccd.2018.00060\">10.1109/iccd.2018.00060</a>."},"keyword":["pc2-harp-ressources"]}