---
res:
  bibo_abstract:
  - The advent of FPGA-based hybrid architecture offers the opportunity of customizing
    memory subsystems to enhance the overall system performance. However, it is not
    straightforward to design efficient FPGA circuits for emerging FPGAs applications
    such as in-memory database and graph analytics, which heavily depend on concurrent
    data structures (CDS'). Highly dynamic behaviors of CDS' have to be orchestrated
    by synchronization primitives for correct execution. These primitives induce overwhelming
    memory traffic for synchronizations on FPGAs. This paper proposes a novel method
    for systematically exploring and exploiting memory-level parallelism (MLP) of
    CDS by transactional execution on FPGAs. Inspired by the idea that semantics of
    transactions can be implemented in a more efficient and scalable manner on FPGAs
    than on CPUs, we propose a transaction-based reconfigurable runtime system for
    capturing MLP of CDS'. Experiments on linked-list and skip-list show our approach
    achieves 5.18x and 1.55x throughput improvement on average than lock-based FPGA
    implementations and optimized CDS algorithms on a state-of-the-art multi-core
    CPU respectively.@eng
  bibo_authorlist:
  - foaf_Person:
      foaf_givenName: Zhaoshi
      foaf_name: Li, Zhaoshi
      foaf_surname: Li
  - foaf_Person:
      foaf_givenName: Leibo
      foaf_name: Liu, Leibo
      foaf_surname: Liu
  - foaf_Person:
      foaf_givenName: Yangdong
      foaf_name: Deng, Yangdong
      foaf_surname: Deng
  - foaf_Person:
      foaf_givenName: Shouyi
      foaf_name: Yin, Shouyi
      foaf_surname: Yin
  - foaf_Person:
      foaf_givenName: Shaojun
      foaf_name: Wei, Shaojun
      foaf_surname: Wei
  bibo_doi: 10.1109/lca.2018.2828402
  dct_date: 2018^xs_gYear
  dct_isPartOf:
  - http://id.crossref.org/issn/1556-6056
  - http://id.crossref.org/issn/1556-6064
  - http://id.crossref.org/issn/2473-2575
  dct_language: eng
  dct_subject:
  - pc2-harp-ressources
  dct_title: Breaking the Synchronization Bottleneck with Reconfigurable Transactional
    Execution@
...