--- res: bibo_abstract: - ' Field-Programmable Gate Arrays (FPGAs) are widely used in the central signal processing design of the Square Kilometer Array (SKA) as hardware accelerators. The frequency domain acceleration search (FDAS) module is an important part of the SKA1-MID pulsar search engine. To develop for a yet to be finalized hardware, for cross-discipline interoperability and to achieve fast prototyping, OpenCL as a high-level FPGA synthesis approaches employed to create the sub-modules of FDAS. The FT convolution and the harmonic-summing plus some other minor sub-modules are elements in the FDAS module that have been well-optimized separately before. In this paper, we explore the design space of combining well-optimized designs, dealing with the ensuing need to trade-off and compromise. Pipeline computing is employed to handle multiple input arrays at high speed. The hardware target is to employ multiple high-end FPGAs to process the combined FDAS module. The results show interesting consequences, where the best individual solutions are not necessarily the best solutions for the speed of a pipeline where FPGA resources and memory bandwidth need to be shared. By proposing multiple buffering techniques to the pipeline, the combined FDAS module can achieve up to 2[Formula: see text] speedup over implementations without pipeline computing. We perform an extensive experimental evaluation on multiple high-end FPGA cards hosted in a workstation and compare to a technology comparable mid-range GPU. @eng' bibo_authorlist: - foaf_Person: foaf_givenName: Haomiao foaf_name: Wang, Haomiao foaf_surname: Wang - foaf_Person: foaf_givenName: Prabu foaf_name: Thiagaraj, Prabu foaf_surname: Thiagaraj - foaf_Person: foaf_givenName: Oliver foaf_name: Sinnen, Oliver foaf_surname: Sinnen bibo_doi: 10.1142/s2251171719500089 dct_date: 2019^xs_gYear dct_isPartOf: - http://id.crossref.org/issn/2251-1717 - http://id.crossref.org/issn/2251-1725 dct_language: eng dct_subject: - pc2-harp-ressources dct_title: Combining Multiple Optimized FPGA-based Pulsar Search Modules Using OpenCL@ ...