{"publication":"The Journal of Supercomputing","citation":{"bibtex":"@article{Rodríguez_Navarro_Asenjo_Corbera_Gran_Suárez_Nunez-Yanez_2019, title={Parallel multiprocessing and scheduling on the heterogeneous Xeon+FPGA platform}, DOI={<a href=\"https://doi.org/10.1007/s11227-019-02935-1\">10.1007/s11227-019-02935-1</a>}, journal={The Journal of Supercomputing}, author={Rodríguez, Andrés and Navarro, Angeles and Asenjo, Rafael and Corbera, Francisco and Gran, Rubén and Suárez, Darío and Nunez-Yanez, Jose}, year={2019} }","apa":"Rodríguez, A., Navarro, A., Asenjo, R., Corbera, F., Gran, R., Suárez, D., &#38; Nunez-Yanez, J. (2019). Parallel multiprocessing and scheduling on the heterogeneous Xeon+FPGA platform. <i>The Journal of Supercomputing</i>. <a href=\"https://doi.org/10.1007/s11227-019-02935-1\">https://doi.org/10.1007/s11227-019-02935-1</a>","short":"A. Rodríguez, A. Navarro, R. Asenjo, F. Corbera, R. Gran, D. Suárez, J. Nunez-Yanez, The Journal of Supercomputing (2019).","mla":"Rodríguez, Andrés, et al. “Parallel Multiprocessing and Scheduling on the Heterogeneous Xeon+FPGA Platform.” <i>The Journal of Supercomputing</i>, 2019, doi:<a href=\"https://doi.org/10.1007/s11227-019-02935-1\">10.1007/s11227-019-02935-1</a>.","ieee":"A. Rodríguez <i>et al.</i>, “Parallel multiprocessing and scheduling on the heterogeneous Xeon+FPGA platform,” <i>The Journal of Supercomputing</i>, 2019.","ama":"Rodríguez A, Navarro A, Asenjo R, et al. Parallel multiprocessing and scheduling on the heterogeneous Xeon+FPGA platform. <i>The Journal of Supercomputing</i>. 2019. doi:<a href=\"https://doi.org/10.1007/s11227-019-02935-1\">10.1007/s11227-019-02935-1</a>","chicago":"Rodríguez, Andrés, Angeles Navarro, Rafael Asenjo, Francisco Corbera, Rubén Gran, Darío Suárez, and Jose Nunez-Yanez. “Parallel Multiprocessing and Scheduling on the Heterogeneous Xeon+FPGA Platform.” <i>The Journal of Supercomputing</i>, 2019. <a href=\"https://doi.org/10.1007/s11227-019-02935-1\">https://doi.org/10.1007/s11227-019-02935-1</a>."},"_id":"16423","user_id":"61189","year":"2019","author":[{"last_name":"Rodríguez","full_name":"Rodríguez, Andrés","first_name":"Andrés"},{"full_name":"Navarro, Angeles","last_name":"Navarro","first_name":"Angeles"},{"full_name":"Asenjo, Rafael","last_name":"Asenjo","first_name":"Rafael"},{"full_name":"Corbera, Francisco","last_name":"Corbera","first_name":"Francisco"},{"first_name":"Rubén","full_name":"Gran, Rubén","last_name":"Gran"},{"first_name":"Darío","last_name":"Suárez","full_name":"Suárez, Darío"},{"first_name":"Jose","last_name":"Nunez-Yanez","full_name":"Nunez-Yanez, Jose"}],"publication_identifier":{"issn":["0920-8542","1573-0484"]},"title":"Parallel multiprocessing and scheduling on the heterogeneous Xeon+FPGA platform","keyword":["pc2-harp-ressources"],"abstract":[{"lang":"eng","text":"Heterogeneous computing that exploits simultaneous co-processing with different device types has been shown to be effective at both increasing performance and reducing energy consumption. In this paper, we extend a scheduling framework encapsulated in a high-level C++ template and previously developed for heterogeneous chips comprising CPU and GPU cores, to new high-performance platforms for the data center, which include a cache coherent FPGA fabric and many-core CPU resources. Our goal is to evaluate the suitability of our framework with these new FPGA-based platforms, identifying performance benefits and limitations.We target the state-of-the-art HARP processor that includes 14 high-end Xeon classes tightly coupled to a FPGA device located in the same package. We select eight benchmarks from the high-performance computing domain that have been ported and optimized for this heterogeneous platform. The results show that a dynamic and adaptive scheduler that exploits simultaneous processing among the devices can improve performance up to a factor of 8 × compared to the best alternative solutions that only use the CPU cores or the FPGA fabric. Moreover, our proposal achieves up to 15% and 37% of improvement compared to the best heterogeneous solutions found with a dynamic and static schedulers, respectively."}],"language":[{"iso":"eng"}],"date_created":"2020-04-06T12:09:25Z","publication_status":"published","status":"public","doi":"10.1007/s11227-019-02935-1","type":"journal_article","date_updated":"2022-01-06T06:52:50Z"}