[{"publication_status":"published","_id":"16524","title":"Multiobjective optimization for transistor sizing of CMOS logic standard cells using set-oriented numerical techniques","doi":"10.1109/norchp.2009.5397800","author":[{"full_name":"Blesken, Matthias","last_name":"Blesken","first_name":"Matthias"},{"full_name":"Ruckert, Ulrich","last_name":"Ruckert","first_name":"Ulrich"},{"last_name":"Steenken","first_name":"Dominik","full_name":"Steenken, Dominik"},{"full_name":"Witting, Katrin","last_name":"Witting","first_name":"Katrin"},{"first_name":"Michael","last_name":"Dellnitz","full_name":"Dellnitz, Michael"}],"language":[{"iso":"eng"}],"date_updated":"2020-05-14T09:01:34Z","publication_identifier":{"isbn":["9781424443109","9781424443116"]},"publication":"2009 NORCHIP","user_id":"15701","citation":{"short":"M. Blesken, U. Ruckert, D. Steenken, K. Witting, M. Dellnitz, in: 2009 NORCHIP, 2009.","chicago":"Blesken, Matthias, Ulrich Ruckert, Dominik Steenken, Katrin Witting, and Michael Dellnitz. “Multiobjective Optimization for Transistor Sizing of CMOS Logic Standard Cells Using Set-Oriented Numerical Techniques.” In <i>2009 NORCHIP</i>, 2009. <a href=\"https://doi.org/10.1109/norchp.2009.5397800\">https://doi.org/10.1109/norchp.2009.5397800</a>.","ieee":"M. Blesken, U. Ruckert, D. Steenken, K. Witting, and M. Dellnitz, “Multiobjective optimization for transistor sizing of CMOS logic standard cells using set-oriented numerical techniques,” in <i>2009 NORCHIP</i>, 2009.","bibtex":"@inproceedings{Blesken_Ruckert_Steenken_Witting_Dellnitz_2009, title={Multiobjective optimization for transistor sizing of CMOS logic standard cells using set-oriented numerical techniques}, DOI={<a href=\"https://doi.org/10.1109/norchp.2009.5397800\">10.1109/norchp.2009.5397800</a>}, booktitle={2009 NORCHIP}, author={Blesken, Matthias and Ruckert, Ulrich and Steenken, Dominik and Witting, Katrin and Dellnitz, Michael}, year={2009} }","ama":"Blesken M, Ruckert U, Steenken D, Witting K, Dellnitz M. Multiobjective optimization for transistor sizing of CMOS logic standard cells using set-oriented numerical techniques. In: <i>2009 NORCHIP</i>. ; 2009. doi:<a href=\"https://doi.org/10.1109/norchp.2009.5397800\">10.1109/norchp.2009.5397800</a>","mla":"Blesken, Matthias, et al. “Multiobjective Optimization for Transistor Sizing of CMOS Logic Standard Cells Using Set-Oriented Numerical Techniques.” <i>2009 NORCHIP</i>, 2009, doi:<a href=\"https://doi.org/10.1109/norchp.2009.5397800\">10.1109/norchp.2009.5397800</a>.","apa":"Blesken, M., Ruckert, U., Steenken, D., Witting, K., &#38; Dellnitz, M. (2009). Multiobjective optimization for transistor sizing of CMOS logic standard cells using set-oriented numerical techniques. In <i>2009 NORCHIP</i>. <a href=\"https://doi.org/10.1109/norchp.2009.5397800\">https://doi.org/10.1109/norchp.2009.5397800</a>"},"year":"2009","department":[{"_id":"101"}],"status":"public","type":"conference","date_created":"2020-04-15T08:11:10Z"}]