{"date_created":"2020-09-15T14:03:02Z","publication":"IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020","place":"Virtual Conference - Originally Frascati (Rome), Italy","type":"conference","title":"Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study","author":[{"full_name":"Sprenger, Alexander","last_name":"Sprenger","first_name":"Alexander","id":"22707"},{"first_name":"Somayeh","id":"78614","last_name":"Sadeghi-Kohan","full_name":"Sadeghi-Kohan, Somayeh"},{"last_name":"Reimer","full_name":"Reimer, Jan Dennis","id":"36703","first_name":"Jan Dennis"},{"first_name":"Sybille","id":"209","orcid":"0000-0002-3717-3939","last_name":"Hellebrand","full_name":"Hellebrand, Sybille"}],"department":[{"_id":"48"}],"user_id":"209","_id":"19422","conference":{"end_date":"2020-10-21","start_date":"2020-10-19"},"language":[{"iso":"eng"}],"status":"public","publication_status":"published","date_updated":"2022-02-19T14:16:58Z","year":"2020","citation":{"ama":"Sprenger A, Sadeghi-Kohan S, Reimer JD, Hellebrand S. Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study. In: <i>IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020</i>. ; 2020.","apa":"Sprenger, A., Sadeghi-Kohan, S., Reimer, J. D., &#38; Hellebrand, S. (2020). Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study. <i>IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020</i>.","chicago":"Sprenger, Alexander, Somayeh Sadeghi-Kohan, Jan Dennis Reimer, and Sybille Hellebrand. “Variation-Aware Test for Logic Interconnects Using Neural Networks - A Case Study.” In <i>IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020</i>. Virtual Conference - Originally Frascati (Rome), Italy, 2020.","mla":"Sprenger, Alexander, et al. “Variation-Aware Test for Logic Interconnects Using Neural Networks - A Case Study.” <i>IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020</i>, 2020.","bibtex":"@inproceedings{Sprenger_Sadeghi-Kohan_Reimer_Hellebrand_2020, place={Virtual Conference - Originally Frascati (Rome), Italy}, title={Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study}, booktitle={IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020}, author={Sprenger, Alexander and Sadeghi-Kohan, Somayeh and Reimer, Jan Dennis and Hellebrand, Sybille}, year={2020} }","ieee":"A. Sprenger, S. Sadeghi-Kohan, J. D. Reimer, and S. Hellebrand, “Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study,” 2020.","short":"A. Sprenger, S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, in: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020, Virtual Conference - Originally Frascati (Rome), Italy, 2020."}}