{"page":"189-196","file":[{"creator":"fossie","file_size":2148787,"date_updated":"2019-02-13T09:04:46Z","date_created":"2019-02-13T09:04:46Z","relation":"main_file","access_level":"closed","content_type":"application/pdf","file_name":"2012-11 Meyer,Schumacher,Plessl,Förstner_Convey vector personalities-FPGA acceleratin with an openmp-like programming effort.pdf","file_id":"7638","success":1}],"doi":"10.1109/FPL.2012.6339370","ddc":["000"],"date_created":"2018-03-29T15:04:25Z","file_date_updated":"2019-02-13T09:04:46Z","keyword":["funding-upb-forschungspreis","funding-maxup","tet_topic_hpc"],"quality_controlled":"1","abstract":[{"lang":"eng","text":"Although the benefits of FPGAs for accelerating scientific codes are widely acknowledged, the use of FPGA accelerators in scientific computing is not widespread because reaping these benefits requires knowledge of hardware design methods and tools that is typically not available with domain scientists. A promising but hardly investigated approach is to develop tool flows that keep the common languages for scientific code (C,C++, and Fortran) and allow the developer to augment the source code with OpenMPlike directives for instructing the compiler which parts of the application shall be offloaded the FPGA accelerator.\r\nIn this work we study whether the promise of effective FPGA acceleration with an OpenMP-like programming effort\r\ncan actually be held. Our target system is the Convey HC-1 reconfigurable computer for which an OpenMP-like\r\nprogramming environment exists. As case study we use an application from computational nanophotonics. Our results\r\nshow that a developer without previous FPGA experience could create an FPGA-accelerated application that is competitive to an optimized OpenMP-parallelized CPU version running on a two socket quad-core server. Finally, we discuss our experiences with this tool flow and the Convey HC-1 from a productivity and economic point of view."}],"has_accepted_license":"1","publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","conference":{"name":"22nd International Conference on Field Programmable Logic and Applicaitons (FPL)"},"type":"conference","date_updated":"2023-09-26T13:39:13Z","language":[{"iso":"eng"}],"citation":{"short":"B. Meyer, J. Schumacher, C. Plessl, J. Förstner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 189–196.","chicago":"Meyer, Björn, Jörn Schumacher, Christian Plessl, and Jens Förstner. “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?” In <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 189–96. IEEE, 2012. <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">https://doi.org/10.1109/FPL.2012.6339370</a>.","bibtex":"@inproceedings{Meyer_Schumacher_Plessl_Förstner_2012, title={Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?}, DOI={<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Meyer, Björn and Schumacher, Jörn and Plessl, Christian and Förstner, Jens}, year={2012}, pages={189–196} }","apa":"Meyer, B., Schumacher, J., Plessl, C., &#38; Förstner, J. (2012). Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 189–196. <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">https://doi.org/10.1109/FPL.2012.6339370</a>","mla":"Meyer, Björn, et al. “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?” <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, IEEE, 2012, pp. 189–96, doi:<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>.","ama":"Meyer B, Schumacher J, Plessl C, Förstner J. Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? In: <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>. IEEE; 2012:189-196. doi:<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>","ieee":"B. Meyer, J. Schumacher, C. Plessl, and J. Förstner, “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?,” in <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 2012, pp. 189–196, doi: <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>."},"user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"15"},{"_id":"78"}],"_id":"2106","title":"Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?","publisher":"IEEE","author":[{"last_name":"Meyer","full_name":"Meyer, Björn","first_name":"Björn"},{"last_name":"Schumacher","full_name":"Schumacher, Jörn","first_name":"Jörn"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153","full_name":"Plessl, Christian"},{"orcid":"0000-0001-7059-9862","first_name":"Jens","full_name":"Förstner, Jens","id":"158","last_name":"Förstner"}],"status":"public","year":"2012"}